1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the top level entry point for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 // Get the target-independent interfaces which we are implementing.
16 include "llvm/Target/Target.td"
18 //===----------------------------------------------------------------------===//
19 // PowerPC Subtarget features.
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
35 def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
36 def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
37 def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
39 "PPC::DIR_E500mc", "">;
40 def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective",
41 "PPC::DIR_E5500", "">;
42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
49 def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">;
51 def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
52 "Enable 64-bit instructions">;
53 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
54 "Enable 64-bit registers usage for ppc32 [beta]">;
55 def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true",
56 "Use condition-register bits individually">;
57 def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
58 "Enable Altivec instructions">;
59 def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
60 "Enable the MFOCRF instruction">;
61 def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
62 "Enable the fsqrt instruction">;
63 def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
64 "Enable the fcpsgn instruction">;
65 def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true",
66 "Enable the fre instruction">;
67 def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true",
68 "Enable the fres instruction">;
69 def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
70 "Enable the frsqrte instruction">;
71 def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
72 "Enable the frsqrtes instruction">;
73 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
74 "Assume higher precision reciprocal estimates">;
75 def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
76 "Enable the stfiwx instruction">;
77 def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
78 "Enable the lfiwax instruction">;
79 def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true",
80 "Enable the fri[mnpz] instructions">;
81 def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
82 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
83 def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
84 "Enable the isel instruction">;
85 def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
86 "Enable the popcnt[dw] instructions">;
87 def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true",
88 "Enable the ldbrx instruction">;
89 def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
90 "Enable Book E instructions">;
91 def FeatureE500 : SubtargetFeature<"E500", "IsE500", "true",
92 "Enable E500/E500mc instructions">;
93 def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
94 "Enable PPC 4xx instructions">;
95 def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
96 "Enable PPC 6xx instructions">;
97 def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
98 "Enable QPX instructions">;
99 def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true",
100 "Enable VSX instructions",
103 def DeprecatedMFTB : SubtargetFeature<"", "DeprecatedMFTB", "true",
104 "Treat mftb as deprecated">;
105 def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true",
106 "Treat vector data stream cache control instructions as deprecated">;
108 // Note: Future features to add when support is extended to more
109 // recent ISA levels:
111 // CMPB p6, p6x, p7 cmpb
112 // DFP p6, p6x, p7 decimal floating-point instructions
113 // POPCNTB p5 through p7 popcntb and related instructions
114 // VSX p7 vector-scalar instruction set
116 //===----------------------------------------------------------------------===//
118 //===----------------------------------------------------------------------===//
120 def FeatureELFv1 : SubtargetFeature<"elfv1", "TargetABI", "PPC_ABI_ELFv1",
121 "Use the ELFv1 ABI">;
123 def FeatureELFv2 : SubtargetFeature<"elfv2", "TargetABI", "PPC_ABI_ELFv2",
124 "Use the ELFv2 ABI">;
126 //===----------------------------------------------------------------------===//
127 // Classes used for relation maps.
128 //===----------------------------------------------------------------------===//
129 // RecFormRel - Filter class used to relate non-record-form instructions with
130 // their record-form variants.
133 // AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
134 // FMA instruction forms with their corresponding factor-killing forms.
139 //===----------------------------------------------------------------------===//
140 // Relation Map Definitions.
141 //===----------------------------------------------------------------------===//
143 def getRecordFormOpcode : InstrMapping {
144 let FilterClass = "RecFormRel";
145 // Instructions with the same BaseName and Interpretation64Bit values
147 let RowFields = ["BaseName", "Interpretation64Bit"];
148 // Instructions with the same RC value form a column.
149 let ColFields = ["RC"];
150 // The key column are the non-record-form instructions.
152 // Value columns RC=1
153 let ValueCols = [["1"]];
156 def getNonRecordFormOpcode : InstrMapping {
157 let FilterClass = "RecFormRel";
158 // Instructions with the same BaseName and Interpretation64Bit values
160 let RowFields = ["BaseName", "Interpretation64Bit"];
161 // Instructions with the same RC value form a column.
162 let ColFields = ["RC"];
163 // The key column are the record-form instructions.
165 // Value columns are RC=0
166 let ValueCols = [["0"]];
169 def getAltVSXFMAOpcode : InstrMapping {
170 let FilterClass = "AltVSXFMARel";
171 // Instructions with the same BaseName and Interpretation64Bit values
173 let RowFields = ["BaseName"];
174 // Instructions with the same RC value form a column.
175 let ColFields = ["IsVSXFMAAlt"];
176 // The key column are the (default) addend-killing instructions.
178 // Value columns IsVSXFMAAlt=1
179 let ValueCols = [["1"]];
182 //===----------------------------------------------------------------------===//
183 // Register File Description
184 //===----------------------------------------------------------------------===//
186 include "PPCRegisterInfo.td"
187 include "PPCSchedule.td"
188 include "PPCInstrInfo.td"
190 //===----------------------------------------------------------------------===//
191 // PowerPC processors supported.
194 def : Processor<"generic", G3Itineraries, [Directive32]>;
195 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
196 FeatureFRES, FeatureFRSQRTE,
197 FeatureBookE, DeprecatedMFTB]>;
198 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
199 FeatureFRES, FeatureFRSQRTE,
200 FeatureBookE, DeprecatedMFTB]>;
201 def : Processor<"601", G3Itineraries, [Directive601]>;
202 def : Processor<"602", G3Itineraries, [Directive602]>;
203 def : Processor<"603", G3Itineraries, [Directive603,
204 FeatureFRES, FeatureFRSQRTE]>;
205 def : Processor<"603e", G3Itineraries, [Directive603,
206 FeatureFRES, FeatureFRSQRTE]>;
207 def : Processor<"603ev", G3Itineraries, [Directive603,
208 FeatureFRES, FeatureFRSQRTE]>;
209 def : Processor<"604", G3Itineraries, [Directive604,
210 FeatureFRES, FeatureFRSQRTE]>;
211 def : Processor<"604e", G3Itineraries, [Directive604,
212 FeatureFRES, FeatureFRSQRTE]>;
213 def : Processor<"620", G3Itineraries, [Directive620,
214 FeatureFRES, FeatureFRSQRTE]>;
215 def : Processor<"750", G4Itineraries, [Directive750,
216 FeatureFRES, FeatureFRSQRTE]>;
217 def : Processor<"g3", G3Itineraries, [Directive750,
218 FeatureFRES, FeatureFRSQRTE]>;
219 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
220 FeatureFRES, FeatureFRSQRTE]>;
221 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
222 FeatureFRES, FeatureFRSQRTE]>;
223 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
224 FeatureFRES, FeatureFRSQRTE]>;
225 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
226 FeatureFRES, FeatureFRSQRTE]>;
227 def : ProcessorModel<"970", G5Model,
228 [Directive970, FeatureAltivec,
229 FeatureMFOCRF, FeatureFSqrt,
230 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
231 Feature64Bit /*, Feature64BitRegs */]>;
232 def : ProcessorModel<"g5", G5Model,
233 [Directive970, FeatureAltivec,
234 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
235 FeatureFRES, FeatureFRSQRTE,
236 Feature64Bit /*, Feature64BitRegs */,
237 DeprecatedMFTB, DeprecatedDST]>;
238 def : ProcessorModel<"e500mc", PPCE500mcModel,
239 [DirectiveE500mc, FeatureMFOCRF,
240 FeatureSTFIWX, FeatureBookE, FeatureISEL,
242 def : ProcessorModel<"e5500", PPCE5500Model,
243 [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
244 FeatureSTFIWX, FeatureBookE, FeatureISEL,
246 def : ProcessorModel<"a2", PPCA2Model,
247 [DirectiveA2, FeatureBookE, FeatureMFOCRF,
248 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
249 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
250 FeatureSTFIWX, FeatureLFIWAX,
251 FeatureFPRND, FeatureFPCVT, FeatureISEL,
252 FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
253 /*, Feature64BitRegs */, DeprecatedMFTB]>;
254 def : ProcessorModel<"a2q", PPCA2Model,
255 [DirectiveA2, FeatureBookE, FeatureMFOCRF,
256 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
257 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
258 FeatureSTFIWX, FeatureLFIWAX,
259 FeatureFPRND, FeatureFPCVT, FeatureISEL,
260 FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
261 /*, Feature64BitRegs */, FeatureQPX, DeprecatedMFTB]>;
262 def : ProcessorModel<"pwr3", G5Model,
263 [DirectivePwr3, FeatureAltivec,
264 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
265 FeatureSTFIWX, Feature64Bit]>;
266 def : ProcessorModel<"pwr4", G5Model,
267 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
268 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
269 FeatureSTFIWX, Feature64Bit]>;
270 def : ProcessorModel<"pwr5", G5Model,
271 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
272 FeatureFSqrt, FeatureFRE, FeatureFRES,
273 FeatureFRSQRTE, FeatureFRSQRTES,
274 FeatureSTFIWX, Feature64Bit,
275 DeprecatedMFTB, DeprecatedDST]>;
276 def : ProcessorModel<"pwr5x", G5Model,
277 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
278 FeatureFSqrt, FeatureFRE, FeatureFRES,
279 FeatureFRSQRTE, FeatureFRSQRTES,
280 FeatureSTFIWX, FeatureFPRND, Feature64Bit,
281 DeprecatedMFTB, DeprecatedDST]>;
282 def : ProcessorModel<"pwr6", G5Model,
283 [DirectivePwr6, FeatureAltivec,
284 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
285 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
286 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
287 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
288 DeprecatedMFTB, DeprecatedDST]>;
289 def : ProcessorModel<"pwr6x", G5Model,
290 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
291 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
292 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
293 FeatureSTFIWX, FeatureLFIWAX,
294 FeatureFPRND, Feature64Bit,
295 DeprecatedMFTB, DeprecatedDST]>;
296 def : ProcessorModel<"pwr7", P7Model,
297 [DirectivePwr7, FeatureAltivec,
298 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
299 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
300 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
301 FeatureFPRND, FeatureFPCVT, FeatureISEL,
302 FeaturePOPCNTD, FeatureLDBRX,
303 Feature64Bit /*, Feature64BitRegs */,
304 DeprecatedMFTB, DeprecatedDST]>;
305 def : ProcessorModel<"pwr8", P7Model /* FIXME: Update to P8Model when available */,
306 [DirectivePwr8, FeatureAltivec,
307 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
308 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
309 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
310 FeatureFPRND, FeatureFPCVT, FeatureISEL,
311 FeaturePOPCNTD, FeatureLDBRX,
312 Feature64Bit /*, Feature64BitRegs */,
313 DeprecatedMFTB, DeprecatedDST]>;
314 def : Processor<"ppc", G3Itineraries, [Directive32]>;
315 def : ProcessorModel<"ppc64", G5Model,
316 [Directive64, FeatureAltivec,
317 FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
318 FeatureFRSQRTE, FeatureSTFIWX,
319 Feature64Bit /*, Feature64BitRegs */]>;
320 def : ProcessorModel<"ppc64le", G5Model,
321 [Directive64, FeatureAltivec,
322 FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
323 FeatureFRSQRTE, FeatureSTFIWX,
324 Feature64Bit /*, Feature64BitRegs */]>;
326 //===----------------------------------------------------------------------===//
327 // Calling Conventions
328 //===----------------------------------------------------------------------===//
330 include "PPCCallingConv.td"
332 def PPCInstrInfo : InstrInfo {
333 let isLittleEndianEncoding = 1;
335 // FIXME: Unset this when no longer needed!
336 let decodePositionallyEncodedOperands = 1;
338 let noNamedPositionallyEncodedOperands = 1;
341 def PPCAsmParser : AsmParser {
342 let ShouldEmitMatchRegisterName = 0;
345 def PPCAsmParserVariant : AsmParserVariant {
348 // We do not use hard coded registers in asm strings. However, some
349 // InstAlias definitions use immediate literals. Set RegisterPrefix
350 // so that those are not misinterpreted as registers.
351 string RegisterPrefix = "%";
355 // Information about the instructions.
356 let InstructionSet = PPCInstrInfo;
358 let AssemblyParsers = [PPCAsmParser];
359 let AssemblyParserVariants = [PPCAsmParserVariant];