1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the top level entry point for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 // Get the target-independent interfaces which we are implementing.
16 include "llvm/Target/Target.td"
18 //===----------------------------------------------------------------------===//
19 // PowerPC Subtarget features.
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
35 def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
36 def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
37 def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
39 "PPC::DIR_E500mc", "">;
40 def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective",
41 "PPC::DIR_E5500", "">;
42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
49 def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">;
51 def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
52 "Enable 64-bit instructions">;
53 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
54 "Enable 64-bit registers usage for ppc32 [beta]">;
55 def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true",
56 "Use condition-register bits individually">;
57 def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
58 "Enable Altivec instructions">;
59 def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
60 "Enable the MFOCRF instruction">;
61 def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
62 "Enable the fsqrt instruction">;
63 def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
64 "Enable the fcpsgn instruction">;
65 def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true",
66 "Enable the fre instruction">;
67 def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true",
68 "Enable the fres instruction">;
69 def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
70 "Enable the frsqrte instruction">;
71 def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
72 "Enable the frsqrtes instruction">;
73 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
74 "Assume higher precision reciprocal estimates">;
75 def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
76 "Enable the stfiwx instruction">;
77 def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
78 "Enable the lfiwax instruction">;
79 def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true",
80 "Enable the fri[mnpz] instructions">;
81 def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
82 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
83 def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
84 "Enable the isel instruction">;
85 def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
86 "Enable the popcnt[dw] instructions">;
87 def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true",
88 "Enable the ldbrx instruction">;
89 def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
90 "Enable Book E instructions">;
91 def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
92 "Enable QPX instructions">;
93 def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true",
94 "Enable VSX instructions",
97 def DeprecatedMFTB : SubtargetFeature<"", "DeprecatedMFTB", "true",
98 "Treat mftb as deprecated">;
99 def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true",
100 "Treat vector data stream cache control instructions as deprecated">;
102 // Note: Future features to add when support is extended to more
103 // recent ISA levels:
105 // CMPB p6, p6x, p7 cmpb
106 // DFP p6, p6x, p7 decimal floating-point instructions
107 // POPCNTB p5 through p7 popcntb and related instructions
108 // VSX p7 vector-scalar instruction set
110 //===----------------------------------------------------------------------===//
112 //===----------------------------------------------------------------------===//
114 def FeatureELFv1 : SubtargetFeature<"elfv1", "TargetABI", "PPC_ABI_ELFv1",
115 "Use the ELFv1 ABI">;
117 def FeatureELFv2 : SubtargetFeature<"elfv2", "TargetABI", "PPC_ABI_ELFv2",
118 "Use the ELFv2 ABI">;
120 //===----------------------------------------------------------------------===//
121 // Classes used for relation maps.
122 //===----------------------------------------------------------------------===//
123 // RecFormRel - Filter class used to relate non-record-form instructions with
124 // their record-form variants.
127 // AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
128 // FMA instruction forms with their corresponding factor-killing forms.
133 //===----------------------------------------------------------------------===//
134 // Relation Map Definitions.
135 //===----------------------------------------------------------------------===//
137 def getRecordFormOpcode : InstrMapping {
138 let FilterClass = "RecFormRel";
139 // Instructions with the same BaseName and Interpretation64Bit values
141 let RowFields = ["BaseName", "Interpretation64Bit"];
142 // Instructions with the same RC value form a column.
143 let ColFields = ["RC"];
144 // The key column are the non-record-form instructions.
146 // Value columns RC=1
147 let ValueCols = [["1"]];
150 def getNonRecordFormOpcode : InstrMapping {
151 let FilterClass = "RecFormRel";
152 // Instructions with the same BaseName and Interpretation64Bit values
154 let RowFields = ["BaseName", "Interpretation64Bit"];
155 // Instructions with the same RC value form a column.
156 let ColFields = ["RC"];
157 // The key column are the record-form instructions.
159 // Value columns are RC=0
160 let ValueCols = [["0"]];
163 def getAltVSXFMAOpcode : InstrMapping {
164 let FilterClass = "AltVSXFMARel";
165 // Instructions with the same BaseName and Interpretation64Bit values
167 let RowFields = ["BaseName"];
168 // Instructions with the same RC value form a column.
169 let ColFields = ["IsVSXFMAAlt"];
170 // The key column are the (default) addend-killing instructions.
172 // Value columns IsVSXFMAAlt=1
173 let ValueCols = [["1"]];
176 //===----------------------------------------------------------------------===//
177 // Register File Description
178 //===----------------------------------------------------------------------===//
180 include "PPCRegisterInfo.td"
181 include "PPCSchedule.td"
182 include "PPCInstrInfo.td"
184 //===----------------------------------------------------------------------===//
185 // PowerPC processors supported.
188 def : Processor<"generic", G3Itineraries, [Directive32]>;
189 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
190 FeatureFRES, FeatureFRSQRTE,
191 FeatureBookE, DeprecatedMFTB]>;
192 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
193 FeatureFRES, FeatureFRSQRTE,
194 FeatureBookE, DeprecatedMFTB]>;
195 def : Processor<"601", G3Itineraries, [Directive601]>;
196 def : Processor<"602", G3Itineraries, [Directive602]>;
197 def : Processor<"603", G3Itineraries, [Directive603,
198 FeatureFRES, FeatureFRSQRTE]>;
199 def : Processor<"603e", G3Itineraries, [Directive603,
200 FeatureFRES, FeatureFRSQRTE]>;
201 def : Processor<"603ev", G3Itineraries, [Directive603,
202 FeatureFRES, FeatureFRSQRTE]>;
203 def : Processor<"604", G3Itineraries, [Directive604,
204 FeatureFRES, FeatureFRSQRTE]>;
205 def : Processor<"604e", G3Itineraries, [Directive604,
206 FeatureFRES, FeatureFRSQRTE]>;
207 def : Processor<"620", G3Itineraries, [Directive620,
208 FeatureFRES, FeatureFRSQRTE]>;
209 def : Processor<"750", G4Itineraries, [Directive750,
210 FeatureFRES, FeatureFRSQRTE]>;
211 def : Processor<"g3", G3Itineraries, [Directive750,
212 FeatureFRES, FeatureFRSQRTE]>;
213 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
214 FeatureFRES, FeatureFRSQRTE]>;
215 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
216 FeatureFRES, FeatureFRSQRTE]>;
217 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
218 FeatureFRES, FeatureFRSQRTE]>;
219 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
220 FeatureFRES, FeatureFRSQRTE]>;
221 def : ProcessorModel<"970", G5Model,
222 [Directive970, FeatureAltivec,
223 FeatureMFOCRF, FeatureFSqrt,
224 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
225 Feature64Bit /*, Feature64BitRegs */]>;
226 def : ProcessorModel<"g5", G5Model,
227 [Directive970, FeatureAltivec,
228 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
229 FeatureFRES, FeatureFRSQRTE,
230 Feature64Bit /*, Feature64BitRegs */,
231 DeprecatedMFTB, DeprecatedDST]>;
232 def : ProcessorModel<"e500mc", PPCE500mcModel,
233 [DirectiveE500mc, FeatureMFOCRF,
234 FeatureSTFIWX, FeatureBookE, FeatureISEL,
236 def : ProcessorModel<"e5500", PPCE5500Model,
237 [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
238 FeatureSTFIWX, FeatureBookE, FeatureISEL,
240 def : ProcessorModel<"a2", PPCA2Model,
241 [DirectiveA2, FeatureBookE, FeatureMFOCRF,
242 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
243 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
244 FeatureSTFIWX, FeatureLFIWAX,
245 FeatureFPRND, FeatureFPCVT, FeatureISEL,
246 FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
247 /*, Feature64BitRegs */, DeprecatedMFTB]>;
248 def : ProcessorModel<"a2q", PPCA2Model,
249 [DirectiveA2, FeatureBookE, FeatureMFOCRF,
250 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
251 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
252 FeatureSTFIWX, FeatureLFIWAX,
253 FeatureFPRND, FeatureFPCVT, FeatureISEL,
254 FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
255 /*, Feature64BitRegs */, FeatureQPX, DeprecatedMFTB]>;
256 def : ProcessorModel<"pwr3", G5Model,
257 [DirectivePwr3, FeatureAltivec,
258 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
259 FeatureSTFIWX, Feature64Bit]>;
260 def : ProcessorModel<"pwr4", G5Model,
261 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
262 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
263 FeatureSTFIWX, Feature64Bit]>;
264 def : ProcessorModel<"pwr5", G5Model,
265 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
266 FeatureFSqrt, FeatureFRE, FeatureFRES,
267 FeatureFRSQRTE, FeatureFRSQRTES,
268 FeatureSTFIWX, Feature64Bit,
269 DeprecatedMFTB, DeprecatedDST]>;
270 def : ProcessorModel<"pwr5x", G5Model,
271 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
272 FeatureFSqrt, FeatureFRE, FeatureFRES,
273 FeatureFRSQRTE, FeatureFRSQRTES,
274 FeatureSTFIWX, FeatureFPRND, Feature64Bit,
275 DeprecatedMFTB, DeprecatedDST]>;
276 def : ProcessorModel<"pwr6", G5Model,
277 [DirectivePwr6, FeatureAltivec,
278 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
279 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
280 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
281 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
282 DeprecatedMFTB, DeprecatedDST]>;
283 def : ProcessorModel<"pwr6x", G5Model,
284 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
285 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
286 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
287 FeatureSTFIWX, FeatureLFIWAX,
288 FeatureFPRND, Feature64Bit,
289 DeprecatedMFTB, DeprecatedDST]>;
290 def : ProcessorModel<"pwr7", P7Model,
291 [DirectivePwr7, FeatureAltivec,
292 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
293 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
294 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
295 FeatureFPRND, FeatureFPCVT, FeatureISEL,
296 FeaturePOPCNTD, FeatureLDBRX,
297 Feature64Bit /*, Feature64BitRegs */,
298 DeprecatedMFTB, DeprecatedDST]>;
299 def : ProcessorModel<"pwr8", P7Model /* FIXME: Update to P8Model when available */,
300 [DirectivePwr8, FeatureAltivec,
301 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
302 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
303 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
304 FeatureFPRND, FeatureFPCVT, FeatureISEL,
305 FeaturePOPCNTD, FeatureLDBRX,
306 Feature64Bit /*, Feature64BitRegs */,
307 DeprecatedMFTB, DeprecatedDST]>;
308 def : Processor<"ppc", G3Itineraries, [Directive32]>;
309 def : ProcessorModel<"ppc64", G5Model,
310 [Directive64, FeatureAltivec,
311 FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
312 FeatureFRSQRTE, FeatureSTFIWX,
313 Feature64Bit /*, Feature64BitRegs */]>;
314 def : ProcessorModel<"ppc64le", G5Model,
315 [Directive64, FeatureAltivec,
316 FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
317 FeatureFRSQRTE, FeatureSTFIWX,
318 Feature64Bit /*, Feature64BitRegs */]>;
320 //===----------------------------------------------------------------------===//
321 // Calling Conventions
322 //===----------------------------------------------------------------------===//
324 include "PPCCallingConv.td"
326 def PPCInstrInfo : InstrInfo {
327 let isLittleEndianEncoding = 1;
329 // FIXME: Unset this when no longer needed!
330 let decodePositionallyEncodedOperands = 1;
332 let noNamedPositionallyEncodedOperands = 1;
335 def PPCAsmParser : AsmParser {
336 let ShouldEmitMatchRegisterName = 0;
339 def PPCAsmParserVariant : AsmParserVariant {
342 // We do not use hard coded registers in asm strings. However, some
343 // InstAlias definitions use immediate literals. Set RegisterPrefix
344 // so that those are not misinterpreted as registers.
345 string RegisterPrefix = "%";
349 // Information about the instructions.
350 let InstructionSet = PPCInstrInfo;
352 let AssemblyParsers = [PPCAsmParser];
353 let AssemblyParserVariants = [PPCAsmParserVariant];