1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the top level entry point for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 // Get the target-independent interfaces which we are implementing.
16 include "llvm/Target/Target.td"
18 //===----------------------------------------------------------------------===//
19 // PowerPC Subtarget features.
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
35 def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
36 def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
37 def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
39 "PPC::DIR_E500mc", "">;
40 def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective",
41 "PPC::DIR_E5500", "">;
42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
50 def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
51 "Enable 64-bit instructions">;
52 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
53 "Enable 64-bit registers usage for ppc32 [beta]">;
54 def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
55 "Enable Altivec instructions">;
56 def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
57 "Enable the MFOCRF instruction">;
58 def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
59 "Enable the fsqrt instruction">;
60 def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
61 "Enable the fcpsgn instruction">;
62 def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true",
63 "Enable the fre instruction">;
64 def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true",
65 "Enable the fres instruction">;
66 def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
67 "Enable the frsqrte instruction">;
68 def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
69 "Enable the frsqrtes instruction">;
70 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
71 "Assume higher precision reciprocal estimates">;
72 def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
73 "Enable the stfiwx instruction">;
74 def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
75 "Enable the lfiwax instruction">;
76 def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true",
77 "Enable the fri[mnpz] instructions">;
78 def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
79 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
80 def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
81 "Enable the isel instruction">;
82 def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
83 "Enable the popcnt[dw] instructions">;
84 def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true",
85 "Enable the ldbrx instruction">;
86 def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
87 "Enable Book E instructions">;
88 def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
89 "Enable QPX instructions">;
91 // Note: Future features to add when support is extended to more
94 // CMPB p6, p6x, p7 cmpb
95 // DFP p6, p6x, p7 decimal floating-point instructions
96 // POPCNTB p5 through p7 popcntb and related instructions
97 // VSX p7 vector-scalar instruction set
99 //===----------------------------------------------------------------------===//
100 // Classes used for relation maps.
101 //===----------------------------------------------------------------------===//
102 // RecFormRel - Filter class used to relate non-record-form instructions with
103 // their record-form variants.
106 //===----------------------------------------------------------------------===//
107 // Relation Map Definitions.
108 //===----------------------------------------------------------------------===//
110 def getRecordFormOpcode : InstrMapping {
111 let FilterClass = "RecFormRel";
112 // Instructions with the same BaseName and Interpretation64Bit values
114 let RowFields = ["BaseName", "Interpretation64Bit"];
115 // Instructions with the same RC value form a column.
116 let ColFields = ["RC"];
117 // The key column are the non-record-form instructions.
119 // Value columns RC=1
120 let ValueCols = [["1"]];
123 def getNonRecordFormOpcode : InstrMapping {
124 let FilterClass = "RecFormRel";
125 // Instructions with the same BaseName and Interpretation64Bit values
127 let RowFields = ["BaseName", "Interpretation64Bit"];
128 // Instructions with the same RC value form a column.
129 let ColFields = ["RC"];
130 // The key column are the record-form instructions.
132 // Value columns are RC=0
133 let ValueCols = [["0"]];
136 //===----------------------------------------------------------------------===//
137 // Register File Description
138 //===----------------------------------------------------------------------===//
140 include "PPCRegisterInfo.td"
141 include "PPCSchedule.td"
142 include "PPCInstrInfo.td"
144 //===----------------------------------------------------------------------===//
145 // PowerPC processors supported.
148 def : Processor<"generic", G3Itineraries, [Directive32]>;
149 def : Processor<"440", PPC440Itineraries, [Directive440, FeatureISEL,
150 FeatureFRES, FeatureFRSQRTE,
152 def : Processor<"450", PPC440Itineraries, [Directive440, FeatureISEL,
153 FeatureFRES, FeatureFRSQRTE,
155 def : Processor<"601", G3Itineraries, [Directive601]>;
156 def : Processor<"602", G3Itineraries, [Directive602]>;
157 def : Processor<"603", G3Itineraries, [Directive603,
158 FeatureFRES, FeatureFRSQRTE]>;
159 def : Processor<"603e", G3Itineraries, [Directive603,
160 FeatureFRES, FeatureFRSQRTE]>;
161 def : Processor<"603ev", G3Itineraries, [Directive603,
162 FeatureFRES, FeatureFRSQRTE]>;
163 def : Processor<"604", G3Itineraries, [Directive604,
164 FeatureFRES, FeatureFRSQRTE]>;
165 def : Processor<"604e", G3Itineraries, [Directive604,
166 FeatureFRES, FeatureFRSQRTE]>;
167 def : Processor<"620", G3Itineraries, [Directive620,
168 FeatureFRES, FeatureFRSQRTE]>;
169 def : Processor<"750", G4Itineraries, [Directive750,
170 FeatureFRES, FeatureFRSQRTE]>;
171 def : Processor<"g3", G3Itineraries, [Directive750,
172 FeatureFRES, FeatureFRSQRTE]>;
173 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
174 FeatureFRES, FeatureFRSQRTE]>;
175 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
176 FeatureFRES, FeatureFRSQRTE]>;
177 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
178 FeatureFRES, FeatureFRSQRTE]>;
179 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
180 FeatureFRES, FeatureFRSQRTE]>;
181 def : ProcessorModel<"970", G5Model,
182 [Directive970, FeatureAltivec,
183 FeatureMFOCRF, FeatureFSqrt,
184 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
185 Feature64Bit /*, Feature64BitRegs */]>;
186 def : ProcessorModel<"g5", G5Model,
187 [Directive970, FeatureAltivec,
188 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
189 FeatureFRES, FeatureFRSQRTE,
190 Feature64Bit /*, Feature64BitRegs */]>;
191 def : ProcessorModel<"e500mc", PPCE500mcModel,
192 [DirectiveE500mc, FeatureMFOCRF,
193 FeatureSTFIWX, FeatureBookE, FeatureISEL]>;
194 def : ProcessorModel<"e5500", PPCE5500Model,
195 [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
196 FeatureSTFIWX, FeatureBookE, FeatureISEL]>;
197 def : ProcessorModel<"a2", PPCA2Model,
198 [DirectiveA2, FeatureBookE, FeatureMFOCRF,
199 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
200 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
201 FeatureSTFIWX, FeatureLFIWAX,
202 FeatureFPRND, FeatureFPCVT, FeatureISEL,
203 FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
204 /*, Feature64BitRegs */]>;
205 def : ProcessorModel<"a2q", PPCA2Model,
206 [DirectiveA2, FeatureBookE, FeatureMFOCRF,
207 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
208 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
209 FeatureSTFIWX, FeatureLFIWAX,
210 FeatureFPRND, FeatureFPCVT, FeatureISEL,
211 FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
212 /*, Feature64BitRegs */, FeatureQPX]>;
213 def : ProcessorModel<"pwr3", G5Model,
214 [DirectivePwr3, FeatureAltivec,
215 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
216 FeatureSTFIWX, Feature64Bit]>;
217 def : ProcessorModel<"pwr4", G5Model,
218 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
219 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
220 FeatureSTFIWX, Feature64Bit]>;
221 def : ProcessorModel<"pwr5", G5Model,
222 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
223 FeatureFSqrt, FeatureFRE, FeatureFRES,
224 FeatureFRSQRTE, FeatureFRSQRTES,
225 FeatureSTFIWX, Feature64Bit]>;
226 def : ProcessorModel<"pwr5x", G5Model,
227 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
228 FeatureFSqrt, FeatureFRE, FeatureFRES,
229 FeatureFRSQRTE, FeatureFRSQRTES,
230 FeatureSTFIWX, FeatureFPRND, Feature64Bit]>;
231 def : ProcessorModel<"pwr6", G5Model,
232 [DirectivePwr6, FeatureAltivec,
233 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
234 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
235 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
236 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */]>;
237 def : ProcessorModel<"pwr6x", G5Model,
238 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
239 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
240 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
241 FeatureSTFIWX, FeatureLFIWAX,
242 FeatureFPRND, Feature64Bit]>;
243 def : ProcessorModel<"pwr7", G5Model,
244 [DirectivePwr7, FeatureAltivec,
245 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
246 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
247 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
248 FeatureFPRND, FeatureFPCVT, FeatureISEL,
249 FeaturePOPCNTD, FeatureLDBRX,
250 Feature64Bit /*, Feature64BitRegs */]>;
251 def : Processor<"ppc", G3Itineraries, [Directive32]>;
252 def : ProcessorModel<"ppc64", G5Model,
253 [Directive64, FeatureAltivec,
254 FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
255 FeatureFRSQRTE, FeatureSTFIWX,
256 Feature64Bit /*, Feature64BitRegs */]>;
257 def : ProcessorModel<"ppc64le", G5Model,
258 [Directive64, FeatureAltivec,
259 FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
260 FeatureFRSQRTE, FeatureSTFIWX,
261 Feature64Bit /*, Feature64BitRegs */]>;
263 //===----------------------------------------------------------------------===//
264 // Calling Conventions
265 //===----------------------------------------------------------------------===//
267 include "PPCCallingConv.td"
269 def PPCInstrInfo : InstrInfo {
270 let isLittleEndianEncoding = 1;
273 def PPCAsmWriter : AsmWriter {
274 string AsmWriterClassName = "InstPrinter";
275 bit isMCAsmWriter = 1;
278 def PPCAsmParser : AsmParser {
279 let ShouldEmitMatchRegisterName = 0;
282 def PPCAsmParserVariant : AsmParserVariant {
285 // We do not use hard coded registers in asm strings. However, some
286 // InstAlias definitions use immediate literals. Set RegisterPrefix
287 // so that those are not misinterpreted as registers.
288 string RegisterPrefix = "%";
292 // Information about the instructions.
293 let InstructionSet = PPCInstrInfo;
295 let AssemblyWriters = [PPCAsmWriter];
296 let AssemblyParsers = [PPCAsmParser];
297 let AssemblyParserVariants = [PPCAsmParserVariant];