1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #include "MCTargetDesc/PPCMCTargetDesc.h"
15 #include "MCTargetDesc/PPCFixupKinds.h"
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
25 #include "llvm/Target/TargetOpcodes.h"
28 #define DEBUG_TYPE "mccodeemitter"
30 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
33 class PPCMCCodeEmitter : public MCCodeEmitter {
34 PPCMCCodeEmitter(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION;
35 void operator=(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION;
37 const MCInstrInfo &MCII;
42 PPCMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool isLittle)
43 : MCII(mcii), CTX(ctx), IsLittleEndian(isLittle) {
46 ~PPCMCCodeEmitter() {}
48 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
49 SmallVectorImpl<MCFixup> &Fixups,
50 const MCSubtargetInfo &STI) const;
51 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
52 SmallVectorImpl<MCFixup> &Fixups,
53 const MCSubtargetInfo &STI) const;
54 unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
55 SmallVectorImpl<MCFixup> &Fixups,
56 const MCSubtargetInfo &STI) const;
57 unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
58 SmallVectorImpl<MCFixup> &Fixups,
59 const MCSubtargetInfo &STI) const;
60 unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo,
61 SmallVectorImpl<MCFixup> &Fixups,
62 const MCSubtargetInfo &STI) const;
63 unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
64 SmallVectorImpl<MCFixup> &Fixups,
65 const MCSubtargetInfo &STI) const;
66 unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
67 SmallVectorImpl<MCFixup> &Fixups,
68 const MCSubtargetInfo &STI) const;
69 unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
70 SmallVectorImpl<MCFixup> &Fixups,
71 const MCSubtargetInfo &STI) const;
72 unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
73 SmallVectorImpl<MCFixup> &Fixups,
74 const MCSubtargetInfo &STI) const;
75 unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
76 SmallVectorImpl<MCFixup> &Fixups,
77 const MCSubtargetInfo &STI) const;
79 /// getMachineOpValue - Return binary encoding of operand. If the machine
80 /// operand requires relocation, record the relocation and return zero.
81 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
82 SmallVectorImpl<MCFixup> &Fixups,
83 const MCSubtargetInfo &STI) const;
85 // getBinaryCodeForInstr - TableGen'erated function for getting the
86 // binary encoding for an instruction.
87 uint64_t getBinaryCodeForInstr(const MCInst &MI,
88 SmallVectorImpl<MCFixup> &Fixups,
89 const MCSubtargetInfo &STI) const;
90 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
91 SmallVectorImpl<MCFixup> &Fixups,
92 const MCSubtargetInfo &STI) const {
93 // For fast-isel, a float COPY_TO_REGCLASS can survive this long.
94 // It's just a nop to keep the register classes happy, so don't
96 unsigned Opcode = MI.getOpcode();
97 const MCInstrDesc &Desc = MCII.get(Opcode);
98 if (Opcode == TargetOpcode::COPY_TO_REGCLASS)
101 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
103 // Output the constant in big/little endian byte order.
104 unsigned Size = Desc.getSize();
105 if (IsLittleEndian) {
106 for (unsigned i = 0; i != Size; ++i) {
111 int ShiftValue = (Size * 8) - 8;
112 for (unsigned i = 0; i != Size; ++i) {
113 OS << (char)(Bits >> ShiftValue);
118 ++MCNumEmitted; // Keep track of the # of mi's emitted.
123 } // end anonymous namespace
125 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
126 const MCRegisterInfo &MRI,
127 const MCSubtargetInfo &STI,
129 Triple TT(STI.getTargetTriple());
130 bool IsLittleEndian = TT.getArch() == Triple::ppc64le;
131 return new PPCMCCodeEmitter(MCII, Ctx, IsLittleEndian);
134 unsigned PPCMCCodeEmitter::
135 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
136 SmallVectorImpl<MCFixup> &Fixups,
137 const MCSubtargetInfo &STI) const {
138 const MCOperand &MO = MI.getOperand(OpNo);
139 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
141 // Add a fixup for the branch target.
142 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
143 (MCFixupKind)PPC::fixup_ppc_br24));
147 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
148 SmallVectorImpl<MCFixup> &Fixups,
149 const MCSubtargetInfo &STI) const {
150 const MCOperand &MO = MI.getOperand(OpNo);
151 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
153 // Add a fixup for the branch target.
154 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
155 (MCFixupKind)PPC::fixup_ppc_brcond14));
159 unsigned PPCMCCodeEmitter::
160 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
161 SmallVectorImpl<MCFixup> &Fixups,
162 const MCSubtargetInfo &STI) const {
163 const MCOperand &MO = MI.getOperand(OpNo);
164 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
166 // Add a fixup for the branch target.
167 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
168 (MCFixupKind)PPC::fixup_ppc_br24abs));
172 unsigned PPCMCCodeEmitter::
173 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
174 SmallVectorImpl<MCFixup> &Fixups,
175 const MCSubtargetInfo &STI) const {
176 const MCOperand &MO = MI.getOperand(OpNo);
177 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
179 // Add a fixup for the branch target.
180 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
181 (MCFixupKind)PPC::fixup_ppc_brcond14abs));
185 unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
186 SmallVectorImpl<MCFixup> &Fixups,
187 const MCSubtargetInfo &STI) const {
188 const MCOperand &MO = MI.getOperand(OpNo);
189 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
191 // Add a fixup for the immediate field.
192 Fixups.push_back(MCFixup::Create(IsLittleEndian? 0 : 2, MO.getExpr(),
193 (MCFixupKind)PPC::fixup_ppc_half16));
197 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
198 SmallVectorImpl<MCFixup> &Fixups,
199 const MCSubtargetInfo &STI) const {
200 // Encode (imm, reg) as a memri, which has the low 16-bits as the
201 // displacement and the next 5 bits as the register #.
202 assert(MI.getOperand(OpNo+1).isReg());
203 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16;
205 const MCOperand &MO = MI.getOperand(OpNo);
207 return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits;
209 // Add a fixup for the displacement field.
210 Fixups.push_back(MCFixup::Create(IsLittleEndian? 0 : 2, MO.getExpr(),
211 (MCFixupKind)PPC::fixup_ppc_half16));
216 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
217 SmallVectorImpl<MCFixup> &Fixups,
218 const MCSubtargetInfo &STI) const {
219 // Encode (imm, reg) as a memrix, which has the low 14-bits as the
220 // displacement and the next 5 bits as the register #.
221 assert(MI.getOperand(OpNo+1).isReg());
222 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14;
224 const MCOperand &MO = MI.getOperand(OpNo);
226 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits;
228 // Add a fixup for the displacement field.
229 Fixups.push_back(MCFixup::Create(IsLittleEndian? 0 : 2, MO.getExpr(),
230 (MCFixupKind)PPC::fixup_ppc_half16ds));
235 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
236 SmallVectorImpl<MCFixup> &Fixups,
237 const MCSubtargetInfo &STI) const {
238 const MCOperand &MO = MI.getOperand(OpNo);
239 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI);
241 // Add a fixup for the TLS register, which simply provides a relocation
242 // hint to the linker that this statement is part of a relocation sequence.
243 // Return the thread-pointer register's encoding.
244 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
245 (MCFixupKind)PPC::fixup_ppc_nofixup));
246 Triple TT(STI.getTargetTriple());
247 bool isPPC64 = TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le;
248 return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2);
251 unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
252 SmallVectorImpl<MCFixup> &Fixups,
253 const MCSubtargetInfo &STI) const {
254 // For special TLS calls, we need two fixups; one for the branch target
255 // (__tls_get_addr), which we create via getDirectBrEncoding as usual,
256 // and one for the TLSGD or TLSLD symbol, which is emitted here.
257 const MCOperand &MO = MI.getOperand(OpNo+1);
258 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
259 (MCFixupKind)PPC::fixup_ppc_nofixup));
260 return getDirectBrEncoding(MI, OpNo, Fixups, STI);
263 unsigned PPCMCCodeEmitter::
264 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
265 SmallVectorImpl<MCFixup> &Fixups,
266 const MCSubtargetInfo &STI) const {
267 const MCOperand &MO = MI.getOperand(OpNo);
268 assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
269 MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
270 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
271 return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
275 unsigned PPCMCCodeEmitter::
276 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
277 SmallVectorImpl<MCFixup> &Fixups,
278 const MCSubtargetInfo &STI) const {
280 // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
281 // The GPR operand should come through here though.
282 assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&
283 MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||
284 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
285 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
289 "Relocation required in an instruction that we cannot encode!");
294 #include "PPCGenMCCodeEmitter.inc"