1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an PPC MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "PPCInstPrinter.h"
16 #include "MCTargetDesc/PPCMCTargetDesc.h"
17 #include "MCTargetDesc/PPCPredicates.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include "llvm/Target/TargetOpcodes.h"
26 // FIXME: Once the integrated assembler supports full register names, tie this
27 // to the verbose-asm setting.
29 FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
30 cl::desc("Use full register names when printing assembly"));
32 #include "PPCGenAsmWriter.inc"
34 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
35 OS << getRegisterName(RegNo);
38 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
40 // Check for slwi/srwi mnemonics.
41 if (MI->getOpcode() == PPC::RLWINM) {
42 unsigned char SH = MI->getOperand(2).getImm();
43 unsigned char MB = MI->getOperand(3).getImm();
44 unsigned char ME = MI->getOperand(4).getImm();
45 bool useSubstituteMnemonic = false;
46 if (SH <= 31 && MB == 0 && ME == (31-SH)) {
47 O << "\tslwi "; useSubstituteMnemonic = true;
49 if (SH <= 31 && MB == (32-SH) && ME == 31) {
50 O << "\tsrwi "; useSubstituteMnemonic = true;
53 if (useSubstituteMnemonic) {
54 printOperand(MI, 0, O);
56 printOperand(MI, 1, O);
57 O << ", " << (unsigned int)SH;
59 printAnnotation(O, Annot);
64 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
65 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
67 printOperand(MI, 0, O);
69 printOperand(MI, 1, O);
70 printAnnotation(O, Annot);
74 if (MI->getOpcode() == PPC::RLDICR) {
75 unsigned char SH = MI->getOperand(2).getImm();
76 unsigned char ME = MI->getOperand(3).getImm();
77 // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
80 printOperand(MI, 0, O);
82 printOperand(MI, 1, O);
83 O << ", " << (unsigned int)SH;
84 printAnnotation(O, Annot);
89 // For fast-isel, a COPY_TO_REGCLASS may survive this long. This is
90 // used when converting a 32-bit float to a 64-bit float as part of
91 // conversion to an integer (see PPCFastISel.cpp:SelectFPToI()),
92 // as otherwise we have problems with incorrect register classes
93 // in machine instruction verification. For now, just avoid trying
94 // to print it as such an instruction has no effect (a 32-bit float
95 // in a register is already in 64-bit form, just with lower
96 // precision). FIXME: Is there a better solution?
97 if (MI->getOpcode() == TargetOpcode::COPY_TO_REGCLASS)
100 printInstruction(MI, O);
101 printAnnotation(O, Annot);
105 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
107 const char *Modifier) {
108 unsigned Code = MI->getOperand(OpNo).getImm();
110 if (StringRef(Modifier) == "cc") {
111 switch ((PPC::Predicate)Code) {
112 case PPC::PRED_LT_MINUS:
113 case PPC::PRED_LT_PLUS:
117 case PPC::PRED_LE_MINUS:
118 case PPC::PRED_LE_PLUS:
122 case PPC::PRED_EQ_MINUS:
123 case PPC::PRED_EQ_PLUS:
127 case PPC::PRED_GE_MINUS:
128 case PPC::PRED_GE_PLUS:
132 case PPC::PRED_GT_MINUS:
133 case PPC::PRED_GT_PLUS:
137 case PPC::PRED_NE_MINUS:
138 case PPC::PRED_NE_PLUS:
142 case PPC::PRED_UN_MINUS:
143 case PPC::PRED_UN_PLUS:
147 case PPC::PRED_NU_MINUS:
148 case PPC::PRED_NU_PLUS:
153 llvm_unreachable("Invalid predicate code");
156 if (StringRef(Modifier) == "pm") {
157 switch ((PPC::Predicate)Code) {
167 case PPC::PRED_LT_MINUS:
168 case PPC::PRED_LE_MINUS:
169 case PPC::PRED_EQ_MINUS:
170 case PPC::PRED_GE_MINUS:
171 case PPC::PRED_GT_MINUS:
172 case PPC::PRED_NE_MINUS:
173 case PPC::PRED_UN_MINUS:
174 case PPC::PRED_NU_MINUS:
177 case PPC::PRED_LT_PLUS:
178 case PPC::PRED_LE_PLUS:
179 case PPC::PRED_EQ_PLUS:
180 case PPC::PRED_GE_PLUS:
181 case PPC::PRED_GT_PLUS:
182 case PPC::PRED_NE_PLUS:
183 case PPC::PRED_UN_PLUS:
184 case PPC::PRED_NU_PLUS:
188 llvm_unreachable("Invalid predicate code");
191 assert(StringRef(Modifier) == "reg" &&
192 "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
193 printOperand(MI, OpNo+1, O);
196 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
198 int Value = MI->getOperand(OpNo).getImm();
199 Value = SignExtend32<5>(Value);
203 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
205 unsigned int Value = MI->getOperand(OpNo).getImm();
206 assert(Value <= 31 && "Invalid u5imm argument!");
207 O << (unsigned int)Value;
210 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
212 unsigned int Value = MI->getOperand(OpNo).getImm();
213 assert(Value <= 63 && "Invalid u6imm argument!");
214 O << (unsigned int)Value;
217 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
219 if (MI->getOperand(OpNo).isImm())
220 O << (short)MI->getOperand(OpNo).getImm();
222 printOperand(MI, OpNo, O);
225 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
227 if (MI->getOperand(OpNo).isImm())
228 O << (unsigned short)MI->getOperand(OpNo).getImm();
230 printOperand(MI, OpNo, O);
233 void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
235 if (!MI->getOperand(OpNo).isImm())
236 return printOperand(MI, OpNo, O);
238 // Branches can take an immediate operand. This is used by the branch
239 // selection pass to print .+8, an eight byte displacement from the PC.
241 printAbsBranchOperand(MI, OpNo, O);
244 void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
246 if (!MI->getOperand(OpNo).isImm())
247 return printOperand(MI, OpNo, O);
249 O << (int)MI->getOperand(OpNo).getImm()*4;
253 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
255 unsigned CCReg = MI->getOperand(OpNo).getReg();
258 default: llvm_unreachable("Unknown CR register");
259 case PPC::CR0: RegNo = 0; break;
260 case PPC::CR1: RegNo = 1; break;
261 case PPC::CR2: RegNo = 2; break;
262 case PPC::CR3: RegNo = 3; break;
263 case PPC::CR4: RegNo = 4; break;
264 case PPC::CR5: RegNo = 5; break;
265 case PPC::CR6: RegNo = 6; break;
266 case PPC::CR7: RegNo = 7; break;
268 O << (0x80 >> RegNo);
271 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
273 printS16ImmOperand(MI, OpNo, O);
275 if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
278 printOperand(MI, OpNo+1, O);
282 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
284 // When used as the base register, r0 reads constant zero rather than
285 // the value contained in the register. For this reason, the darwin
286 // assembler requires that we print r0 as 0 (no r) when used as the base.
287 if (MI->getOperand(OpNo).getReg() == PPC::R0)
290 printOperand(MI, OpNo, O);
292 printOperand(MI, OpNo+1, O);
295 void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
297 printBranchOperand(MI, OpNo, O);
299 printOperand(MI, OpNo+1, O);
304 /// stripRegisterPrefix - This method strips the character prefix from a
305 /// register name so that only the number is left. Used by for linux asm.
306 static const char *stripRegisterPrefix(const char *RegName) {
310 switch (RegName[0]) {
313 case 'v': return RegName + 1;
314 case 'c': if (RegName[1] == 'r') return RegName + 2;
320 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
322 const MCOperand &Op = MI->getOperand(OpNo);
324 const char *RegName = getRegisterName(Op.getReg());
325 // The linux and AIX assembler does not take register prefixes.
326 if (!isDarwinSyntax())
327 RegName = stripRegisterPrefix(RegName);
338 assert(Op.isExpr() && "unknown operand kind in printOperand");