1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "llvm/MC/MCTargetAsmParser.h"
13 #include "llvm/MC/MCStreamer.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCRegisterInfo.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
18 #include "llvm/MC/MCParser/MCAsmLexer.h"
19 #include "llvm/MC/MCParser/MCAsmParser.h"
20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/SmallString.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/StringSwitch.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
34 static unsigned RRegs[32] = {
35 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
36 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
37 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
38 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
39 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
40 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
41 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
42 PPC::R28, PPC::R29, PPC::R30, PPC::R31
44 static unsigned RRegsNoR0[32] = {
46 PPC::R1, PPC::R2, PPC::R3,
47 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
48 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
49 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
50 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
51 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
52 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
53 PPC::R28, PPC::R29, PPC::R30, PPC::R31
55 static unsigned XRegs[32] = {
56 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
57 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
58 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
59 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
60 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
61 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
62 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
63 PPC::X28, PPC::X29, PPC::X30, PPC::X31
65 static unsigned XRegsNoX0[32] = {
67 PPC::X1, PPC::X2, PPC::X3,
68 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
69 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
70 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
71 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
72 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
73 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
74 PPC::X28, PPC::X29, PPC::X30, PPC::X31
76 static unsigned FRegs[32] = {
77 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
78 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
79 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
80 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
81 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
82 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
83 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
84 PPC::F28, PPC::F29, PPC::F30, PPC::F31
86 static unsigned VRegs[32] = {
87 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
88 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
89 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
90 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
91 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
92 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
93 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
94 PPC::V28, PPC::V29, PPC::V30, PPC::V31
96 static unsigned CRBITRegs[32] = {
97 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
98 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
99 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
100 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
101 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
102 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
103 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
104 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
106 static unsigned CRRegs[8] = {
107 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
108 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
111 // Evaluate an expression containing condition register
112 // or condition register field symbols. Returns positive
113 // value on success, or -1 on error.
115 EvaluateCRExpr(const MCExpr *E) {
116 switch (E->getKind()) {
120 case MCExpr::Constant: {
121 int64_t Res = cast<MCConstantExpr>(E)->getValue();
122 return Res < 0 ? -1 : Res;
125 case MCExpr::SymbolRef: {
126 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
127 StringRef Name = SRE->getSymbol().getName();
129 if (Name == "lt") return 0;
130 if (Name == "gt") return 1;
131 if (Name == "eq") return 2;
132 if (Name == "so") return 3;
133 if (Name == "un") return 3;
135 if (Name == "cr0") return 0;
136 if (Name == "cr1") return 1;
137 if (Name == "cr2") return 2;
138 if (Name == "cr3") return 3;
139 if (Name == "cr4") return 4;
140 if (Name == "cr5") return 5;
141 if (Name == "cr6") return 6;
142 if (Name == "cr7") return 7;
150 case MCExpr::Binary: {
151 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
152 int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
153 int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
156 if (LHSVal < 0 || RHSVal < 0)
159 switch (BE->getOpcode()) {
161 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
162 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
165 return Res < 0 ? -1 : Res;
169 llvm_unreachable("Invalid expression kind!");
174 class PPCAsmParser : public MCTargetAsmParser {
175 MCSubtargetInfo &STI;
179 MCAsmParser &getParser() const { return Parser; }
180 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
182 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
183 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
185 bool isPPC64() const { return IsPPC64; }
187 bool MatchRegisterName(const AsmToken &Tok,
188 unsigned &RegNo, int64_t &IntVal);
190 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
192 const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
193 PPCMCExpr::VariantKind &Variant);
194 const MCExpr *FixupVariantKind(const MCExpr *E);
195 bool ParseExpression(const MCExpr *&EVal);
197 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
199 bool ParseDirectiveWord(unsigned Size, SMLoc L);
200 bool ParseDirectiveTC(unsigned Size, SMLoc L);
201 bool ParseDirectiveMachine(SMLoc L);
203 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
204 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
205 MCStreamer &Out, unsigned &ErrorInfo,
206 bool MatchingInlineAsm);
208 void ProcessInstruction(MCInst &Inst,
209 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
211 /// @name Auto-generated Match Functions
214 #define GET_ASSEMBLER_HEADER
215 #include "PPCGenAsmMatcher.inc"
221 PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
222 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
223 // Check for 64-bit vs. 32-bit pointer mode.
224 Triple TheTriple(STI.getTargetTriple());
225 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
226 TheTriple.getArch() == Triple::ppc64le);
227 // Initialize the set of available features.
228 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
231 virtual bool ParseInstruction(ParseInstructionInfo &Info,
232 StringRef Name, SMLoc NameLoc,
233 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
235 virtual bool ParseDirective(AsmToken DirectiveID);
237 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
240 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
242 struct PPCOperand : public MCParsedAsmOperand {
250 SMLoc StartLoc, EndLoc;
264 int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
268 const MCSymbolRefExpr *Sym;
275 struct TLSRegOp TLSReg;
278 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
280 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
282 StartLoc = o.StartLoc;
301 /// getStartLoc - Get the location of the first token of this operand.
302 SMLoc getStartLoc() const { return StartLoc; }
304 /// getEndLoc - Get the location of the last token of this operand.
305 SMLoc getEndLoc() const { return EndLoc; }
307 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
308 bool isPPC64() const { return IsPPC64; }
310 int64_t getImm() const {
311 assert(Kind == Immediate && "Invalid access!");
315 const MCExpr *getExpr() const {
316 assert(Kind == Expression && "Invalid access!");
320 int64_t getExprCRVal() const {
321 assert(Kind == Expression && "Invalid access!");
325 const MCExpr *getTLSReg() const {
326 assert(Kind == TLSRegister && "Invalid access!");
330 unsigned getReg() const {
331 assert(isRegNumber() && "Invalid access!");
332 return (unsigned) Imm.Val;
335 unsigned getCCReg() const {
336 assert(isCCRegNumber() && "Invalid access!");
337 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
340 unsigned getCRBit() const {
341 assert(isCRBitNumber() && "Invalid access!");
342 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
345 unsigned getCRBitMask() const {
346 assert(isCRBitMask() && "Invalid access!");
347 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
350 bool isToken() const { return Kind == Token; }
351 bool isImm() const { return Kind == Immediate || Kind == Expression; }
352 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
353 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
354 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
355 bool isU16Imm() const { return Kind == Expression ||
356 (Kind == Immediate && isUInt<16>(getImm())); }
357 bool isS16Imm() const { return Kind == Expression ||
358 (Kind == Immediate && isInt<16>(getImm())); }
359 bool isS16ImmX4() const { return Kind == Expression ||
360 (Kind == Immediate && isInt<16>(getImm()) &&
361 (getImm() & 3) == 0); }
362 bool isS17Imm() const { return Kind == Expression ||
363 (Kind == Immediate && isInt<17>(getImm())); }
364 bool isTLSReg() const { return Kind == TLSRegister; }
365 bool isDirectBr() const { return Kind == Expression ||
366 (Kind == Immediate && isInt<26>(getImm()) &&
367 (getImm() & 3) == 0); }
368 bool isCondBr() const { return Kind == Expression ||
369 (Kind == Immediate && isInt<16>(getImm()) &&
370 (getImm() & 3) == 0); }
371 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
372 bool isCCRegNumber() const { return (Kind == Expression
373 && isUInt<3>(getExprCRVal())) ||
375 && isUInt<3>(getImm())); }
376 bool isCRBitNumber() const { return (Kind == Expression
377 && isUInt<5>(getExprCRVal())) ||
379 && isUInt<5>(getImm())); }
380 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
381 isPowerOf2_32(getImm()); }
382 bool isMem() const { return false; }
383 bool isReg() const { return false; }
385 void addRegOperands(MCInst &Inst, unsigned N) const {
386 llvm_unreachable("addRegOperands");
389 void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
390 assert(N == 1 && "Invalid number of operands!");
391 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
394 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
395 assert(N == 1 && "Invalid number of operands!");
396 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
399 void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
400 assert(N == 1 && "Invalid number of operands!");
401 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
404 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
405 assert(N == 1 && "Invalid number of operands!");
406 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
409 void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
411 addRegG8RCOperands(Inst, N);
413 addRegGPRCOperands(Inst, N);
416 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
418 addRegG8RCNoX0Operands(Inst, N);
420 addRegGPRCNoR0Operands(Inst, N);
423 void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
424 assert(N == 1 && "Invalid number of operands!");
425 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
428 void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
429 assert(N == 1 && "Invalid number of operands!");
430 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
433 void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
434 assert(N == 1 && "Invalid number of operands!");
435 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
438 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
439 assert(N == 1 && "Invalid number of operands!");
440 Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
443 void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
444 assert(N == 1 && "Invalid number of operands!");
445 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
448 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
449 assert(N == 1 && "Invalid number of operands!");
450 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
453 void addImmOperands(MCInst &Inst, unsigned N) const {
454 assert(N == 1 && "Invalid number of operands!");
455 if (Kind == Immediate)
456 Inst.addOperand(MCOperand::CreateImm(getImm()));
458 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
461 void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
462 assert(N == 1 && "Invalid number of operands!");
463 if (Kind == Immediate)
464 Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
466 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
469 void addTLSRegOperands(MCInst &Inst, unsigned N) const {
470 assert(N == 1 && "Invalid number of operands!");
471 Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
474 StringRef getToken() const {
475 assert(Kind == Token && "Invalid access!");
476 return StringRef(Tok.Data, Tok.Length);
479 virtual void print(raw_ostream &OS) const;
481 static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) {
482 PPCOperand *Op = new PPCOperand(Token);
483 Op->Tok.Data = Str.data();
484 Op->Tok.Length = Str.size();
487 Op->IsPPC64 = IsPPC64;
491 static PPCOperand *CreateImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
492 PPCOperand *Op = new PPCOperand(Immediate);
496 Op->IsPPC64 = IsPPC64;
500 static PPCOperand *CreateExpr(const MCExpr *Val,
501 SMLoc S, SMLoc E, bool IsPPC64) {
502 PPCOperand *Op = new PPCOperand(Expression);
504 Op->Expr.CRVal = EvaluateCRExpr(Val);
507 Op->IsPPC64 = IsPPC64;
511 static PPCOperand *CreateTLSReg(const MCSymbolRefExpr *Sym,
512 SMLoc S, SMLoc E, bool IsPPC64) {
513 PPCOperand *Op = new PPCOperand(TLSRegister);
514 Op->TLSReg.Sym = Sym;
517 Op->IsPPC64 = IsPPC64;
521 static PPCOperand *CreateFromMCExpr(const MCExpr *Val,
522 SMLoc S, SMLoc E, bool IsPPC64) {
523 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
524 return CreateImm(CE->getValue(), S, E, IsPPC64);
526 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
527 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
528 return CreateTLSReg(SRE, S, E, IsPPC64);
530 return CreateExpr(Val, S, E, IsPPC64);
534 } // end anonymous namespace.
536 void PPCOperand::print(raw_ostream &OS) const {
539 OS << "'" << getToken() << "'";
545 getExpr()->print(OS);
548 getTLSReg()->print(OS);
555 ProcessInstruction(MCInst &Inst,
556 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
557 int Opcode = Inst.getOpcode();
561 TmpInst.setOpcode(PPC::LA);
562 TmpInst.addOperand(Inst.getOperand(0));
563 TmpInst.addOperand(Inst.getOperand(2));
564 TmpInst.addOperand(Inst.getOperand(1));
570 int64_t N = Inst.getOperand(2).getImm();
571 TmpInst.setOpcode(PPC::ADDI);
572 TmpInst.addOperand(Inst.getOperand(0));
573 TmpInst.addOperand(Inst.getOperand(1));
574 TmpInst.addOperand(MCOperand::CreateImm(-N));
580 int64_t N = Inst.getOperand(2).getImm();
581 TmpInst.setOpcode(PPC::ADDIS);
582 TmpInst.addOperand(Inst.getOperand(0));
583 TmpInst.addOperand(Inst.getOperand(1));
584 TmpInst.addOperand(MCOperand::CreateImm(-N));
590 int64_t N = Inst.getOperand(2).getImm();
591 TmpInst.setOpcode(PPC::ADDIC);
592 TmpInst.addOperand(Inst.getOperand(0));
593 TmpInst.addOperand(Inst.getOperand(1));
594 TmpInst.addOperand(MCOperand::CreateImm(-N));
600 int64_t N = Inst.getOperand(2).getImm();
601 TmpInst.setOpcode(PPC::ADDICo);
602 TmpInst.addOperand(Inst.getOperand(0));
603 TmpInst.addOperand(Inst.getOperand(1));
604 TmpInst.addOperand(MCOperand::CreateImm(-N));
611 int64_t N = Inst.getOperand(2).getImm();
612 int64_t B = Inst.getOperand(3).getImm();
613 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
614 TmpInst.addOperand(Inst.getOperand(0));
615 TmpInst.addOperand(Inst.getOperand(1));
616 TmpInst.addOperand(MCOperand::CreateImm(B));
617 TmpInst.addOperand(MCOperand::CreateImm(0));
618 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
625 int64_t N = Inst.getOperand(2).getImm();
626 int64_t B = Inst.getOperand(3).getImm();
627 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
628 TmpInst.addOperand(Inst.getOperand(0));
629 TmpInst.addOperand(Inst.getOperand(1));
630 TmpInst.addOperand(MCOperand::CreateImm(B + N));
631 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
632 TmpInst.addOperand(MCOperand::CreateImm(31));
639 int64_t N = Inst.getOperand(2).getImm();
640 int64_t B = Inst.getOperand(3).getImm();
641 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
642 TmpInst.addOperand(Inst.getOperand(0));
643 TmpInst.addOperand(Inst.getOperand(0));
644 TmpInst.addOperand(Inst.getOperand(1));
645 TmpInst.addOperand(MCOperand::CreateImm(32 - B));
646 TmpInst.addOperand(MCOperand::CreateImm(B));
647 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
654 int64_t N = Inst.getOperand(2).getImm();
655 int64_t B = Inst.getOperand(3).getImm();
656 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
657 TmpInst.addOperand(Inst.getOperand(0));
658 TmpInst.addOperand(Inst.getOperand(0));
659 TmpInst.addOperand(Inst.getOperand(1));
660 TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
661 TmpInst.addOperand(MCOperand::CreateImm(B));
662 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
669 int64_t N = Inst.getOperand(2).getImm();
670 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
671 TmpInst.addOperand(Inst.getOperand(0));
672 TmpInst.addOperand(Inst.getOperand(1));
673 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
674 TmpInst.addOperand(MCOperand::CreateImm(0));
675 TmpInst.addOperand(MCOperand::CreateImm(31));
682 int64_t N = Inst.getOperand(2).getImm();
683 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
684 TmpInst.addOperand(Inst.getOperand(0));
685 TmpInst.addOperand(Inst.getOperand(1));
686 TmpInst.addOperand(MCOperand::CreateImm(N));
687 TmpInst.addOperand(MCOperand::CreateImm(0));
688 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
695 int64_t N = Inst.getOperand(2).getImm();
696 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
697 TmpInst.addOperand(Inst.getOperand(0));
698 TmpInst.addOperand(Inst.getOperand(1));
699 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
700 TmpInst.addOperand(MCOperand::CreateImm(N));
701 TmpInst.addOperand(MCOperand::CreateImm(31));
708 int64_t N = Inst.getOperand(2).getImm();
709 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
710 TmpInst.addOperand(Inst.getOperand(0));
711 TmpInst.addOperand(Inst.getOperand(1));
712 TmpInst.addOperand(MCOperand::CreateImm(0));
713 TmpInst.addOperand(MCOperand::CreateImm(0));
714 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
719 case PPC::CLRLSLWIo: {
721 int64_t B = Inst.getOperand(2).getImm();
722 int64_t N = Inst.getOperand(3).getImm();
723 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
724 TmpInst.addOperand(Inst.getOperand(0));
725 TmpInst.addOperand(Inst.getOperand(1));
726 TmpInst.addOperand(MCOperand::CreateImm(N));
727 TmpInst.addOperand(MCOperand::CreateImm(B - N));
728 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
735 int64_t N = Inst.getOperand(2).getImm();
736 int64_t B = Inst.getOperand(3).getImm();
737 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
738 TmpInst.addOperand(Inst.getOperand(0));
739 TmpInst.addOperand(Inst.getOperand(1));
740 TmpInst.addOperand(MCOperand::CreateImm(B));
741 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
748 int64_t N = Inst.getOperand(2).getImm();
749 int64_t B = Inst.getOperand(3).getImm();
750 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
751 TmpInst.addOperand(Inst.getOperand(0));
752 TmpInst.addOperand(Inst.getOperand(1));
753 TmpInst.addOperand(MCOperand::CreateImm(B + N));
754 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
761 int64_t N = Inst.getOperand(2).getImm();
762 int64_t B = Inst.getOperand(3).getImm();
763 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
764 TmpInst.addOperand(Inst.getOperand(0));
765 TmpInst.addOperand(Inst.getOperand(0));
766 TmpInst.addOperand(Inst.getOperand(1));
767 TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
768 TmpInst.addOperand(MCOperand::CreateImm(B));
775 int64_t N = Inst.getOperand(2).getImm();
776 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
777 TmpInst.addOperand(Inst.getOperand(0));
778 TmpInst.addOperand(Inst.getOperand(1));
779 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
780 TmpInst.addOperand(MCOperand::CreateImm(0));
787 int64_t N = Inst.getOperand(2).getImm();
788 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
789 TmpInst.addOperand(Inst.getOperand(0));
790 TmpInst.addOperand(Inst.getOperand(1));
791 TmpInst.addOperand(MCOperand::CreateImm(N));
792 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
799 int64_t N = Inst.getOperand(2).getImm();
800 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
801 TmpInst.addOperand(Inst.getOperand(0));
802 TmpInst.addOperand(Inst.getOperand(1));
803 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
804 TmpInst.addOperand(MCOperand::CreateImm(N));
811 int64_t N = Inst.getOperand(2).getImm();
812 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
813 TmpInst.addOperand(Inst.getOperand(0));
814 TmpInst.addOperand(Inst.getOperand(1));
815 TmpInst.addOperand(MCOperand::CreateImm(0));
816 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
821 case PPC::CLRLSLDIo: {
823 int64_t B = Inst.getOperand(2).getImm();
824 int64_t N = Inst.getOperand(3).getImm();
825 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
826 TmpInst.addOperand(Inst.getOperand(0));
827 TmpInst.addOperand(Inst.getOperand(1));
828 TmpInst.addOperand(MCOperand::CreateImm(N));
829 TmpInst.addOperand(MCOperand::CreateImm(B - N));
837 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
838 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
839 MCStreamer &Out, unsigned &ErrorInfo,
840 bool MatchingInlineAsm) {
843 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
846 // Post-process instructions (typically extended mnemonics)
847 ProcessInstruction(Inst, Operands);
849 Out.EmitInstruction(Inst);
851 case Match_MissingFeature:
852 return Error(IDLoc, "instruction use requires an option to be enabled");
853 case Match_MnemonicFail:
854 return Error(IDLoc, "unrecognized instruction mnemonic");
855 case Match_InvalidOperand: {
856 SMLoc ErrorLoc = IDLoc;
857 if (ErrorInfo != ~0U) {
858 if (ErrorInfo >= Operands.size())
859 return Error(IDLoc, "too few operands for instruction");
861 ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc();
862 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
865 return Error(ErrorLoc, "invalid operand for instruction");
869 llvm_unreachable("Implement any new match types added!");
873 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
874 if (Tok.is(AsmToken::Identifier)) {
875 StringRef Name = Tok.getString();
877 if (Name.equals_lower("lr")) {
878 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
881 } else if (Name.equals_lower("ctr")) {
882 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
885 } else if (Name.equals_lower("vrsave")) {
889 } else if (Name.substr(0, 1).equals_lower("r") &&
890 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
891 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
893 } else if (Name.substr(0, 1).equals_lower("f") &&
894 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
895 RegNo = FRegs[IntVal];
897 } else if (Name.substr(0, 1).equals_lower("v") &&
898 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
899 RegNo = VRegs[IntVal];
901 } else if (Name.substr(0, 2).equals_lower("cr") &&
902 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
903 RegNo = CRRegs[IntVal];
912 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
913 const AsmToken &Tok = Parser.getTok();
914 StartLoc = Tok.getLoc();
915 EndLoc = Tok.getEndLoc();
919 if (!MatchRegisterName(Tok, RegNo, IntVal)) {
920 Parser.Lex(); // Eat identifier token.
924 return Error(StartLoc, "invalid register name");
927 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
928 /// the expression and check for VK_PPC_LO/HI/HA
929 /// symbol variants. If all symbols with modifier use the same
930 /// variant, return the corresponding PPCMCExpr::VariantKind,
931 /// and a modified expression using the default symbol variant.
932 /// Otherwise, return NULL.
933 const MCExpr *PPCAsmParser::
934 ExtractModifierFromExpr(const MCExpr *E,
935 PPCMCExpr::VariantKind &Variant) {
936 MCContext &Context = getParser().getContext();
937 Variant = PPCMCExpr::VK_PPC_None;
939 switch (E->getKind()) {
941 case MCExpr::Constant:
944 case MCExpr::SymbolRef: {
945 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
947 switch (SRE->getKind()) {
948 case MCSymbolRefExpr::VK_PPC_LO:
949 Variant = PPCMCExpr::VK_PPC_LO;
951 case MCSymbolRefExpr::VK_PPC_HI:
952 Variant = PPCMCExpr::VK_PPC_HI;
954 case MCSymbolRefExpr::VK_PPC_HA:
955 Variant = PPCMCExpr::VK_PPC_HA;
957 case MCSymbolRefExpr::VK_PPC_HIGHER:
958 Variant = PPCMCExpr::VK_PPC_HIGHER;
960 case MCSymbolRefExpr::VK_PPC_HIGHERA:
961 Variant = PPCMCExpr::VK_PPC_HIGHERA;
963 case MCSymbolRefExpr::VK_PPC_HIGHEST:
964 Variant = PPCMCExpr::VK_PPC_HIGHEST;
966 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
967 Variant = PPCMCExpr::VK_PPC_HIGHESTA;
973 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
976 case MCExpr::Unary: {
977 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
978 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
981 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
984 case MCExpr::Binary: {
985 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
986 PPCMCExpr::VariantKind LHSVariant, RHSVariant;
987 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
988 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
993 if (!LHS) LHS = BE->getLHS();
994 if (!RHS) RHS = BE->getRHS();
996 if (LHSVariant == PPCMCExpr::VK_PPC_None)
997 Variant = RHSVariant;
998 else if (RHSVariant == PPCMCExpr::VK_PPC_None)
999 Variant = LHSVariant;
1000 else if (LHSVariant == RHSVariant)
1001 Variant = LHSVariant;
1005 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1009 llvm_unreachable("Invalid expression kind!");
1012 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1013 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having
1014 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1015 /// FIXME: This is a hack.
1016 const MCExpr *PPCAsmParser::
1017 FixupVariantKind(const MCExpr *E) {
1018 MCContext &Context = getParser().getContext();
1020 switch (E->getKind()) {
1021 case MCExpr::Target:
1022 case MCExpr::Constant:
1025 case MCExpr::SymbolRef: {
1026 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1027 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1029 switch (SRE->getKind()) {
1030 case MCSymbolRefExpr::VK_TLSGD:
1031 Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1033 case MCSymbolRefExpr::VK_TLSLD:
1034 Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1039 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context);
1042 case MCExpr::Unary: {
1043 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1044 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1045 if (Sub == UE->getSubExpr())
1047 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1050 case MCExpr::Binary: {
1051 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1052 const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1053 const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1054 if (LHS == BE->getLHS() && RHS == BE->getRHS())
1056 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1060 llvm_unreachable("Invalid expression kind!");
1063 /// Parse an expression. This differs from the default "parseExpression"
1064 /// in that it handles complex \code @l/@ha \endcode modifiers.
1066 ParseExpression(const MCExpr *&EVal) {
1067 if (getParser().parseExpression(EVal))
1070 EVal = FixupVariantKind(EVal);
1072 PPCMCExpr::VariantKind Variant;
1073 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1075 EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
1081 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1082 SMLoc S = Parser.getTok().getLoc();
1083 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1087 // Attempt to parse the next token as an immediate
1088 switch (getLexer().getKind()) {
1089 // Special handling for register names. These are interpreted
1090 // as immediates corresponding to the register number.
1091 case AsmToken::Percent:
1092 Parser.Lex(); // Eat the '%'.
1095 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1096 Parser.Lex(); // Eat the identifier token.
1097 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1098 Operands.push_back(Op);
1101 return Error(S, "invalid register name");
1103 // All other expressions
1104 case AsmToken::LParen:
1105 case AsmToken::Plus:
1106 case AsmToken::Minus:
1107 case AsmToken::Integer:
1108 case AsmToken::Identifier:
1110 case AsmToken::Dollar:
1111 if (!ParseExpression(EVal))
1115 return Error(S, "unknown operand");
1118 // Push the parsed operand into the list of operands
1119 Op = PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64());
1120 Operands.push_back(Op);
1122 // Check whether this is a TLS call expression
1123 bool TLSCall = false;
1124 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1125 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1127 if (TLSCall && getLexer().is(AsmToken::LParen)) {
1128 const MCExpr *TLSSym;
1130 Parser.Lex(); // Eat the '('.
1131 S = Parser.getTok().getLoc();
1132 if (ParseExpression(TLSSym))
1133 return Error(S, "invalid TLS call expression");
1134 if (getLexer().isNot(AsmToken::RParen))
1135 return Error(Parser.getTok().getLoc(), "missing ')'");
1136 E = Parser.getTok().getLoc();
1137 Parser.Lex(); // Eat the ')'.
1139 Op = PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64());
1140 Operands.push_back(Op);
1143 // Otherwise, check for D-form memory operands
1144 if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1145 Parser.Lex(); // Eat the '('.
1146 S = Parser.getTok().getLoc();
1149 switch (getLexer().getKind()) {
1150 case AsmToken::Percent:
1151 Parser.Lex(); // Eat the '%'.
1153 if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1154 return Error(S, "invalid register name");
1155 Parser.Lex(); // Eat the identifier token.
1158 case AsmToken::Integer:
1159 if (getParser().parseAbsoluteExpression(IntVal) ||
1160 IntVal < 0 || IntVal > 31)
1161 return Error(S, "invalid register number");
1165 return Error(S, "invalid memory operand");
1168 if (getLexer().isNot(AsmToken::RParen))
1169 return Error(Parser.getTok().getLoc(), "missing ')'");
1170 E = Parser.getTok().getLoc();
1171 Parser.Lex(); // Eat the ')'.
1173 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1174 Operands.push_back(Op);
1180 /// Parse an instruction mnemonic followed by its operands.
1182 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1183 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1184 // The first operand is the token for the instruction name.
1185 // If the next character is a '+' or '-', we need to add it to the
1186 // instruction name, to match what TableGen is doing.
1187 if (getLexer().is(AsmToken::Plus)) {
1189 char *NewOpcode = new char[Name.size() + 1];
1190 memcpy(NewOpcode, Name.data(), Name.size());
1191 NewOpcode[Name.size()] = '+';
1192 Name = StringRef(NewOpcode, Name.size() + 1);
1194 if (getLexer().is(AsmToken::Minus)) {
1196 char *NewOpcode = new char[Name.size() + 1];
1197 memcpy(NewOpcode, Name.data(), Name.size());
1198 NewOpcode[Name.size()] = '-';
1199 Name = StringRef(NewOpcode, Name.size() + 1);
1201 // If the instruction ends in a '.', we need to create a separate
1202 // token for it, to match what TableGen is doing.
1203 size_t Dot = Name.find('.');
1204 StringRef Mnemonic = Name.slice(0, Dot);
1205 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1206 if (Dot != StringRef::npos) {
1207 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1208 StringRef DotStr = Name.slice(Dot, StringRef::npos);
1209 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1212 // If there are no more operands then finish
1213 if (getLexer().is(AsmToken::EndOfStatement))
1216 // Parse the first operand
1217 if (ParseOperand(Operands))
1220 while (getLexer().isNot(AsmToken::EndOfStatement) &&
1221 getLexer().is(AsmToken::Comma)) {
1222 // Consume the comma token
1225 // Parse the next operand
1226 if (ParseOperand(Operands))
1233 /// ParseDirective parses the PPC specific directives
1234 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1235 StringRef IDVal = DirectiveID.getIdentifier();
1236 if (IDVal == ".word")
1237 return ParseDirectiveWord(2, DirectiveID.getLoc());
1238 if (IDVal == ".llong")
1239 return ParseDirectiveWord(8, DirectiveID.getLoc());
1241 return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1242 if (IDVal == ".machine")
1243 return ParseDirectiveMachine(DirectiveID.getLoc());
1247 /// ParseDirectiveWord
1248 /// ::= .word [ expression (, expression)* ]
1249 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1250 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1252 const MCExpr *Value;
1253 if (getParser().parseExpression(Value))
1256 getParser().getStreamer().EmitValue(Value, Size);
1258 if (getLexer().is(AsmToken::EndOfStatement))
1261 if (getLexer().isNot(AsmToken::Comma))
1262 return Error(L, "unexpected token in directive");
1271 /// ParseDirectiveTC
1272 /// ::= .tc [ symbol (, expression)* ]
1273 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1274 // Skip TC symbol, which is only used with XCOFF.
1275 while (getLexer().isNot(AsmToken::EndOfStatement)
1276 && getLexer().isNot(AsmToken::Comma))
1278 if (getLexer().isNot(AsmToken::Comma))
1279 return Error(L, "unexpected token in directive");
1282 // Align to word size.
1283 getParser().getStreamer().EmitValueToAlignment(Size);
1285 // Emit expressions.
1286 return ParseDirectiveWord(Size, L);
1289 /// ParseDirectiveMachine
1290 /// ::= .machine [ cpu | "push" | "pop" ]
1291 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1292 if (getLexer().isNot(AsmToken::Identifier) &&
1293 getLexer().isNot(AsmToken::String))
1294 return Error(L, "unexpected token in directive");
1296 StringRef CPU = Parser.getTok().getIdentifier();
1299 // FIXME: Right now, the parser always allows any available
1300 // instruction, so the .machine directive is not useful.
1301 // Implement ".machine any" (by doing nothing) for the benefit
1302 // of existing assembler code. Likewise, we can then implement
1303 // ".machine push" and ".machine pop" as no-op.
1304 if (CPU != "any" && CPU != "push" && CPU != "pop")
1305 return Error(L, "unrecognized machine type");
1307 if (getLexer().isNot(AsmToken::EndOfStatement))
1308 return Error(L, "unexpected token in directive");
1313 /// Force static initialization.
1314 extern "C" void LLVMInitializePowerPCAsmParser() {
1315 RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1316 RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1317 RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1320 #define GET_REGISTER_MATCHER
1321 #define GET_MATCHER_IMPLEMENTATION
1322 #include "PPCGenAsmMatcher.inc"
1324 // Define this matcher function after the auto-generated include so we
1325 // have the match class enum definitions.
1326 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
1328 // If the kind is a token for a literal immediate, check if our asm
1329 // operand matches. This is for InstAliases which have a fixed-value
1330 // immediate in the syntax.
1333 case MCK_0: ImmVal = 0; break;
1334 case MCK_1: ImmVal = 1; break;
1335 default: return Match_InvalidOperand;
1338 PPCOperand *Op = static_cast<PPCOperand*>(AsmOp);
1339 if (Op->isImm() && Op->getImm() == ImmVal)
1340 return Match_Success;
1342 return Match_InvalidOperand;