1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCParser/MCAsmLexer.h"
22 #include "llvm/MC/MCParser/MCAsmParser.h"
23 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCStreamer.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/MC/MCTargetAsmParser.h"
28 #include "llvm/Support/SourceMgr.h"
29 #include "llvm/Support/TargetRegistry.h"
30 #include "llvm/Support/raw_ostream.h"
36 static unsigned RRegs[32] = {
37 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
38 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
39 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
40 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
41 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
42 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
43 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
44 PPC::R28, PPC::R29, PPC::R30, PPC::R31
46 static unsigned RRegsNoR0[32] = {
48 PPC::R1, PPC::R2, PPC::R3,
49 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
50 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
51 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
52 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
53 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
54 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
55 PPC::R28, PPC::R29, PPC::R30, PPC::R31
57 static unsigned XRegs[32] = {
58 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
59 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
60 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
61 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
62 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
63 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
64 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
65 PPC::X28, PPC::X29, PPC::X30, PPC::X31
67 static unsigned XRegsNoX0[32] = {
69 PPC::X1, PPC::X2, PPC::X3,
70 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
71 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
72 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
73 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
74 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
75 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
76 PPC::X28, PPC::X29, PPC::X30, PPC::X31
78 static unsigned FRegs[32] = {
79 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
80 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
81 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
82 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
83 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
84 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
85 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
86 PPC::F28, PPC::F29, PPC::F30, PPC::F31
88 static unsigned VRegs[32] = {
89 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
90 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
91 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
92 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
93 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
94 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
95 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
96 PPC::V28, PPC::V29, PPC::V30, PPC::V31
98 static unsigned VSRegs[64] = {
99 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3,
100 PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7,
101 PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11,
102 PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
103 PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
104 PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
105 PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
106 PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
108 PPC::VSH0, PPC::VSH1, PPC::VSH2, PPC::VSH3,
109 PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7,
110 PPC::VSH8, PPC::VSH9, PPC::VSH10, PPC::VSH11,
111 PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
112 PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
113 PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
114 PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
115 PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
117 static unsigned VSFRegs[64] = {
118 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
119 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
120 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
121 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
122 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
123 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
124 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
125 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
127 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
128 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
129 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
130 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
131 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
132 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
133 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
134 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
136 static unsigned CRBITRegs[32] = {
137 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
138 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
139 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
140 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
141 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
142 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
143 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
144 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
146 static unsigned CRRegs[8] = {
147 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
148 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
151 // Evaluate an expression containing condition register
152 // or condition register field symbols. Returns positive
153 // value on success, or -1 on error.
155 EvaluateCRExpr(const MCExpr *E) {
156 switch (E->getKind()) {
160 case MCExpr::Constant: {
161 int64_t Res = cast<MCConstantExpr>(E)->getValue();
162 return Res < 0 ? -1 : Res;
165 case MCExpr::SymbolRef: {
166 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
167 StringRef Name = SRE->getSymbol().getName();
169 if (Name == "lt") return 0;
170 if (Name == "gt") return 1;
171 if (Name == "eq") return 2;
172 if (Name == "so") return 3;
173 if (Name == "un") return 3;
175 if (Name == "cr0") return 0;
176 if (Name == "cr1") return 1;
177 if (Name == "cr2") return 2;
178 if (Name == "cr3") return 3;
179 if (Name == "cr4") return 4;
180 if (Name == "cr5") return 5;
181 if (Name == "cr6") return 6;
182 if (Name == "cr7") return 7;
190 case MCExpr::Binary: {
191 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
192 int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
193 int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
196 if (LHSVal < 0 || RHSVal < 0)
199 switch (BE->getOpcode()) {
201 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
202 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
205 return Res < 0 ? -1 : Res;
209 llvm_unreachable("Invalid expression kind!");
214 class PPCAsmParser : public MCTargetAsmParser {
215 MCSubtargetInfo &STI;
217 const MCInstrInfo &MII;
221 MCAsmParser &getParser() const { return Parser; }
222 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
224 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
225 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
227 bool isPPC64() const { return IsPPC64; }
228 bool isDarwin() const { return IsDarwin; }
230 bool MatchRegisterName(const AsmToken &Tok,
231 unsigned &RegNo, int64_t &IntVal);
233 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
235 const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
236 PPCMCExpr::VariantKind &Variant);
237 const MCExpr *FixupVariantKind(const MCExpr *E);
238 bool ParseExpression(const MCExpr *&EVal);
239 bool ParseDarwinExpression(const MCExpr *&EVal);
241 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
243 bool ParseDirectiveWord(unsigned Size, SMLoc L);
244 bool ParseDirectiveTC(unsigned Size, SMLoc L);
245 bool ParseDirectiveMachine(SMLoc L);
246 bool ParseDarwinDirectiveMachine(SMLoc L);
248 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
249 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
250 MCStreamer &Out, unsigned &ErrorInfo,
251 bool MatchingInlineAsm);
253 void ProcessInstruction(MCInst &Inst,
254 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
256 /// @name Auto-generated Match Functions
259 #define GET_ASSEMBLER_HEADER
260 #include "PPCGenAsmMatcher.inc"
266 PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
267 const MCInstrInfo &_MII,
268 const MCTargetOptions &Options)
269 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(_MII) {
270 // Check for 64-bit vs. 32-bit pointer mode.
271 Triple TheTriple(STI.getTargetTriple());
272 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
273 TheTriple.getArch() == Triple::ppc64le);
274 IsDarwin = TheTriple.isMacOSX();
275 // Initialize the set of available features.
276 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
279 virtual bool ParseInstruction(ParseInstructionInfo &Info,
280 StringRef Name, SMLoc NameLoc,
281 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
283 virtual bool ParseDirective(AsmToken DirectiveID);
285 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
287 virtual const MCExpr *applyModifierToExpr(const MCExpr *E,
288 MCSymbolRefExpr::VariantKind,
292 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
294 struct PPCOperand : public MCParsedAsmOperand {
302 SMLoc StartLoc, EndLoc;
316 int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
320 const MCSymbolRefExpr *Sym;
327 struct TLSRegOp TLSReg;
330 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
332 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
334 StartLoc = o.StartLoc;
353 /// getStartLoc - Get the location of the first token of this operand.
354 SMLoc getStartLoc() const { return StartLoc; }
356 /// getEndLoc - Get the location of the last token of this operand.
357 SMLoc getEndLoc() const { return EndLoc; }
359 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
360 bool isPPC64() const { return IsPPC64; }
362 int64_t getImm() const {
363 assert(Kind == Immediate && "Invalid access!");
367 const MCExpr *getExpr() const {
368 assert(Kind == Expression && "Invalid access!");
372 int64_t getExprCRVal() const {
373 assert(Kind == Expression && "Invalid access!");
377 const MCExpr *getTLSReg() const {
378 assert(Kind == TLSRegister && "Invalid access!");
382 unsigned getReg() const {
383 assert(isRegNumber() && "Invalid access!");
384 return (unsigned) Imm.Val;
387 unsigned getVSReg() const {
388 assert(isVSRegNumber() && "Invalid access!");
389 return (unsigned) Imm.Val;
392 unsigned getCCReg() const {
393 assert(isCCRegNumber() && "Invalid access!");
394 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
397 unsigned getCRBit() const {
398 assert(isCRBitNumber() && "Invalid access!");
399 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
402 unsigned getCRBitMask() const {
403 assert(isCRBitMask() && "Invalid access!");
404 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
407 bool isToken() const { return Kind == Token; }
408 bool isImm() const { return Kind == Immediate || Kind == Expression; }
409 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
410 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
411 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
412 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
413 bool isU16Imm() const { return Kind == Expression ||
414 (Kind == Immediate && isUInt<16>(getImm())); }
415 bool isS16Imm() const { return Kind == Expression ||
416 (Kind == Immediate && isInt<16>(getImm())); }
417 bool isS16ImmX4() const { return Kind == Expression ||
418 (Kind == Immediate && isInt<16>(getImm()) &&
419 (getImm() & 3) == 0); }
420 bool isS17Imm() const { return Kind == Expression ||
421 (Kind == Immediate && isInt<17>(getImm())); }
422 bool isTLSReg() const { return Kind == TLSRegister; }
423 bool isDirectBr() const { return Kind == Expression ||
424 (Kind == Immediate && isInt<26>(getImm()) &&
425 (getImm() & 3) == 0); }
426 bool isCondBr() const { return Kind == Expression ||
427 (Kind == Immediate && isInt<16>(getImm()) &&
428 (getImm() & 3) == 0); }
429 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
430 bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
431 bool isCCRegNumber() const { return (Kind == Expression
432 && isUInt<3>(getExprCRVal())) ||
434 && isUInt<3>(getImm())); }
435 bool isCRBitNumber() const { return (Kind == Expression
436 && isUInt<5>(getExprCRVal())) ||
438 && isUInt<5>(getImm())); }
439 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
440 isPowerOf2_32(getImm()); }
441 bool isMem() const { return false; }
442 bool isReg() const { return false; }
444 void addRegOperands(MCInst &Inst, unsigned N) const {
445 llvm_unreachable("addRegOperands");
448 void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
449 assert(N == 1 && "Invalid number of operands!");
450 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
453 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
454 assert(N == 1 && "Invalid number of operands!");
455 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
458 void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
459 assert(N == 1 && "Invalid number of operands!");
460 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
463 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
464 assert(N == 1 && "Invalid number of operands!");
465 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
468 void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
470 addRegG8RCOperands(Inst, N);
472 addRegGPRCOperands(Inst, N);
475 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
477 addRegG8RCNoX0Operands(Inst, N);
479 addRegGPRCNoR0Operands(Inst, N);
482 void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
483 assert(N == 1 && "Invalid number of operands!");
484 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
487 void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
488 assert(N == 1 && "Invalid number of operands!");
489 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
492 void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
493 assert(N == 1 && "Invalid number of operands!");
494 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
497 void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
498 assert(N == 1 && "Invalid number of operands!");
499 Inst.addOperand(MCOperand::CreateReg(VSRegs[getVSReg()]));
502 void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
503 assert(N == 1 && "Invalid number of operands!");
504 Inst.addOperand(MCOperand::CreateReg(VSFRegs[getVSReg()]));
507 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
508 assert(N == 1 && "Invalid number of operands!");
509 Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
512 void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
513 assert(N == 1 && "Invalid number of operands!");
514 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
517 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
518 assert(N == 1 && "Invalid number of operands!");
519 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
522 void addImmOperands(MCInst &Inst, unsigned N) const {
523 assert(N == 1 && "Invalid number of operands!");
524 if (Kind == Immediate)
525 Inst.addOperand(MCOperand::CreateImm(getImm()));
527 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
530 void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
531 assert(N == 1 && "Invalid number of operands!");
532 if (Kind == Immediate)
533 Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
535 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
538 void addTLSRegOperands(MCInst &Inst, unsigned N) const {
539 assert(N == 1 && "Invalid number of operands!");
540 Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
543 StringRef getToken() const {
544 assert(Kind == Token && "Invalid access!");
545 return StringRef(Tok.Data, Tok.Length);
548 virtual void print(raw_ostream &OS) const;
550 static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) {
551 PPCOperand *Op = new PPCOperand(Token);
552 Op->Tok.Data = Str.data();
553 Op->Tok.Length = Str.size();
556 Op->IsPPC64 = IsPPC64;
560 static PPCOperand *CreateTokenWithStringCopy(StringRef Str, SMLoc S,
562 // Allocate extra memory for the string and copy it.
563 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
564 PPCOperand *Op = new (Mem) PPCOperand(Token);
565 Op->Tok.Data = (const char *)(Op + 1);
566 Op->Tok.Length = Str.size();
567 std::memcpy((char *)(Op + 1), Str.data(), Str.size());
570 Op->IsPPC64 = IsPPC64;
574 static PPCOperand *CreateImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
575 PPCOperand *Op = new PPCOperand(Immediate);
579 Op->IsPPC64 = IsPPC64;
583 static PPCOperand *CreateExpr(const MCExpr *Val,
584 SMLoc S, SMLoc E, bool IsPPC64) {
585 PPCOperand *Op = new PPCOperand(Expression);
587 Op->Expr.CRVal = EvaluateCRExpr(Val);
590 Op->IsPPC64 = IsPPC64;
594 static PPCOperand *CreateTLSReg(const MCSymbolRefExpr *Sym,
595 SMLoc S, SMLoc E, bool IsPPC64) {
596 PPCOperand *Op = new PPCOperand(TLSRegister);
597 Op->TLSReg.Sym = Sym;
600 Op->IsPPC64 = IsPPC64;
604 static PPCOperand *CreateFromMCExpr(const MCExpr *Val,
605 SMLoc S, SMLoc E, bool IsPPC64) {
606 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
607 return CreateImm(CE->getValue(), S, E, IsPPC64);
609 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
610 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
611 return CreateTLSReg(SRE, S, E, IsPPC64);
613 return CreateExpr(Val, S, E, IsPPC64);
617 } // end anonymous namespace.
619 void PPCOperand::print(raw_ostream &OS) const {
622 OS << "'" << getToken() << "'";
628 getExpr()->print(OS);
631 getTLSReg()->print(OS);
638 ProcessInstruction(MCInst &Inst,
639 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
640 int Opcode = Inst.getOpcode();
644 TmpInst.setOpcode(PPC::LA);
645 TmpInst.addOperand(Inst.getOperand(0));
646 TmpInst.addOperand(Inst.getOperand(2));
647 TmpInst.addOperand(Inst.getOperand(1));
653 int64_t N = Inst.getOperand(2).getImm();
654 TmpInst.setOpcode(PPC::ADDI);
655 TmpInst.addOperand(Inst.getOperand(0));
656 TmpInst.addOperand(Inst.getOperand(1));
657 TmpInst.addOperand(MCOperand::CreateImm(-N));
663 int64_t N = Inst.getOperand(2).getImm();
664 TmpInst.setOpcode(PPC::ADDIS);
665 TmpInst.addOperand(Inst.getOperand(0));
666 TmpInst.addOperand(Inst.getOperand(1));
667 TmpInst.addOperand(MCOperand::CreateImm(-N));
673 int64_t N = Inst.getOperand(2).getImm();
674 TmpInst.setOpcode(PPC::ADDIC);
675 TmpInst.addOperand(Inst.getOperand(0));
676 TmpInst.addOperand(Inst.getOperand(1));
677 TmpInst.addOperand(MCOperand::CreateImm(-N));
683 int64_t N = Inst.getOperand(2).getImm();
684 TmpInst.setOpcode(PPC::ADDICo);
685 TmpInst.addOperand(Inst.getOperand(0));
686 TmpInst.addOperand(Inst.getOperand(1));
687 TmpInst.addOperand(MCOperand::CreateImm(-N));
694 int64_t N = Inst.getOperand(2).getImm();
695 int64_t B = Inst.getOperand(3).getImm();
696 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
697 TmpInst.addOperand(Inst.getOperand(0));
698 TmpInst.addOperand(Inst.getOperand(1));
699 TmpInst.addOperand(MCOperand::CreateImm(B));
700 TmpInst.addOperand(MCOperand::CreateImm(0));
701 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
708 int64_t N = Inst.getOperand(2).getImm();
709 int64_t B = Inst.getOperand(3).getImm();
710 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
711 TmpInst.addOperand(Inst.getOperand(0));
712 TmpInst.addOperand(Inst.getOperand(1));
713 TmpInst.addOperand(MCOperand::CreateImm(B + N));
714 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
715 TmpInst.addOperand(MCOperand::CreateImm(31));
722 int64_t N = Inst.getOperand(2).getImm();
723 int64_t B = Inst.getOperand(3).getImm();
724 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
725 TmpInst.addOperand(Inst.getOperand(0));
726 TmpInst.addOperand(Inst.getOperand(0));
727 TmpInst.addOperand(Inst.getOperand(1));
728 TmpInst.addOperand(MCOperand::CreateImm(32 - B));
729 TmpInst.addOperand(MCOperand::CreateImm(B));
730 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
737 int64_t N = Inst.getOperand(2).getImm();
738 int64_t B = Inst.getOperand(3).getImm();
739 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
740 TmpInst.addOperand(Inst.getOperand(0));
741 TmpInst.addOperand(Inst.getOperand(0));
742 TmpInst.addOperand(Inst.getOperand(1));
743 TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
744 TmpInst.addOperand(MCOperand::CreateImm(B));
745 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
752 int64_t N = Inst.getOperand(2).getImm();
753 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
754 TmpInst.addOperand(Inst.getOperand(0));
755 TmpInst.addOperand(Inst.getOperand(1));
756 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
757 TmpInst.addOperand(MCOperand::CreateImm(0));
758 TmpInst.addOperand(MCOperand::CreateImm(31));
765 int64_t N = Inst.getOperand(2).getImm();
766 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
767 TmpInst.addOperand(Inst.getOperand(0));
768 TmpInst.addOperand(Inst.getOperand(1));
769 TmpInst.addOperand(MCOperand::CreateImm(N));
770 TmpInst.addOperand(MCOperand::CreateImm(0));
771 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
778 int64_t N = Inst.getOperand(2).getImm();
779 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
780 TmpInst.addOperand(Inst.getOperand(0));
781 TmpInst.addOperand(Inst.getOperand(1));
782 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
783 TmpInst.addOperand(MCOperand::CreateImm(N));
784 TmpInst.addOperand(MCOperand::CreateImm(31));
791 int64_t N = Inst.getOperand(2).getImm();
792 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
793 TmpInst.addOperand(Inst.getOperand(0));
794 TmpInst.addOperand(Inst.getOperand(1));
795 TmpInst.addOperand(MCOperand::CreateImm(0));
796 TmpInst.addOperand(MCOperand::CreateImm(0));
797 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
802 case PPC::CLRLSLWIo: {
804 int64_t B = Inst.getOperand(2).getImm();
805 int64_t N = Inst.getOperand(3).getImm();
806 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
807 TmpInst.addOperand(Inst.getOperand(0));
808 TmpInst.addOperand(Inst.getOperand(1));
809 TmpInst.addOperand(MCOperand::CreateImm(N));
810 TmpInst.addOperand(MCOperand::CreateImm(B - N));
811 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
818 int64_t N = Inst.getOperand(2).getImm();
819 int64_t B = Inst.getOperand(3).getImm();
820 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
821 TmpInst.addOperand(Inst.getOperand(0));
822 TmpInst.addOperand(Inst.getOperand(1));
823 TmpInst.addOperand(MCOperand::CreateImm(B));
824 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
831 int64_t N = Inst.getOperand(2).getImm();
832 int64_t B = Inst.getOperand(3).getImm();
833 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
834 TmpInst.addOperand(Inst.getOperand(0));
835 TmpInst.addOperand(Inst.getOperand(1));
836 TmpInst.addOperand(MCOperand::CreateImm(B + N));
837 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
844 int64_t N = Inst.getOperand(2).getImm();
845 int64_t B = Inst.getOperand(3).getImm();
846 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
847 TmpInst.addOperand(Inst.getOperand(0));
848 TmpInst.addOperand(Inst.getOperand(0));
849 TmpInst.addOperand(Inst.getOperand(1));
850 TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
851 TmpInst.addOperand(MCOperand::CreateImm(B));
858 int64_t N = Inst.getOperand(2).getImm();
859 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
860 TmpInst.addOperand(Inst.getOperand(0));
861 TmpInst.addOperand(Inst.getOperand(1));
862 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
863 TmpInst.addOperand(MCOperand::CreateImm(0));
870 int64_t N = Inst.getOperand(2).getImm();
871 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
872 TmpInst.addOperand(Inst.getOperand(0));
873 TmpInst.addOperand(Inst.getOperand(1));
874 TmpInst.addOperand(MCOperand::CreateImm(N));
875 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
882 int64_t N = Inst.getOperand(2).getImm();
883 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
884 TmpInst.addOperand(Inst.getOperand(0));
885 TmpInst.addOperand(Inst.getOperand(1));
886 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
887 TmpInst.addOperand(MCOperand::CreateImm(N));
894 int64_t N = Inst.getOperand(2).getImm();
895 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
896 TmpInst.addOperand(Inst.getOperand(0));
897 TmpInst.addOperand(Inst.getOperand(1));
898 TmpInst.addOperand(MCOperand::CreateImm(0));
899 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
904 case PPC::CLRLSLDIo: {
906 int64_t B = Inst.getOperand(2).getImm();
907 int64_t N = Inst.getOperand(3).getImm();
908 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
909 TmpInst.addOperand(Inst.getOperand(0));
910 TmpInst.addOperand(Inst.getOperand(1));
911 TmpInst.addOperand(MCOperand::CreateImm(N));
912 TmpInst.addOperand(MCOperand::CreateImm(B - N));
920 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
921 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
922 MCStreamer &Out, unsigned &ErrorInfo,
923 bool MatchingInlineAsm) {
926 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
929 // Post-process instructions (typically extended mnemonics)
930 ProcessInstruction(Inst, Operands);
932 Out.EmitInstruction(Inst, STI);
934 case Match_MissingFeature:
935 return Error(IDLoc, "instruction use requires an option to be enabled");
936 case Match_MnemonicFail:
937 return Error(IDLoc, "unrecognized instruction mnemonic");
938 case Match_InvalidOperand: {
939 SMLoc ErrorLoc = IDLoc;
940 if (ErrorInfo != ~0U) {
941 if (ErrorInfo >= Operands.size())
942 return Error(IDLoc, "too few operands for instruction");
944 ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc();
945 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
948 return Error(ErrorLoc, "invalid operand for instruction");
952 llvm_unreachable("Implement any new match types added!");
956 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
957 if (Tok.is(AsmToken::Identifier)) {
958 StringRef Name = Tok.getString();
960 if (Name.equals_lower("lr")) {
961 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
964 } else if (Name.equals_lower("ctr")) {
965 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
968 } else if (Name.equals_lower("vrsave")) {
972 } else if (Name.startswith_lower("r") &&
973 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
974 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
976 } else if (Name.startswith_lower("f") &&
977 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
978 RegNo = FRegs[IntVal];
980 } else if (Name.startswith_lower("v") &&
981 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
982 RegNo = VRegs[IntVal];
984 } else if (Name.startswith_lower("cr") &&
985 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
986 RegNo = CRRegs[IntVal];
995 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
996 const AsmToken &Tok = Parser.getTok();
997 StartLoc = Tok.getLoc();
998 EndLoc = Tok.getEndLoc();
1002 if (!MatchRegisterName(Tok, RegNo, IntVal)) {
1003 Parser.Lex(); // Eat identifier token.
1007 return Error(StartLoc, "invalid register name");
1010 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
1011 /// the expression and check for VK_PPC_LO/HI/HA
1012 /// symbol variants. If all symbols with modifier use the same
1013 /// variant, return the corresponding PPCMCExpr::VariantKind,
1014 /// and a modified expression using the default symbol variant.
1015 /// Otherwise, return NULL.
1016 const MCExpr *PPCAsmParser::
1017 ExtractModifierFromExpr(const MCExpr *E,
1018 PPCMCExpr::VariantKind &Variant) {
1019 MCContext &Context = getParser().getContext();
1020 Variant = PPCMCExpr::VK_PPC_None;
1022 switch (E->getKind()) {
1023 case MCExpr::Target:
1024 case MCExpr::Constant:
1027 case MCExpr::SymbolRef: {
1028 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1030 switch (SRE->getKind()) {
1031 case MCSymbolRefExpr::VK_PPC_LO:
1032 Variant = PPCMCExpr::VK_PPC_LO;
1034 case MCSymbolRefExpr::VK_PPC_HI:
1035 Variant = PPCMCExpr::VK_PPC_HI;
1037 case MCSymbolRefExpr::VK_PPC_HA:
1038 Variant = PPCMCExpr::VK_PPC_HA;
1040 case MCSymbolRefExpr::VK_PPC_HIGHER:
1041 Variant = PPCMCExpr::VK_PPC_HIGHER;
1043 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1044 Variant = PPCMCExpr::VK_PPC_HIGHERA;
1046 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1047 Variant = PPCMCExpr::VK_PPC_HIGHEST;
1049 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1050 Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1056 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
1059 case MCExpr::Unary: {
1060 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1061 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1064 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1067 case MCExpr::Binary: {
1068 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1069 PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1070 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1071 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1076 if (!LHS) LHS = BE->getLHS();
1077 if (!RHS) RHS = BE->getRHS();
1079 if (LHSVariant == PPCMCExpr::VK_PPC_None)
1080 Variant = RHSVariant;
1081 else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1082 Variant = LHSVariant;
1083 else if (LHSVariant == RHSVariant)
1084 Variant = LHSVariant;
1088 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1092 llvm_unreachable("Invalid expression kind!");
1095 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1096 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having
1097 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1098 /// FIXME: This is a hack.
1099 const MCExpr *PPCAsmParser::
1100 FixupVariantKind(const MCExpr *E) {
1101 MCContext &Context = getParser().getContext();
1103 switch (E->getKind()) {
1104 case MCExpr::Target:
1105 case MCExpr::Constant:
1108 case MCExpr::SymbolRef: {
1109 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1110 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1112 switch (SRE->getKind()) {
1113 case MCSymbolRefExpr::VK_TLSGD:
1114 Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1116 case MCSymbolRefExpr::VK_TLSLD:
1117 Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1122 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context);
1125 case MCExpr::Unary: {
1126 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1127 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1128 if (Sub == UE->getSubExpr())
1130 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1133 case MCExpr::Binary: {
1134 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1135 const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1136 const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1137 if (LHS == BE->getLHS() && RHS == BE->getRHS())
1139 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1143 llvm_unreachable("Invalid expression kind!");
1146 /// ParseExpression. This differs from the default "parseExpression" in that
1147 /// it handles modifiers.
1149 ParseExpression(const MCExpr *&EVal) {
1152 return ParseDarwinExpression(EVal);
1155 // Handle \code @l/@ha \endcode
1156 if (getParser().parseExpression(EVal))
1159 EVal = FixupVariantKind(EVal);
1161 PPCMCExpr::VariantKind Variant;
1162 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1164 EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
1169 /// ParseDarwinExpression. (MachO Platforms)
1170 /// This differs from the default "parseExpression" in that it handles detection
1171 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present,
1172 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1173 /// syntax form so it is done here. TODO: Determine if there is merit in arranging
1174 /// for this to be done at a higher level.
1176 ParseDarwinExpression(const MCExpr *&EVal) {
1177 PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1178 switch (getLexer().getKind()) {
1181 case AsmToken::Identifier:
1182 // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1183 // something starting with any other char should be part of the
1184 // asm syntax. If handwritten asm includes an identifier like lo16,
1185 // then all bets are off - but no-one would do that, right?
1186 StringRef poss = Parser.getTok().getString();
1187 if (poss.equals_lower("lo16")) {
1188 Variant = PPCMCExpr::VK_PPC_LO;
1189 } else if (poss.equals_lower("hi16")) {
1190 Variant = PPCMCExpr::VK_PPC_HI;
1191 } else if (poss.equals_lower("ha16")) {
1192 Variant = PPCMCExpr::VK_PPC_HA;
1194 if (Variant != PPCMCExpr::VK_PPC_None) {
1195 Parser.Lex(); // Eat the xx16
1196 if (getLexer().isNot(AsmToken::LParen))
1197 return Error(Parser.getTok().getLoc(), "expected '('");
1198 Parser.Lex(); // Eat the '('
1203 if (getParser().parseExpression(EVal))
1206 if (Variant != PPCMCExpr::VK_PPC_None) {
1207 if (getLexer().isNot(AsmToken::RParen))
1208 return Error(Parser.getTok().getLoc(), "expected ')'");
1209 Parser.Lex(); // Eat the ')'
1210 EVal = PPCMCExpr::Create(Variant, EVal, false, getParser().getContext());
1216 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1219 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1220 SMLoc S = Parser.getTok().getLoc();
1221 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1225 // Attempt to parse the next token as an immediate
1226 switch (getLexer().getKind()) {
1227 // Special handling for register names. These are interpreted
1228 // as immediates corresponding to the register number.
1229 case AsmToken::Percent:
1230 Parser.Lex(); // Eat the '%'.
1233 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1234 Parser.Lex(); // Eat the identifier token.
1235 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1236 Operands.push_back(Op);
1239 return Error(S, "invalid register name");
1241 case AsmToken::Identifier:
1242 // Note that non-register-name identifiers from the compiler will begin
1243 // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include
1244 // identifiers like r31foo - so we fall through in the event that parsing
1245 // a register name fails.
1249 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1250 Parser.Lex(); // Eat the identifier token.
1251 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1252 Operands.push_back(Op);
1256 // Fall-through to process non-register-name identifiers as expression.
1257 // All other expressions
1258 case AsmToken::LParen:
1259 case AsmToken::Plus:
1260 case AsmToken::Minus:
1261 case AsmToken::Integer:
1263 case AsmToken::Dollar:
1264 case AsmToken::Exclaim:
1265 case AsmToken::Tilde:
1266 if (!ParseExpression(EVal))
1270 return Error(S, "unknown operand");
1273 // Push the parsed operand into the list of operands
1274 Op = PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64());
1275 Operands.push_back(Op);
1277 // Check whether this is a TLS call expression
1278 bool TLSCall = false;
1279 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1280 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1282 if (TLSCall && getLexer().is(AsmToken::LParen)) {
1283 const MCExpr *TLSSym;
1285 Parser.Lex(); // Eat the '('.
1286 S = Parser.getTok().getLoc();
1287 if (ParseExpression(TLSSym))
1288 return Error(S, "invalid TLS call expression");
1289 if (getLexer().isNot(AsmToken::RParen))
1290 return Error(Parser.getTok().getLoc(), "missing ')'");
1291 E = Parser.getTok().getLoc();
1292 Parser.Lex(); // Eat the ')'.
1294 Op = PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64());
1295 Operands.push_back(Op);
1298 // Otherwise, check for D-form memory operands
1299 if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1300 Parser.Lex(); // Eat the '('.
1301 S = Parser.getTok().getLoc();
1304 switch (getLexer().getKind()) {
1305 case AsmToken::Percent:
1306 Parser.Lex(); // Eat the '%'.
1308 if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1309 return Error(S, "invalid register name");
1310 Parser.Lex(); // Eat the identifier token.
1313 case AsmToken::Integer:
1315 if (getParser().parseAbsoluteExpression(IntVal) ||
1316 IntVal < 0 || IntVal > 31)
1317 return Error(S, "invalid register number");
1319 return Error(S, "unexpected integer value");
1323 case AsmToken::Identifier:
1326 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1327 Parser.Lex(); // Eat the identifier token.
1334 return Error(S, "invalid memory operand");
1337 if (getLexer().isNot(AsmToken::RParen))
1338 return Error(Parser.getTok().getLoc(), "missing ')'");
1339 E = Parser.getTok().getLoc();
1340 Parser.Lex(); // Eat the ')'.
1342 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1343 Operands.push_back(Op);
1349 /// Parse an instruction mnemonic followed by its operands.
1351 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1352 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1353 // The first operand is the token for the instruction name.
1354 // If the next character is a '+' or '-', we need to add it to the
1355 // instruction name, to match what TableGen is doing.
1356 std::string NewOpcode;
1357 if (getLexer().is(AsmToken::Plus)) {
1363 if (getLexer().is(AsmToken::Minus)) {
1369 // If the instruction ends in a '.', we need to create a separate
1370 // token for it, to match what TableGen is doing.
1371 size_t Dot = Name.find('.');
1372 StringRef Mnemonic = Name.slice(0, Dot);
1373 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1375 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1377 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1378 if (Dot != StringRef::npos) {
1379 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1380 StringRef DotStr = Name.slice(Dot, StringRef::npos);
1381 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1383 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1385 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1388 // If there are no more operands then finish
1389 if (getLexer().is(AsmToken::EndOfStatement))
1392 // Parse the first operand
1393 if (ParseOperand(Operands))
1396 while (getLexer().isNot(AsmToken::EndOfStatement) &&
1397 getLexer().is(AsmToken::Comma)) {
1398 // Consume the comma token
1401 // Parse the next operand
1402 if (ParseOperand(Operands))
1409 /// ParseDirective parses the PPC specific directives
1410 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1411 StringRef IDVal = DirectiveID.getIdentifier();
1413 if (IDVal == ".word")
1414 return ParseDirectiveWord(2, DirectiveID.getLoc());
1415 if (IDVal == ".llong")
1416 return ParseDirectiveWord(8, DirectiveID.getLoc());
1418 return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1419 if (IDVal == ".machine")
1420 return ParseDirectiveMachine(DirectiveID.getLoc());
1422 if (IDVal == ".machine")
1423 return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1428 /// ParseDirectiveWord
1429 /// ::= .word [ expression (, expression)* ]
1430 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1431 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1433 const MCExpr *Value;
1434 if (getParser().parseExpression(Value))
1437 getParser().getStreamer().EmitValue(Value, Size);
1439 if (getLexer().is(AsmToken::EndOfStatement))
1442 if (getLexer().isNot(AsmToken::Comma))
1443 return Error(L, "unexpected token in directive");
1452 /// ParseDirectiveTC
1453 /// ::= .tc [ symbol (, expression)* ]
1454 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1455 // Skip TC symbol, which is only used with XCOFF.
1456 while (getLexer().isNot(AsmToken::EndOfStatement)
1457 && getLexer().isNot(AsmToken::Comma))
1459 if (getLexer().isNot(AsmToken::Comma)) {
1460 Error(L, "unexpected token in directive");
1465 // Align to word size.
1466 getParser().getStreamer().EmitValueToAlignment(Size);
1468 // Emit expressions.
1469 return ParseDirectiveWord(Size, L);
1472 /// ParseDirectiveMachine (ELF platforms)
1473 /// ::= .machine [ cpu | "push" | "pop" ]
1474 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1475 if (getLexer().isNot(AsmToken::Identifier) &&
1476 getLexer().isNot(AsmToken::String)) {
1477 Error(L, "unexpected token in directive");
1481 StringRef CPU = Parser.getTok().getIdentifier();
1484 // FIXME: Right now, the parser always allows any available
1485 // instruction, so the .machine directive is not useful.
1486 // Implement ".machine any" (by doing nothing) for the benefit
1487 // of existing assembler code. Likewise, we can then implement
1488 // ".machine push" and ".machine pop" as no-op.
1489 if (CPU != "any" && CPU != "push" && CPU != "pop") {
1490 Error(L, "unrecognized machine type");
1494 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1495 Error(L, "unexpected token in directive");
1498 PPCTargetStreamer &TStreamer =
1499 *static_cast<PPCTargetStreamer *>(
1500 getParser().getStreamer().getTargetStreamer());
1501 TStreamer.emitMachine(CPU);
1506 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1507 /// ::= .machine cpu-identifier
1508 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1509 if (getLexer().isNot(AsmToken::Identifier) &&
1510 getLexer().isNot(AsmToken::String)) {
1511 Error(L, "unexpected token in directive");
1515 StringRef CPU = Parser.getTok().getIdentifier();
1518 // FIXME: this is only the 'default' set of cpu variants.
1519 // However we don't act on this information at present, this is simply
1520 // allowing parsing to proceed with minimal sanity checking.
1521 if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1522 Error(L, "unrecognized cpu type");
1526 if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1527 Error(L, "wrong cpu type specified for 64bit");
1530 if (!isPPC64() && CPU == "ppc64") {
1531 Error(L, "wrong cpu type specified for 32bit");
1535 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1536 Error(L, "unexpected token in directive");
1543 /// Force static initialization.
1544 extern "C" void LLVMInitializePowerPCAsmParser() {
1545 RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1546 RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1547 RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1550 #define GET_REGISTER_MATCHER
1551 #define GET_MATCHER_IMPLEMENTATION
1552 #include "PPCGenAsmMatcher.inc"
1554 // Define this matcher function after the auto-generated include so we
1555 // have the match class enum definitions.
1556 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
1558 // If the kind is a token for a literal immediate, check if our asm
1559 // operand matches. This is for InstAliases which have a fixed-value
1560 // immediate in the syntax.
1563 case MCK_0: ImmVal = 0; break;
1564 case MCK_1: ImmVal = 1; break;
1565 case MCK_2: ImmVal = 2; break;
1566 case MCK_3: ImmVal = 3; break;
1567 default: return Match_InvalidOperand;
1570 PPCOperand *Op = static_cast<PPCOperand*>(AsmOp);
1571 if (Op->isImm() && Op->getImm() == ImmVal)
1572 return Match_Success;
1574 return Match_InvalidOperand;
1578 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1579 MCSymbolRefExpr::VariantKind Variant,
1582 case MCSymbolRefExpr::VK_PPC_LO:
1583 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1584 case MCSymbolRefExpr::VK_PPC_HI:
1585 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1586 case MCSymbolRefExpr::VK_PPC_HA:
1587 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1588 case MCSymbolRefExpr::VK_PPC_HIGHER:
1589 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1590 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1591 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1592 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1593 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1594 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1595 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);