1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "llvm/MC/MCTargetAsmParser.h"
13 #include "llvm/MC/MCStreamer.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCRegisterInfo.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
18 #include "llvm/MC/MCParser/MCAsmLexer.h"
19 #include "llvm/MC/MCParser/MCAsmParser.h"
20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringSwitch.h"
24 #include "llvm/ADT/Twine.h"
25 #include "llvm/Support/SourceMgr.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Support/raw_ostream.h"
33 static unsigned RRegs[32] = {
34 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
35 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
36 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
37 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
38 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
39 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
40 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
41 PPC::R28, PPC::R29, PPC::R30, PPC::R31
43 static unsigned RRegsNoR0[32] = {
45 PPC::R1, PPC::R2, PPC::R3,
46 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
47 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
48 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
49 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
50 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
51 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
52 PPC::R28, PPC::R29, PPC::R30, PPC::R31
54 static unsigned XRegs[32] = {
55 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
56 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
57 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
58 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
59 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
60 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
61 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
62 PPC::X28, PPC::X29, PPC::X30, PPC::X31
64 static unsigned XRegsNoX0[32] = {
66 PPC::X1, PPC::X2, PPC::X3,
67 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
68 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
69 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
70 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
71 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
72 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
73 PPC::X28, PPC::X29, PPC::X30, PPC::X31
75 static unsigned FRegs[32] = {
76 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
77 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
78 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
79 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
80 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
81 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
82 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
83 PPC::F28, PPC::F29, PPC::F30, PPC::F31
85 static unsigned VRegs[32] = {
86 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
87 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
88 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
89 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
90 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
91 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
92 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
93 PPC::V28, PPC::V29, PPC::V30, PPC::V31
95 static unsigned CRBITRegs[32] = {
96 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
97 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
98 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
99 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
100 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
101 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
102 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
103 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
105 static unsigned CRRegs[8] = {
106 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
107 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
110 // Evaluate an expression containing condition register
111 // or condition register field symbols. Returns positive
112 // value on success, or -1 on error.
114 EvaluateCRExpr(const MCExpr *E) {
115 switch (E->getKind()) {
119 case MCExpr::Constant: {
120 int64_t Res = cast<MCConstantExpr>(E)->getValue();
121 return Res < 0 ? -1 : Res;
124 case MCExpr::SymbolRef: {
125 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
126 StringRef Name = SRE->getSymbol().getName();
128 if (Name == "lt") return 0;
129 if (Name == "gt") return 1;
130 if (Name == "eq") return 2;
131 if (Name == "so") return 3;
132 if (Name == "un") return 3;
134 if (Name == "cr0") return 0;
135 if (Name == "cr1") return 1;
136 if (Name == "cr2") return 2;
137 if (Name == "cr3") return 3;
138 if (Name == "cr4") return 4;
139 if (Name == "cr5") return 5;
140 if (Name == "cr6") return 6;
141 if (Name == "cr7") return 7;
149 case MCExpr::Binary: {
150 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
151 int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
152 int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
155 if (LHSVal < 0 || RHSVal < 0)
158 switch (BE->getOpcode()) {
160 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
161 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
164 return Res < 0 ? -1 : Res;
168 llvm_unreachable("Invalid expression kind!");
173 class PPCAsmParser : public MCTargetAsmParser {
174 MCSubtargetInfo &STI;
178 MCAsmParser &getParser() const { return Parser; }
179 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
181 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
182 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
184 bool isPPC64() const { return IsPPC64; }
186 bool MatchRegisterName(const AsmToken &Tok,
187 unsigned &RegNo, int64_t &IntVal);
189 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
191 const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
192 PPCMCExpr::VariantKind &Variant);
193 bool ParseExpression(const MCExpr *&EVal);
195 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
197 bool ParseDirectiveWord(unsigned Size, SMLoc L);
198 bool ParseDirectiveTC(unsigned Size, SMLoc L);
199 bool ParseDirectiveMachine(SMLoc L);
201 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
202 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
203 MCStreamer &Out, unsigned &ErrorInfo,
204 bool MatchingInlineAsm);
206 void ProcessInstruction(MCInst &Inst,
207 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
209 /// @name Auto-generated Match Functions
212 #define GET_ASSEMBLER_HEADER
213 #include "PPCGenAsmMatcher.inc"
219 PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
220 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
221 // Check for 64-bit vs. 32-bit pointer mode.
222 Triple TheTriple(STI.getTargetTriple());
223 IsPPC64 = TheTriple.getArch() == Triple::ppc64;
224 // Initialize the set of available features.
225 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
228 virtual bool ParseInstruction(ParseInstructionInfo &Info,
229 StringRef Name, SMLoc NameLoc,
230 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
232 virtual bool ParseDirective(AsmToken DirectiveID);
234 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
237 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
239 struct PPCOperand : public MCParsedAsmOperand {
247 SMLoc StartLoc, EndLoc;
261 int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
265 const MCSymbolRefExpr *Sym;
272 struct TLSRegOp TLSReg;
275 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
277 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
279 StartLoc = o.StartLoc;
298 /// getStartLoc - Get the location of the first token of this operand.
299 SMLoc getStartLoc() const { return StartLoc; }
301 /// getEndLoc - Get the location of the last token of this operand.
302 SMLoc getEndLoc() const { return EndLoc; }
304 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
305 bool isPPC64() const { return IsPPC64; }
307 int64_t getImm() const {
308 assert(Kind == Immediate && "Invalid access!");
312 const MCExpr *getExpr() const {
313 assert(Kind == Expression && "Invalid access!");
317 int64_t getExprCRVal() const {
318 assert(Kind == Expression && "Invalid access!");
322 const MCExpr *getTLSReg() const {
323 assert(Kind == TLSRegister && "Invalid access!");
327 unsigned getReg() const {
328 assert(isRegNumber() && "Invalid access!");
329 return (unsigned) Imm.Val;
332 unsigned getCCReg() const {
333 assert(isCCRegNumber() && "Invalid access!");
334 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
337 unsigned getCRBit() const {
338 assert(isCRBitNumber() && "Invalid access!");
339 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
342 unsigned getCRBitMask() const {
343 assert(isCRBitMask() && "Invalid access!");
344 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
347 bool isToken() const { return Kind == Token; }
348 bool isImm() const { return Kind == Immediate || Kind == Expression; }
349 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
350 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
351 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
352 bool isU16Imm() const { return Kind == Expression ||
353 (Kind == Immediate && isUInt<16>(getImm())); }
354 bool isS16Imm() const { return Kind == Expression ||
355 (Kind == Immediate && isInt<16>(getImm())); }
356 bool isS16ImmX4() const { return Kind == Expression ||
357 (Kind == Immediate && isInt<16>(getImm()) &&
358 (getImm() & 3) == 0); }
359 bool isS17Imm() const { return Kind == Expression ||
360 (Kind == Immediate && isInt<17>(getImm())); }
361 bool isTLSReg() const { return Kind == TLSRegister; }
362 bool isDirectBr() const { return Kind == Expression ||
363 (Kind == Immediate && isInt<26>(getImm()) &&
364 (getImm() & 3) == 0); }
365 bool isCondBr() const { return Kind == Expression ||
366 (Kind == Immediate && isInt<16>(getImm()) &&
367 (getImm() & 3) == 0); }
368 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
369 bool isCCRegNumber() const { return (Kind == Expression
370 && isUInt<3>(getExprCRVal())) ||
372 && isUInt<3>(getImm())); }
373 bool isCRBitNumber() const { return (Kind == Expression
374 && isUInt<5>(getExprCRVal())) ||
376 && isUInt<5>(getImm())); }
377 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
378 isPowerOf2_32(getImm()); }
379 bool isMem() const { return false; }
380 bool isReg() const { return false; }
382 void addRegOperands(MCInst &Inst, unsigned N) const {
383 llvm_unreachable("addRegOperands");
386 void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
387 assert(N == 1 && "Invalid number of operands!");
388 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
391 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
392 assert(N == 1 && "Invalid number of operands!");
393 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
396 void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
397 assert(N == 1 && "Invalid number of operands!");
398 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
401 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
402 assert(N == 1 && "Invalid number of operands!");
403 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
406 void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
408 addRegG8RCOperands(Inst, N);
410 addRegGPRCOperands(Inst, N);
413 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
415 addRegG8RCNoX0Operands(Inst, N);
417 addRegGPRCNoR0Operands(Inst, N);
420 void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
421 assert(N == 1 && "Invalid number of operands!");
422 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
425 void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
426 assert(N == 1 && "Invalid number of operands!");
427 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
430 void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
431 assert(N == 1 && "Invalid number of operands!");
432 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
435 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
436 assert(N == 1 && "Invalid number of operands!");
437 Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
440 void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
441 assert(N == 1 && "Invalid number of operands!");
442 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
445 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
446 assert(N == 1 && "Invalid number of operands!");
447 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
450 void addImmOperands(MCInst &Inst, unsigned N) const {
451 assert(N == 1 && "Invalid number of operands!");
452 if (Kind == Immediate)
453 Inst.addOperand(MCOperand::CreateImm(getImm()));
455 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
458 void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
459 assert(N == 1 && "Invalid number of operands!");
460 if (Kind == Immediate)
461 Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
463 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
466 void addTLSRegOperands(MCInst &Inst, unsigned N) const {
467 assert(N == 1 && "Invalid number of operands!");
468 Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
471 StringRef getToken() const {
472 assert(Kind == Token && "Invalid access!");
473 return StringRef(Tok.Data, Tok.Length);
476 virtual void print(raw_ostream &OS) const;
478 static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) {
479 PPCOperand *Op = new PPCOperand(Token);
480 Op->Tok.Data = Str.data();
481 Op->Tok.Length = Str.size();
484 Op->IsPPC64 = IsPPC64;
488 static PPCOperand *CreateImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
489 PPCOperand *Op = new PPCOperand(Immediate);
493 Op->IsPPC64 = IsPPC64;
497 static PPCOperand *CreateExpr(const MCExpr *Val,
498 SMLoc S, SMLoc E, bool IsPPC64) {
499 PPCOperand *Op = new PPCOperand(Expression);
501 Op->Expr.CRVal = EvaluateCRExpr(Val);
504 Op->IsPPC64 = IsPPC64;
508 static PPCOperand *CreateTLSReg(const MCSymbolRefExpr *Sym,
509 SMLoc S, SMLoc E, bool IsPPC64) {
510 PPCOperand *Op = new PPCOperand(TLSRegister);
511 Op->TLSReg.Sym = Sym;
514 Op->IsPPC64 = IsPPC64;
518 static PPCOperand *CreateFromMCExpr(const MCExpr *Val,
519 SMLoc S, SMLoc E, bool IsPPC64) {
520 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
521 return CreateImm(CE->getValue(), S, E, IsPPC64);
523 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
524 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
525 return CreateTLSReg(SRE, S, E, IsPPC64);
527 return CreateExpr(Val, S, E, IsPPC64);
531 } // end anonymous namespace.
533 void PPCOperand::print(raw_ostream &OS) const {
536 OS << "'" << getToken() << "'";
542 getExpr()->print(OS);
545 getTLSReg()->print(OS);
552 ProcessInstruction(MCInst &Inst,
553 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
554 int Opcode = Inst.getOpcode();
558 TmpInst.setOpcode(PPC::LA);
559 TmpInst.addOperand(Inst.getOperand(0));
560 TmpInst.addOperand(Inst.getOperand(2));
561 TmpInst.addOperand(Inst.getOperand(1));
567 int64_t N = Inst.getOperand(2).getImm();
568 TmpInst.setOpcode(PPC::ADDI);
569 TmpInst.addOperand(Inst.getOperand(0));
570 TmpInst.addOperand(Inst.getOperand(1));
571 TmpInst.addOperand(MCOperand::CreateImm(-N));
577 int64_t N = Inst.getOperand(2).getImm();
578 TmpInst.setOpcode(PPC::ADDIS);
579 TmpInst.addOperand(Inst.getOperand(0));
580 TmpInst.addOperand(Inst.getOperand(1));
581 TmpInst.addOperand(MCOperand::CreateImm(-N));
587 int64_t N = Inst.getOperand(2).getImm();
588 TmpInst.setOpcode(PPC::ADDIC);
589 TmpInst.addOperand(Inst.getOperand(0));
590 TmpInst.addOperand(Inst.getOperand(1));
591 TmpInst.addOperand(MCOperand::CreateImm(-N));
597 int64_t N = Inst.getOperand(2).getImm();
598 TmpInst.setOpcode(PPC::ADDICo);
599 TmpInst.addOperand(Inst.getOperand(0));
600 TmpInst.addOperand(Inst.getOperand(1));
601 TmpInst.addOperand(MCOperand::CreateImm(-N));
608 int64_t N = Inst.getOperand(2).getImm();
609 int64_t B = Inst.getOperand(3).getImm();
610 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
611 TmpInst.addOperand(Inst.getOperand(0));
612 TmpInst.addOperand(Inst.getOperand(1));
613 TmpInst.addOperand(MCOperand::CreateImm(B));
614 TmpInst.addOperand(MCOperand::CreateImm(0));
615 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
622 int64_t N = Inst.getOperand(2).getImm();
623 int64_t B = Inst.getOperand(3).getImm();
624 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
625 TmpInst.addOperand(Inst.getOperand(0));
626 TmpInst.addOperand(Inst.getOperand(1));
627 TmpInst.addOperand(MCOperand::CreateImm(B + N));
628 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
629 TmpInst.addOperand(MCOperand::CreateImm(31));
636 int64_t N = Inst.getOperand(2).getImm();
637 int64_t B = Inst.getOperand(3).getImm();
638 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
639 TmpInst.addOperand(Inst.getOperand(0));
640 TmpInst.addOperand(Inst.getOperand(0));
641 TmpInst.addOperand(Inst.getOperand(1));
642 TmpInst.addOperand(MCOperand::CreateImm(32 - B));
643 TmpInst.addOperand(MCOperand::CreateImm(B));
644 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
651 int64_t N = Inst.getOperand(2).getImm();
652 int64_t B = Inst.getOperand(3).getImm();
653 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
654 TmpInst.addOperand(Inst.getOperand(0));
655 TmpInst.addOperand(Inst.getOperand(0));
656 TmpInst.addOperand(Inst.getOperand(1));
657 TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
658 TmpInst.addOperand(MCOperand::CreateImm(B));
659 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
666 int64_t N = Inst.getOperand(2).getImm();
667 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
668 TmpInst.addOperand(Inst.getOperand(0));
669 TmpInst.addOperand(Inst.getOperand(1));
670 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
671 TmpInst.addOperand(MCOperand::CreateImm(0));
672 TmpInst.addOperand(MCOperand::CreateImm(31));
679 int64_t N = Inst.getOperand(2).getImm();
680 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
681 TmpInst.addOperand(Inst.getOperand(0));
682 TmpInst.addOperand(Inst.getOperand(1));
683 TmpInst.addOperand(MCOperand::CreateImm(N));
684 TmpInst.addOperand(MCOperand::CreateImm(0));
685 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
692 int64_t N = Inst.getOperand(2).getImm();
693 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
694 TmpInst.addOperand(Inst.getOperand(0));
695 TmpInst.addOperand(Inst.getOperand(1));
696 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
697 TmpInst.addOperand(MCOperand::CreateImm(N));
698 TmpInst.addOperand(MCOperand::CreateImm(31));
705 int64_t N = Inst.getOperand(2).getImm();
706 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
707 TmpInst.addOperand(Inst.getOperand(0));
708 TmpInst.addOperand(Inst.getOperand(1));
709 TmpInst.addOperand(MCOperand::CreateImm(0));
710 TmpInst.addOperand(MCOperand::CreateImm(0));
711 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
716 case PPC::CLRLSLWIo: {
718 int64_t B = Inst.getOperand(2).getImm();
719 int64_t N = Inst.getOperand(3).getImm();
720 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
721 TmpInst.addOperand(Inst.getOperand(0));
722 TmpInst.addOperand(Inst.getOperand(1));
723 TmpInst.addOperand(MCOperand::CreateImm(N));
724 TmpInst.addOperand(MCOperand::CreateImm(B - N));
725 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
732 int64_t N = Inst.getOperand(2).getImm();
733 int64_t B = Inst.getOperand(3).getImm();
734 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
735 TmpInst.addOperand(Inst.getOperand(0));
736 TmpInst.addOperand(Inst.getOperand(1));
737 TmpInst.addOperand(MCOperand::CreateImm(B));
738 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
745 int64_t N = Inst.getOperand(2).getImm();
746 int64_t B = Inst.getOperand(3).getImm();
747 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
748 TmpInst.addOperand(Inst.getOperand(0));
749 TmpInst.addOperand(Inst.getOperand(1));
750 TmpInst.addOperand(MCOperand::CreateImm(B + N));
751 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
758 int64_t N = Inst.getOperand(2).getImm();
759 int64_t B = Inst.getOperand(3).getImm();
760 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
761 TmpInst.addOperand(Inst.getOperand(0));
762 TmpInst.addOperand(Inst.getOperand(0));
763 TmpInst.addOperand(Inst.getOperand(1));
764 TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
765 TmpInst.addOperand(MCOperand::CreateImm(B));
772 int64_t N = Inst.getOperand(2).getImm();
773 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
774 TmpInst.addOperand(Inst.getOperand(0));
775 TmpInst.addOperand(Inst.getOperand(1));
776 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
777 TmpInst.addOperand(MCOperand::CreateImm(0));
784 int64_t N = Inst.getOperand(2).getImm();
785 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
786 TmpInst.addOperand(Inst.getOperand(0));
787 TmpInst.addOperand(Inst.getOperand(1));
788 TmpInst.addOperand(MCOperand::CreateImm(N));
789 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
796 int64_t N = Inst.getOperand(2).getImm();
797 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
798 TmpInst.addOperand(Inst.getOperand(0));
799 TmpInst.addOperand(Inst.getOperand(1));
800 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
801 TmpInst.addOperand(MCOperand::CreateImm(N));
808 int64_t N = Inst.getOperand(2).getImm();
809 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
810 TmpInst.addOperand(Inst.getOperand(0));
811 TmpInst.addOperand(Inst.getOperand(1));
812 TmpInst.addOperand(MCOperand::CreateImm(0));
813 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
818 case PPC::CLRLSLDIo: {
820 int64_t B = Inst.getOperand(2).getImm();
821 int64_t N = Inst.getOperand(3).getImm();
822 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
823 TmpInst.addOperand(Inst.getOperand(0));
824 TmpInst.addOperand(Inst.getOperand(1));
825 TmpInst.addOperand(MCOperand::CreateImm(N));
826 TmpInst.addOperand(MCOperand::CreateImm(B - N));
834 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
835 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
836 MCStreamer &Out, unsigned &ErrorInfo,
837 bool MatchingInlineAsm) {
840 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
843 // Post-process instructions (typically extended mnemonics)
844 ProcessInstruction(Inst, Operands);
846 Out.EmitInstruction(Inst);
848 case Match_MissingFeature:
849 return Error(IDLoc, "instruction use requires an option to be enabled");
850 case Match_MnemonicFail:
851 return Error(IDLoc, "unrecognized instruction mnemonic");
852 case Match_InvalidOperand: {
853 SMLoc ErrorLoc = IDLoc;
854 if (ErrorInfo != ~0U) {
855 if (ErrorInfo >= Operands.size())
856 return Error(IDLoc, "too few operands for instruction");
858 ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc();
859 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
862 return Error(ErrorLoc, "invalid operand for instruction");
866 llvm_unreachable("Implement any new match types added!");
870 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
871 if (Tok.is(AsmToken::Identifier)) {
872 StringRef Name = Tok.getString();
874 if (Name.equals_lower("lr")) {
875 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
878 } else if (Name.equals_lower("ctr")) {
879 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
882 } else if (Name.equals_lower("vrsave")) {
886 } else if (Name.substr(0, 1).equals_lower("r") &&
887 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
888 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
890 } else if (Name.substr(0, 1).equals_lower("f") &&
891 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
892 RegNo = FRegs[IntVal];
894 } else if (Name.substr(0, 1).equals_lower("v") &&
895 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
896 RegNo = VRegs[IntVal];
898 } else if (Name.substr(0, 2).equals_lower("cr") &&
899 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
900 RegNo = CRRegs[IntVal];
909 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
910 const AsmToken &Tok = Parser.getTok();
911 StartLoc = Tok.getLoc();
912 EndLoc = Tok.getEndLoc();
916 if (!MatchRegisterName(Tok, RegNo, IntVal)) {
917 Parser.Lex(); // Eat identifier token.
921 return Error(StartLoc, "invalid register name");
924 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
925 /// the expression and check for VK_PPC_LO/HI/HA
926 /// symbol variants. If all symbols with modifier use the same
927 /// variant, return the corresponding PPCMCExpr::VariantKind,
928 /// and a modified expression using the default symbol variant.
929 /// Otherwise, return NULL.
930 const MCExpr *PPCAsmParser::
931 ExtractModifierFromExpr(const MCExpr *E,
932 PPCMCExpr::VariantKind &Variant) {
933 MCContext &Context = getParser().getContext();
934 Variant = PPCMCExpr::VK_PPC_None;
936 switch (E->getKind()) {
938 case MCExpr::Constant:
941 case MCExpr::SymbolRef: {
942 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
944 switch (SRE->getKind()) {
945 case MCSymbolRefExpr::VK_PPC_LO:
946 Variant = PPCMCExpr::VK_PPC_LO;
948 case MCSymbolRefExpr::VK_PPC_HI:
949 Variant = PPCMCExpr::VK_PPC_HI;
951 case MCSymbolRefExpr::VK_PPC_HA:
952 Variant = PPCMCExpr::VK_PPC_HA;
954 case MCSymbolRefExpr::VK_PPC_HIGHER:
955 Variant = PPCMCExpr::VK_PPC_HIGHER;
957 case MCSymbolRefExpr::VK_PPC_HIGHERA:
958 Variant = PPCMCExpr::VK_PPC_HIGHERA;
960 case MCSymbolRefExpr::VK_PPC_HIGHEST:
961 Variant = PPCMCExpr::VK_PPC_HIGHEST;
963 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
964 Variant = PPCMCExpr::VK_PPC_HIGHESTA;
970 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
973 case MCExpr::Unary: {
974 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
975 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
978 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
981 case MCExpr::Binary: {
982 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
983 PPCMCExpr::VariantKind LHSVariant, RHSVariant;
984 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
985 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
990 if (!LHS) LHS = BE->getLHS();
991 if (!RHS) RHS = BE->getRHS();
993 if (LHSVariant == PPCMCExpr::VK_PPC_None)
994 Variant = RHSVariant;
995 else if (RHSVariant == PPCMCExpr::VK_PPC_None)
996 Variant = LHSVariant;
997 else if (LHSVariant == RHSVariant)
998 Variant = LHSVariant;
1002 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1006 llvm_unreachable("Invalid expression kind!");
1009 /// Parse an expression. This differs from the default "parseExpression"
1010 /// in that it handles complex \code @l/@ha \endcode modifiers.
1012 ParseExpression(const MCExpr *&EVal) {
1013 if (getParser().parseExpression(EVal))
1016 PPCMCExpr::VariantKind Variant;
1017 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1019 EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
1025 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1026 SMLoc S = Parser.getTok().getLoc();
1027 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1031 // Attempt to parse the next token as an immediate
1032 switch (getLexer().getKind()) {
1033 // Special handling for register names. These are interpreted
1034 // as immediates corresponding to the register number.
1035 case AsmToken::Percent:
1036 Parser.Lex(); // Eat the '%'.
1039 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1040 Parser.Lex(); // Eat the identifier token.
1041 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1042 Operands.push_back(Op);
1045 return Error(S, "invalid register name");
1047 // All other expressions
1048 case AsmToken::LParen:
1049 case AsmToken::Plus:
1050 case AsmToken::Minus:
1051 case AsmToken::Integer:
1052 case AsmToken::Identifier:
1054 case AsmToken::Dollar:
1055 if (!ParseExpression(EVal))
1059 return Error(S, "unknown operand");
1062 // Push the parsed operand into the list of operands
1063 Op = PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64());
1064 Operands.push_back(Op);
1066 // Check whether this is a TLS call expression
1067 bool TLSCall = false;
1068 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1069 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1071 if (TLSCall && getLexer().is(AsmToken::LParen)) {
1072 const MCExpr *TLSSym;
1074 Parser.Lex(); // Eat the '('.
1075 S = Parser.getTok().getLoc();
1076 if (ParseExpression(TLSSym))
1077 return Error(S, "invalid TLS call expression");
1078 if (getLexer().isNot(AsmToken::RParen))
1079 return Error(Parser.getTok().getLoc(), "missing ')'");
1080 E = Parser.getTok().getLoc();
1081 Parser.Lex(); // Eat the ')'.
1083 Op = PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64());
1084 Operands.push_back(Op);
1087 // Otherwise, check for D-form memory operands
1088 if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1089 Parser.Lex(); // Eat the '('.
1090 S = Parser.getTok().getLoc();
1093 switch (getLexer().getKind()) {
1094 case AsmToken::Percent:
1095 Parser.Lex(); // Eat the '%'.
1097 if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1098 return Error(S, "invalid register name");
1099 Parser.Lex(); // Eat the identifier token.
1102 case AsmToken::Integer:
1103 if (getParser().parseAbsoluteExpression(IntVal) ||
1104 IntVal < 0 || IntVal > 31)
1105 return Error(S, "invalid register number");
1109 return Error(S, "invalid memory operand");
1112 if (getLexer().isNot(AsmToken::RParen))
1113 return Error(Parser.getTok().getLoc(), "missing ')'");
1114 E = Parser.getTok().getLoc();
1115 Parser.Lex(); // Eat the ')'.
1117 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1118 Operands.push_back(Op);
1124 /// Parse an instruction mnemonic followed by its operands.
1126 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1127 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1128 // The first operand is the token for the instruction name.
1129 // If the next character is a '+' or '-', we need to add it to the
1130 // instruction name, to match what TableGen is doing.
1131 if (getLexer().is(AsmToken::Plus)) {
1133 char *NewOpcode = new char[Name.size() + 1];
1134 memcpy(NewOpcode, Name.data(), Name.size());
1135 NewOpcode[Name.size()] = '+';
1136 Name = StringRef(NewOpcode, Name.size() + 1);
1138 if (getLexer().is(AsmToken::Minus)) {
1140 char *NewOpcode = new char[Name.size() + 1];
1141 memcpy(NewOpcode, Name.data(), Name.size());
1142 NewOpcode[Name.size()] = '-';
1143 Name = StringRef(NewOpcode, Name.size() + 1);
1145 // If the instruction ends in a '.', we need to create a separate
1146 // token for it, to match what TableGen is doing.
1147 size_t Dot = Name.find('.');
1148 StringRef Mnemonic = Name.slice(0, Dot);
1149 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1150 if (Dot != StringRef::npos) {
1151 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1152 StringRef DotStr = Name.slice(Dot, StringRef::npos);
1153 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1156 // If there are no more operands then finish
1157 if (getLexer().is(AsmToken::EndOfStatement))
1160 // Parse the first operand
1161 if (ParseOperand(Operands))
1164 while (getLexer().isNot(AsmToken::EndOfStatement) &&
1165 getLexer().is(AsmToken::Comma)) {
1166 // Consume the comma token
1169 // Parse the next operand
1170 if (ParseOperand(Operands))
1177 /// ParseDirective parses the PPC specific directives
1178 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1179 StringRef IDVal = DirectiveID.getIdentifier();
1180 if (IDVal == ".word")
1181 return ParseDirectiveWord(2, DirectiveID.getLoc());
1182 if (IDVal == ".llong")
1183 return ParseDirectiveWord(8, DirectiveID.getLoc());
1185 return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1186 if (IDVal == ".machine")
1187 return ParseDirectiveMachine(DirectiveID.getLoc());
1191 /// ParseDirectiveWord
1192 /// ::= .word [ expression (, expression)* ]
1193 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1194 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1196 const MCExpr *Value;
1197 if (getParser().parseExpression(Value))
1200 getParser().getStreamer().EmitValue(Value, Size);
1202 if (getLexer().is(AsmToken::EndOfStatement))
1205 if (getLexer().isNot(AsmToken::Comma))
1206 return Error(L, "unexpected token in directive");
1215 /// ParseDirectiveTC
1216 /// ::= .tc [ symbol (, expression)* ]
1217 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1218 // Skip TC symbol, which is only used with XCOFF.
1219 while (getLexer().isNot(AsmToken::EndOfStatement)
1220 && getLexer().isNot(AsmToken::Comma))
1222 if (getLexer().isNot(AsmToken::Comma))
1223 return Error(L, "unexpected token in directive");
1226 // Align to word size.
1227 getParser().getStreamer().EmitValueToAlignment(Size);
1229 // Emit expressions.
1230 return ParseDirectiveWord(Size, L);
1233 /// ParseDirectiveMachine
1234 /// ::= .machine [ cpu | "push" | "pop" ]
1235 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1236 if (getLexer().isNot(AsmToken::Identifier) &&
1237 getLexer().isNot(AsmToken::String))
1238 return Error(L, "unexpected token in directive");
1240 StringRef CPU = Parser.getTok().getIdentifier();
1243 // FIXME: Right now, the parser always allows any available
1244 // instruction, so the .machine directive is not useful.
1245 // Implement ".machine any" (by doing nothing) for the benefit
1246 // of existing assembler code. Likewise, we can then implement
1247 // ".machine push" and ".machine pop" as no-op.
1248 if (CPU != "any" && CPU != "push" && CPU != "pop")
1249 return Error(L, "unrecognized machine type");
1251 if (getLexer().isNot(AsmToken::EndOfStatement))
1252 return Error(L, "unexpected token in directive");
1257 /// Force static initialization.
1258 extern "C" void LLVMInitializePowerPCAsmParser() {
1259 RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1260 RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1263 #define GET_REGISTER_MATCHER
1264 #define GET_MATCHER_IMPLEMENTATION
1265 #include "PPCGenAsmMatcher.inc"
1267 // Define this matcher function after the auto-generated include so we
1268 // have the match class enum definitions.
1269 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
1271 // If the kind is a token for a literal immediate, check if our asm
1272 // operand matches. This is for InstAliases which have a fixed-value
1273 // immediate in the syntax.
1276 case MCK_0: ImmVal = 0; break;
1277 case MCK_1: ImmVal = 1; break;
1278 default: return Match_InvalidOperand;
1281 PPCOperand *Op = static_cast<PPCOperand*>(AsmOp);
1282 if (Op->isImm() && Op->getImm() == ImmVal)
1283 return Match_Success;
1285 return Match_InvalidOperand;