1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "llvm/MC/MCTargetAsmParser.h"
13 #include "llvm/MC/MCStreamer.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCRegisterInfo.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
18 #include "llvm/MC/MCParser/MCAsmLexer.h"
19 #include "llvm/MC/MCParser/MCAsmParser.h"
20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/SmallString.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/StringSwitch.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
34 static unsigned RRegs[32] = {
35 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
36 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
37 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
38 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
39 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
40 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
41 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
42 PPC::R28, PPC::R29, PPC::R30, PPC::R31
44 static unsigned RRegsNoR0[32] = {
46 PPC::R1, PPC::R2, PPC::R3,
47 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
48 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
49 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
50 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
51 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
52 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
53 PPC::R28, PPC::R29, PPC::R30, PPC::R31
55 static unsigned XRegs[32] = {
56 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
57 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
58 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
59 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
60 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
61 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
62 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
63 PPC::X28, PPC::X29, PPC::X30, PPC::X31
65 static unsigned XRegsNoX0[32] = {
67 PPC::X1, PPC::X2, PPC::X3,
68 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
69 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
70 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
71 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
72 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
73 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
74 PPC::X28, PPC::X29, PPC::X30, PPC::X31
76 static unsigned FRegs[32] = {
77 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
78 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
79 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
80 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
81 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
82 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
83 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
84 PPC::F28, PPC::F29, PPC::F30, PPC::F31
86 static unsigned VRegs[32] = {
87 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
88 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
89 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
90 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
91 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
92 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
93 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
94 PPC::V28, PPC::V29, PPC::V30, PPC::V31
96 static unsigned CRBITRegs[32] = {
97 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
98 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
99 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
100 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
101 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
102 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
103 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
104 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
106 static unsigned CRRegs[8] = {
107 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
108 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
111 // Evaluate an expression containing condition register
112 // or condition register field symbols. Returns positive
113 // value on success, or -1 on error.
115 EvaluateCRExpr(const MCExpr *E) {
116 switch (E->getKind()) {
120 case MCExpr::Constant: {
121 int64_t Res = cast<MCConstantExpr>(E)->getValue();
122 return Res < 0 ? -1 : Res;
125 case MCExpr::SymbolRef: {
126 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
127 StringRef Name = SRE->getSymbol().getName();
129 if (Name == "lt") return 0;
130 if (Name == "gt") return 1;
131 if (Name == "eq") return 2;
132 if (Name == "so") return 3;
133 if (Name == "un") return 3;
135 if (Name == "cr0") return 0;
136 if (Name == "cr1") return 1;
137 if (Name == "cr2") return 2;
138 if (Name == "cr3") return 3;
139 if (Name == "cr4") return 4;
140 if (Name == "cr5") return 5;
141 if (Name == "cr6") return 6;
142 if (Name == "cr7") return 7;
150 case MCExpr::Binary: {
151 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
152 int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
153 int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
156 if (LHSVal < 0 || RHSVal < 0)
159 switch (BE->getOpcode()) {
161 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
162 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
165 return Res < 0 ? -1 : Res;
169 llvm_unreachable("Invalid expression kind!");
174 class PPCAsmParser : public MCTargetAsmParser {
175 MCSubtargetInfo &STI;
179 MCAsmParser &getParser() const { return Parser; }
180 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
182 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
183 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
185 bool isPPC64() const { return IsPPC64; }
187 bool MatchRegisterName(const AsmToken &Tok,
188 unsigned &RegNo, int64_t &IntVal);
190 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
192 const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
193 PPCMCExpr::VariantKind &Variant);
194 const MCExpr *FixupVariantKind(const MCExpr *E);
195 bool ParseExpression(const MCExpr *&EVal);
197 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
199 bool ParseDirectiveWord(unsigned Size, SMLoc L);
200 bool ParseDirectiveTC(unsigned Size, SMLoc L);
201 bool ParseDirectiveMachine(SMLoc L);
203 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
204 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
205 MCStreamer &Out, unsigned &ErrorInfo,
206 bool MatchingInlineAsm);
208 void ProcessInstruction(MCInst &Inst,
209 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
211 /// @name Auto-generated Match Functions
214 #define GET_ASSEMBLER_HEADER
215 #include "PPCGenAsmMatcher.inc"
221 PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
222 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
223 // Check for 64-bit vs. 32-bit pointer mode.
224 Triple TheTriple(STI.getTargetTriple());
225 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
226 TheTriple.getArch() == Triple::ppc64le);
227 // Initialize the set of available features.
228 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
231 virtual bool ParseInstruction(ParseInstructionInfo &Info,
232 StringRef Name, SMLoc NameLoc,
233 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
235 virtual bool ParseDirective(AsmToken DirectiveID);
237 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
239 virtual const MCExpr *applyModifierToExpr(const MCExpr *E,
240 MCSymbolRefExpr::VariantKind,
244 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
246 struct PPCOperand : public MCParsedAsmOperand {
254 SMLoc StartLoc, EndLoc;
268 int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
272 const MCSymbolRefExpr *Sym;
279 struct TLSRegOp TLSReg;
282 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
284 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
286 StartLoc = o.StartLoc;
305 /// getStartLoc - Get the location of the first token of this operand.
306 SMLoc getStartLoc() const { return StartLoc; }
308 /// getEndLoc - Get the location of the last token of this operand.
309 SMLoc getEndLoc() const { return EndLoc; }
311 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
312 bool isPPC64() const { return IsPPC64; }
314 int64_t getImm() const {
315 assert(Kind == Immediate && "Invalid access!");
319 const MCExpr *getExpr() const {
320 assert(Kind == Expression && "Invalid access!");
324 int64_t getExprCRVal() const {
325 assert(Kind == Expression && "Invalid access!");
329 const MCExpr *getTLSReg() const {
330 assert(Kind == TLSRegister && "Invalid access!");
334 unsigned getReg() const {
335 assert(isRegNumber() && "Invalid access!");
336 return (unsigned) Imm.Val;
339 unsigned getCCReg() const {
340 assert(isCCRegNumber() && "Invalid access!");
341 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
344 unsigned getCRBit() const {
345 assert(isCRBitNumber() && "Invalid access!");
346 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
349 unsigned getCRBitMask() const {
350 assert(isCRBitMask() && "Invalid access!");
351 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
354 bool isToken() const { return Kind == Token; }
355 bool isImm() const { return Kind == Immediate || Kind == Expression; }
356 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
357 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
358 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
359 bool isU16Imm() const { return Kind == Expression ||
360 (Kind == Immediate && isUInt<16>(getImm())); }
361 bool isS16Imm() const { return Kind == Expression ||
362 (Kind == Immediate && isInt<16>(getImm())); }
363 bool isS16ImmX4() const { return Kind == Expression ||
364 (Kind == Immediate && isInt<16>(getImm()) &&
365 (getImm() & 3) == 0); }
366 bool isS17Imm() const { return Kind == Expression ||
367 (Kind == Immediate && isInt<17>(getImm())); }
368 bool isTLSReg() const { return Kind == TLSRegister; }
369 bool isDirectBr() const { return Kind == Expression ||
370 (Kind == Immediate && isInt<26>(getImm()) &&
371 (getImm() & 3) == 0); }
372 bool isCondBr() const { return Kind == Expression ||
373 (Kind == Immediate && isInt<16>(getImm()) &&
374 (getImm() & 3) == 0); }
375 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
376 bool isCCRegNumber() const { return (Kind == Expression
377 && isUInt<3>(getExprCRVal())) ||
379 && isUInt<3>(getImm())); }
380 bool isCRBitNumber() const { return (Kind == Expression
381 && isUInt<5>(getExprCRVal())) ||
383 && isUInt<5>(getImm())); }
384 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
385 isPowerOf2_32(getImm()); }
386 bool isMem() const { return false; }
387 bool isReg() const { return false; }
389 void addRegOperands(MCInst &Inst, unsigned N) const {
390 llvm_unreachable("addRegOperands");
393 void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
394 assert(N == 1 && "Invalid number of operands!");
395 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
398 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
399 assert(N == 1 && "Invalid number of operands!");
400 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
403 void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
404 assert(N == 1 && "Invalid number of operands!");
405 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
408 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
409 assert(N == 1 && "Invalid number of operands!");
410 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
413 void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
415 addRegG8RCOperands(Inst, N);
417 addRegGPRCOperands(Inst, N);
420 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
422 addRegG8RCNoX0Operands(Inst, N);
424 addRegGPRCNoR0Operands(Inst, N);
427 void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
428 assert(N == 1 && "Invalid number of operands!");
429 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
432 void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
433 assert(N == 1 && "Invalid number of operands!");
434 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
437 void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
438 assert(N == 1 && "Invalid number of operands!");
439 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
442 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
443 assert(N == 1 && "Invalid number of operands!");
444 Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
447 void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
448 assert(N == 1 && "Invalid number of operands!");
449 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
452 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
453 assert(N == 1 && "Invalid number of operands!");
454 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
457 void addImmOperands(MCInst &Inst, unsigned N) const {
458 assert(N == 1 && "Invalid number of operands!");
459 if (Kind == Immediate)
460 Inst.addOperand(MCOperand::CreateImm(getImm()));
462 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
465 void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
466 assert(N == 1 && "Invalid number of operands!");
467 if (Kind == Immediate)
468 Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
470 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
473 void addTLSRegOperands(MCInst &Inst, unsigned N) const {
474 assert(N == 1 && "Invalid number of operands!");
475 Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
478 StringRef getToken() const {
479 assert(Kind == Token && "Invalid access!");
480 return StringRef(Tok.Data, Tok.Length);
483 virtual void print(raw_ostream &OS) const;
485 static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) {
486 PPCOperand *Op = new PPCOperand(Token);
487 Op->Tok.Data = Str.data();
488 Op->Tok.Length = Str.size();
491 Op->IsPPC64 = IsPPC64;
495 static PPCOperand *CreateTokenWithStringCopy(StringRef Str, SMLoc S,
497 // Allocate extra memory for the string and copy it.
498 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
499 PPCOperand *Op = new (Mem) PPCOperand(Token);
500 Op->Tok.Data = (const char *)(Op + 1);
501 Op->Tok.Length = Str.size();
502 std::memcpy((char *)(Op + 1), Str.data(), Str.size());
505 Op->IsPPC64 = IsPPC64;
509 static PPCOperand *CreateImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
510 PPCOperand *Op = new PPCOperand(Immediate);
514 Op->IsPPC64 = IsPPC64;
518 static PPCOperand *CreateExpr(const MCExpr *Val,
519 SMLoc S, SMLoc E, bool IsPPC64) {
520 PPCOperand *Op = new PPCOperand(Expression);
522 Op->Expr.CRVal = EvaluateCRExpr(Val);
525 Op->IsPPC64 = IsPPC64;
529 static PPCOperand *CreateTLSReg(const MCSymbolRefExpr *Sym,
530 SMLoc S, SMLoc E, bool IsPPC64) {
531 PPCOperand *Op = new PPCOperand(TLSRegister);
532 Op->TLSReg.Sym = Sym;
535 Op->IsPPC64 = IsPPC64;
539 static PPCOperand *CreateFromMCExpr(const MCExpr *Val,
540 SMLoc S, SMLoc E, bool IsPPC64) {
541 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
542 return CreateImm(CE->getValue(), S, E, IsPPC64);
544 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
545 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
546 return CreateTLSReg(SRE, S, E, IsPPC64);
548 return CreateExpr(Val, S, E, IsPPC64);
552 } // end anonymous namespace.
554 void PPCOperand::print(raw_ostream &OS) const {
557 OS << "'" << getToken() << "'";
563 getExpr()->print(OS);
566 getTLSReg()->print(OS);
573 ProcessInstruction(MCInst &Inst,
574 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
575 int Opcode = Inst.getOpcode();
579 TmpInst.setOpcode(PPC::LA);
580 TmpInst.addOperand(Inst.getOperand(0));
581 TmpInst.addOperand(Inst.getOperand(2));
582 TmpInst.addOperand(Inst.getOperand(1));
588 int64_t N = Inst.getOperand(2).getImm();
589 TmpInst.setOpcode(PPC::ADDI);
590 TmpInst.addOperand(Inst.getOperand(0));
591 TmpInst.addOperand(Inst.getOperand(1));
592 TmpInst.addOperand(MCOperand::CreateImm(-N));
598 int64_t N = Inst.getOperand(2).getImm();
599 TmpInst.setOpcode(PPC::ADDIS);
600 TmpInst.addOperand(Inst.getOperand(0));
601 TmpInst.addOperand(Inst.getOperand(1));
602 TmpInst.addOperand(MCOperand::CreateImm(-N));
608 int64_t N = Inst.getOperand(2).getImm();
609 TmpInst.setOpcode(PPC::ADDIC);
610 TmpInst.addOperand(Inst.getOperand(0));
611 TmpInst.addOperand(Inst.getOperand(1));
612 TmpInst.addOperand(MCOperand::CreateImm(-N));
618 int64_t N = Inst.getOperand(2).getImm();
619 TmpInst.setOpcode(PPC::ADDICo);
620 TmpInst.addOperand(Inst.getOperand(0));
621 TmpInst.addOperand(Inst.getOperand(1));
622 TmpInst.addOperand(MCOperand::CreateImm(-N));
629 int64_t N = Inst.getOperand(2).getImm();
630 int64_t B = Inst.getOperand(3).getImm();
631 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
632 TmpInst.addOperand(Inst.getOperand(0));
633 TmpInst.addOperand(Inst.getOperand(1));
634 TmpInst.addOperand(MCOperand::CreateImm(B));
635 TmpInst.addOperand(MCOperand::CreateImm(0));
636 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
643 int64_t N = Inst.getOperand(2).getImm();
644 int64_t B = Inst.getOperand(3).getImm();
645 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
646 TmpInst.addOperand(Inst.getOperand(0));
647 TmpInst.addOperand(Inst.getOperand(1));
648 TmpInst.addOperand(MCOperand::CreateImm(B + N));
649 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
650 TmpInst.addOperand(MCOperand::CreateImm(31));
657 int64_t N = Inst.getOperand(2).getImm();
658 int64_t B = Inst.getOperand(3).getImm();
659 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
660 TmpInst.addOperand(Inst.getOperand(0));
661 TmpInst.addOperand(Inst.getOperand(0));
662 TmpInst.addOperand(Inst.getOperand(1));
663 TmpInst.addOperand(MCOperand::CreateImm(32 - B));
664 TmpInst.addOperand(MCOperand::CreateImm(B));
665 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
672 int64_t N = Inst.getOperand(2).getImm();
673 int64_t B = Inst.getOperand(3).getImm();
674 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
675 TmpInst.addOperand(Inst.getOperand(0));
676 TmpInst.addOperand(Inst.getOperand(0));
677 TmpInst.addOperand(Inst.getOperand(1));
678 TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
679 TmpInst.addOperand(MCOperand::CreateImm(B));
680 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
687 int64_t N = Inst.getOperand(2).getImm();
688 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
689 TmpInst.addOperand(Inst.getOperand(0));
690 TmpInst.addOperand(Inst.getOperand(1));
691 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
692 TmpInst.addOperand(MCOperand::CreateImm(0));
693 TmpInst.addOperand(MCOperand::CreateImm(31));
700 int64_t N = Inst.getOperand(2).getImm();
701 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
702 TmpInst.addOperand(Inst.getOperand(0));
703 TmpInst.addOperand(Inst.getOperand(1));
704 TmpInst.addOperand(MCOperand::CreateImm(N));
705 TmpInst.addOperand(MCOperand::CreateImm(0));
706 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
713 int64_t N = Inst.getOperand(2).getImm();
714 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
715 TmpInst.addOperand(Inst.getOperand(0));
716 TmpInst.addOperand(Inst.getOperand(1));
717 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
718 TmpInst.addOperand(MCOperand::CreateImm(N));
719 TmpInst.addOperand(MCOperand::CreateImm(31));
726 int64_t N = Inst.getOperand(2).getImm();
727 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
728 TmpInst.addOperand(Inst.getOperand(0));
729 TmpInst.addOperand(Inst.getOperand(1));
730 TmpInst.addOperand(MCOperand::CreateImm(0));
731 TmpInst.addOperand(MCOperand::CreateImm(0));
732 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
737 case PPC::CLRLSLWIo: {
739 int64_t B = Inst.getOperand(2).getImm();
740 int64_t N = Inst.getOperand(3).getImm();
741 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
742 TmpInst.addOperand(Inst.getOperand(0));
743 TmpInst.addOperand(Inst.getOperand(1));
744 TmpInst.addOperand(MCOperand::CreateImm(N));
745 TmpInst.addOperand(MCOperand::CreateImm(B - N));
746 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
753 int64_t N = Inst.getOperand(2).getImm();
754 int64_t B = Inst.getOperand(3).getImm();
755 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
756 TmpInst.addOperand(Inst.getOperand(0));
757 TmpInst.addOperand(Inst.getOperand(1));
758 TmpInst.addOperand(MCOperand::CreateImm(B));
759 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
766 int64_t N = Inst.getOperand(2).getImm();
767 int64_t B = Inst.getOperand(3).getImm();
768 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
769 TmpInst.addOperand(Inst.getOperand(0));
770 TmpInst.addOperand(Inst.getOperand(1));
771 TmpInst.addOperand(MCOperand::CreateImm(B + N));
772 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
779 int64_t N = Inst.getOperand(2).getImm();
780 int64_t B = Inst.getOperand(3).getImm();
781 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
782 TmpInst.addOperand(Inst.getOperand(0));
783 TmpInst.addOperand(Inst.getOperand(0));
784 TmpInst.addOperand(Inst.getOperand(1));
785 TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
786 TmpInst.addOperand(MCOperand::CreateImm(B));
793 int64_t N = Inst.getOperand(2).getImm();
794 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
795 TmpInst.addOperand(Inst.getOperand(0));
796 TmpInst.addOperand(Inst.getOperand(1));
797 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
798 TmpInst.addOperand(MCOperand::CreateImm(0));
805 int64_t N = Inst.getOperand(2).getImm();
806 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
807 TmpInst.addOperand(Inst.getOperand(0));
808 TmpInst.addOperand(Inst.getOperand(1));
809 TmpInst.addOperand(MCOperand::CreateImm(N));
810 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
817 int64_t N = Inst.getOperand(2).getImm();
818 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
819 TmpInst.addOperand(Inst.getOperand(0));
820 TmpInst.addOperand(Inst.getOperand(1));
821 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
822 TmpInst.addOperand(MCOperand::CreateImm(N));
829 int64_t N = Inst.getOperand(2).getImm();
830 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
831 TmpInst.addOperand(Inst.getOperand(0));
832 TmpInst.addOperand(Inst.getOperand(1));
833 TmpInst.addOperand(MCOperand::CreateImm(0));
834 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
839 case PPC::CLRLSLDIo: {
841 int64_t B = Inst.getOperand(2).getImm();
842 int64_t N = Inst.getOperand(3).getImm();
843 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
844 TmpInst.addOperand(Inst.getOperand(0));
845 TmpInst.addOperand(Inst.getOperand(1));
846 TmpInst.addOperand(MCOperand::CreateImm(N));
847 TmpInst.addOperand(MCOperand::CreateImm(B - N));
855 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
856 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
857 MCStreamer &Out, unsigned &ErrorInfo,
858 bool MatchingInlineAsm) {
861 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
864 // Post-process instructions (typically extended mnemonics)
865 ProcessInstruction(Inst, Operands);
867 Out.EmitInstruction(Inst);
869 case Match_MissingFeature:
870 return Error(IDLoc, "instruction use requires an option to be enabled");
871 case Match_MnemonicFail:
872 return Error(IDLoc, "unrecognized instruction mnemonic");
873 case Match_InvalidOperand: {
874 SMLoc ErrorLoc = IDLoc;
875 if (ErrorInfo != ~0U) {
876 if (ErrorInfo >= Operands.size())
877 return Error(IDLoc, "too few operands for instruction");
879 ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc();
880 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
883 return Error(ErrorLoc, "invalid operand for instruction");
887 llvm_unreachable("Implement any new match types added!");
891 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
892 if (Tok.is(AsmToken::Identifier)) {
893 StringRef Name = Tok.getString();
895 if (Name.equals_lower("lr")) {
896 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
899 } else if (Name.equals_lower("ctr")) {
900 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
903 } else if (Name.equals_lower("vrsave")) {
907 } else if (Name.substr(0, 1).equals_lower("r") &&
908 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
909 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
911 } else if (Name.substr(0, 1).equals_lower("f") &&
912 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
913 RegNo = FRegs[IntVal];
915 } else if (Name.substr(0, 1).equals_lower("v") &&
916 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
917 RegNo = VRegs[IntVal];
919 } else if (Name.substr(0, 2).equals_lower("cr") &&
920 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
921 RegNo = CRRegs[IntVal];
930 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
931 const AsmToken &Tok = Parser.getTok();
932 StartLoc = Tok.getLoc();
933 EndLoc = Tok.getEndLoc();
937 if (!MatchRegisterName(Tok, RegNo, IntVal)) {
938 Parser.Lex(); // Eat identifier token.
942 return Error(StartLoc, "invalid register name");
945 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
946 /// the expression and check for VK_PPC_LO/HI/HA
947 /// symbol variants. If all symbols with modifier use the same
948 /// variant, return the corresponding PPCMCExpr::VariantKind,
949 /// and a modified expression using the default symbol variant.
950 /// Otherwise, return NULL.
951 const MCExpr *PPCAsmParser::
952 ExtractModifierFromExpr(const MCExpr *E,
953 PPCMCExpr::VariantKind &Variant) {
954 MCContext &Context = getParser().getContext();
955 Variant = PPCMCExpr::VK_PPC_None;
957 switch (E->getKind()) {
959 case MCExpr::Constant:
962 case MCExpr::SymbolRef: {
963 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
965 switch (SRE->getKind()) {
966 case MCSymbolRefExpr::VK_PPC_LO:
967 Variant = PPCMCExpr::VK_PPC_LO;
969 case MCSymbolRefExpr::VK_PPC_HI:
970 Variant = PPCMCExpr::VK_PPC_HI;
972 case MCSymbolRefExpr::VK_PPC_HA:
973 Variant = PPCMCExpr::VK_PPC_HA;
975 case MCSymbolRefExpr::VK_PPC_HIGHER:
976 Variant = PPCMCExpr::VK_PPC_HIGHER;
978 case MCSymbolRefExpr::VK_PPC_HIGHERA:
979 Variant = PPCMCExpr::VK_PPC_HIGHERA;
981 case MCSymbolRefExpr::VK_PPC_HIGHEST:
982 Variant = PPCMCExpr::VK_PPC_HIGHEST;
984 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
985 Variant = PPCMCExpr::VK_PPC_HIGHESTA;
991 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
994 case MCExpr::Unary: {
995 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
996 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
999 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1002 case MCExpr::Binary: {
1003 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1004 PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1005 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1006 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1011 if (!LHS) LHS = BE->getLHS();
1012 if (!RHS) RHS = BE->getRHS();
1014 if (LHSVariant == PPCMCExpr::VK_PPC_None)
1015 Variant = RHSVariant;
1016 else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1017 Variant = LHSVariant;
1018 else if (LHSVariant == RHSVariant)
1019 Variant = LHSVariant;
1023 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1027 llvm_unreachable("Invalid expression kind!");
1030 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1031 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having
1032 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1033 /// FIXME: This is a hack.
1034 const MCExpr *PPCAsmParser::
1035 FixupVariantKind(const MCExpr *E) {
1036 MCContext &Context = getParser().getContext();
1038 switch (E->getKind()) {
1039 case MCExpr::Target:
1040 case MCExpr::Constant:
1043 case MCExpr::SymbolRef: {
1044 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1045 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1047 switch (SRE->getKind()) {
1048 case MCSymbolRefExpr::VK_TLSGD:
1049 Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1051 case MCSymbolRefExpr::VK_TLSLD:
1052 Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1057 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context);
1060 case MCExpr::Unary: {
1061 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1062 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1063 if (Sub == UE->getSubExpr())
1065 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1068 case MCExpr::Binary: {
1069 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1070 const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1071 const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1072 if (LHS == BE->getLHS() && RHS == BE->getRHS())
1074 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1078 llvm_unreachable("Invalid expression kind!");
1081 /// Parse an expression. This differs from the default "parseExpression"
1082 /// in that it handles complex \code @l/@ha \endcode modifiers.
1084 ParseExpression(const MCExpr *&EVal) {
1085 if (getParser().parseExpression(EVal))
1088 EVal = FixupVariantKind(EVal);
1090 PPCMCExpr::VariantKind Variant;
1091 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1093 EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
1099 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1100 SMLoc S = Parser.getTok().getLoc();
1101 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1105 // Attempt to parse the next token as an immediate
1106 switch (getLexer().getKind()) {
1107 // Special handling for register names. These are interpreted
1108 // as immediates corresponding to the register number.
1109 case AsmToken::Percent:
1110 Parser.Lex(); // Eat the '%'.
1113 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1114 Parser.Lex(); // Eat the identifier token.
1115 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1116 Operands.push_back(Op);
1119 return Error(S, "invalid register name");
1121 // All other expressions
1122 case AsmToken::LParen:
1123 case AsmToken::Plus:
1124 case AsmToken::Minus:
1125 case AsmToken::Integer:
1126 case AsmToken::Identifier:
1128 case AsmToken::Dollar:
1129 if (!ParseExpression(EVal))
1133 return Error(S, "unknown operand");
1136 // Push the parsed operand into the list of operands
1137 Op = PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64());
1138 Operands.push_back(Op);
1140 // Check whether this is a TLS call expression
1141 bool TLSCall = false;
1142 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1143 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1145 if (TLSCall && getLexer().is(AsmToken::LParen)) {
1146 const MCExpr *TLSSym;
1148 Parser.Lex(); // Eat the '('.
1149 S = Parser.getTok().getLoc();
1150 if (ParseExpression(TLSSym))
1151 return Error(S, "invalid TLS call expression");
1152 if (getLexer().isNot(AsmToken::RParen))
1153 return Error(Parser.getTok().getLoc(), "missing ')'");
1154 E = Parser.getTok().getLoc();
1155 Parser.Lex(); // Eat the ')'.
1157 Op = PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64());
1158 Operands.push_back(Op);
1161 // Otherwise, check for D-form memory operands
1162 if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1163 Parser.Lex(); // Eat the '('.
1164 S = Parser.getTok().getLoc();
1167 switch (getLexer().getKind()) {
1168 case AsmToken::Percent:
1169 Parser.Lex(); // Eat the '%'.
1171 if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1172 return Error(S, "invalid register name");
1173 Parser.Lex(); // Eat the identifier token.
1176 case AsmToken::Integer:
1177 if (getParser().parseAbsoluteExpression(IntVal) ||
1178 IntVal < 0 || IntVal > 31)
1179 return Error(S, "invalid register number");
1183 return Error(S, "invalid memory operand");
1186 if (getLexer().isNot(AsmToken::RParen))
1187 return Error(Parser.getTok().getLoc(), "missing ')'");
1188 E = Parser.getTok().getLoc();
1189 Parser.Lex(); // Eat the ')'.
1191 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1192 Operands.push_back(Op);
1198 /// Parse an instruction mnemonic followed by its operands.
1200 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1201 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1202 // The first operand is the token for the instruction name.
1203 // If the next character is a '+' or '-', we need to add it to the
1204 // instruction name, to match what TableGen is doing.
1205 std::string NewOpcode;
1206 if (getLexer().is(AsmToken::Plus)) {
1212 if (getLexer().is(AsmToken::Minus)) {
1218 // If the instruction ends in a '.', we need to create a separate
1219 // token for it, to match what TableGen is doing.
1220 size_t Dot = Name.find('.');
1221 StringRef Mnemonic = Name.slice(0, Dot);
1222 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1224 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1226 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1227 if (Dot != StringRef::npos) {
1228 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1229 StringRef DotStr = Name.slice(Dot, StringRef::npos);
1230 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1232 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1234 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1237 // If there are no more operands then finish
1238 if (getLexer().is(AsmToken::EndOfStatement))
1241 // Parse the first operand
1242 if (ParseOperand(Operands))
1245 while (getLexer().isNot(AsmToken::EndOfStatement) &&
1246 getLexer().is(AsmToken::Comma)) {
1247 // Consume the comma token
1250 // Parse the next operand
1251 if (ParseOperand(Operands))
1258 /// ParseDirective parses the PPC specific directives
1259 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1260 StringRef IDVal = DirectiveID.getIdentifier();
1261 if (IDVal == ".word")
1262 return ParseDirectiveWord(2, DirectiveID.getLoc());
1263 if (IDVal == ".llong")
1264 return ParseDirectiveWord(8, DirectiveID.getLoc());
1266 return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1267 if (IDVal == ".machine")
1268 return ParseDirectiveMachine(DirectiveID.getLoc());
1272 /// ParseDirectiveWord
1273 /// ::= .word [ expression (, expression)* ]
1274 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1275 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1277 const MCExpr *Value;
1278 if (getParser().parseExpression(Value))
1281 getParser().getStreamer().EmitValue(Value, Size);
1283 if (getLexer().is(AsmToken::EndOfStatement))
1286 if (getLexer().isNot(AsmToken::Comma))
1287 return Error(L, "unexpected token in directive");
1296 /// ParseDirectiveTC
1297 /// ::= .tc [ symbol (, expression)* ]
1298 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1299 // Skip TC symbol, which is only used with XCOFF.
1300 while (getLexer().isNot(AsmToken::EndOfStatement)
1301 && getLexer().isNot(AsmToken::Comma))
1303 if (getLexer().isNot(AsmToken::Comma))
1304 return Error(L, "unexpected token in directive");
1307 // Align to word size.
1308 getParser().getStreamer().EmitValueToAlignment(Size);
1310 // Emit expressions.
1311 return ParseDirectiveWord(Size, L);
1314 /// ParseDirectiveMachine
1315 /// ::= .machine [ cpu | "push" | "pop" ]
1316 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1317 if (getLexer().isNot(AsmToken::Identifier) &&
1318 getLexer().isNot(AsmToken::String))
1319 return Error(L, "unexpected token in directive");
1321 StringRef CPU = Parser.getTok().getIdentifier();
1324 // FIXME: Right now, the parser always allows any available
1325 // instruction, so the .machine directive is not useful.
1326 // Implement ".machine any" (by doing nothing) for the benefit
1327 // of existing assembler code. Likewise, we can then implement
1328 // ".machine push" and ".machine pop" as no-op.
1329 if (CPU != "any" && CPU != "push" && CPU != "pop")
1330 return Error(L, "unrecognized machine type");
1332 if (getLexer().isNot(AsmToken::EndOfStatement))
1333 return Error(L, "unexpected token in directive");
1338 /// Force static initialization.
1339 extern "C" void LLVMInitializePowerPCAsmParser() {
1340 RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1341 RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1342 RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1345 #define GET_REGISTER_MATCHER
1346 #define GET_MATCHER_IMPLEMENTATION
1347 #include "PPCGenAsmMatcher.inc"
1349 // Define this matcher function after the auto-generated include so we
1350 // have the match class enum definitions.
1351 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
1353 // If the kind is a token for a literal immediate, check if our asm
1354 // operand matches. This is for InstAliases which have a fixed-value
1355 // immediate in the syntax.
1358 case MCK_0: ImmVal = 0; break;
1359 case MCK_1: ImmVal = 1; break;
1360 default: return Match_InvalidOperand;
1363 PPCOperand *Op = static_cast<PPCOperand*>(AsmOp);
1364 if (Op->isImm() && Op->getImm() == ImmVal)
1365 return Match_Success;
1367 return Match_InvalidOperand;
1371 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1372 MCSymbolRefExpr::VariantKind Variant,
1375 case MCSymbolRefExpr::VK_PPC_LO:
1376 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1377 case MCSymbolRefExpr::VK_PPC_HI:
1378 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1379 case MCSymbolRefExpr::VK_PPC_HA:
1380 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1381 case MCSymbolRefExpr::VK_PPC_HIGHER:
1382 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1383 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1384 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1385 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1386 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1387 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1388 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);