1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "llvm/MC/MCTargetAsmParser.h"
13 #include "llvm/MC/MCStreamer.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCInstrInfo.h"
17 #include "llvm/MC/MCRegisterInfo.h"
18 #include "llvm/MC/MCSubtargetInfo.h"
19 #include "llvm/MC/MCParser/MCAsmLexer.h"
20 #include "llvm/MC/MCParser/MCAsmParser.h"
21 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/Twine.h"
27 #include "llvm/Support/SourceMgr.h"
28 #include "llvm/Support/TargetRegistry.h"
29 #include "llvm/Support/raw_ostream.h"
35 static unsigned RRegs[32] = {
36 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
37 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
38 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
39 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
40 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
41 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
42 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
43 PPC::R28, PPC::R29, PPC::R30, PPC::R31
45 static unsigned RRegsNoR0[32] = {
47 PPC::R1, PPC::R2, PPC::R3,
48 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
49 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
50 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
51 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
52 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
53 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
54 PPC::R28, PPC::R29, PPC::R30, PPC::R31
56 static unsigned XRegs[32] = {
57 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
58 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
59 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
60 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
61 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
62 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
63 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
64 PPC::X28, PPC::X29, PPC::X30, PPC::X31
66 static unsigned XRegsNoX0[32] = {
68 PPC::X1, PPC::X2, PPC::X3,
69 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
70 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
71 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
72 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
73 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
74 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
75 PPC::X28, PPC::X29, PPC::X30, PPC::X31
77 static unsigned FRegs[32] = {
78 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
79 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
80 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
81 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
82 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
83 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
84 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
85 PPC::F28, PPC::F29, PPC::F30, PPC::F31
87 static unsigned VRegs[32] = {
88 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
89 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
90 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
91 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
92 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
93 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
94 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
95 PPC::V28, PPC::V29, PPC::V30, PPC::V31
97 static unsigned CRBITRegs[32] = {
98 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
99 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
100 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
101 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
102 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
103 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
104 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
105 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
107 static unsigned CRRegs[8] = {
108 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
109 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
112 // Evaluate an expression containing condition register
113 // or condition register field symbols. Returns positive
114 // value on success, or -1 on error.
116 EvaluateCRExpr(const MCExpr *E) {
117 switch (E->getKind()) {
121 case MCExpr::Constant: {
122 int64_t Res = cast<MCConstantExpr>(E)->getValue();
123 return Res < 0 ? -1 : Res;
126 case MCExpr::SymbolRef: {
127 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
128 StringRef Name = SRE->getSymbol().getName();
130 if (Name == "lt") return 0;
131 if (Name == "gt") return 1;
132 if (Name == "eq") return 2;
133 if (Name == "so") return 3;
134 if (Name == "un") return 3;
136 if (Name == "cr0") return 0;
137 if (Name == "cr1") return 1;
138 if (Name == "cr2") return 2;
139 if (Name == "cr3") return 3;
140 if (Name == "cr4") return 4;
141 if (Name == "cr5") return 5;
142 if (Name == "cr6") return 6;
143 if (Name == "cr7") return 7;
151 case MCExpr::Binary: {
152 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
153 int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
154 int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
157 if (LHSVal < 0 || RHSVal < 0)
160 switch (BE->getOpcode()) {
162 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
163 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
166 return Res < 0 ? -1 : Res;
170 llvm_unreachable("Invalid expression kind!");
175 class PPCAsmParser : public MCTargetAsmParser {
176 MCSubtargetInfo &STI;
178 const MCInstrInfo &MII;
182 MCAsmParser &getParser() const { return Parser; }
183 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
185 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
186 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
188 bool isPPC64() const { return IsPPC64; }
189 bool isDarwin() const { return IsDarwin; }
191 bool MatchRegisterName(const AsmToken &Tok,
192 unsigned &RegNo, int64_t &IntVal);
194 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
196 const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
197 PPCMCExpr::VariantKind &Variant);
198 const MCExpr *FixupVariantKind(const MCExpr *E);
199 bool ParseExpression(const MCExpr *&EVal);
200 bool ParseDarwinExpression(const MCExpr *&EVal);
202 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
204 bool ParseDirectiveWord(unsigned Size, SMLoc L);
205 bool ParseDirectiveTC(unsigned Size, SMLoc L);
206 bool ParseDirectiveMachine(SMLoc L);
207 bool ParseDarwinDirectiveMachine(SMLoc L);
209 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
210 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
211 MCStreamer &Out, unsigned &ErrorInfo,
212 bool MatchingInlineAsm);
214 void ProcessInstruction(MCInst &Inst,
215 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
217 /// @name Auto-generated Match Functions
220 #define GET_ASSEMBLER_HEADER
221 #include "PPCGenAsmMatcher.inc"
227 PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
228 const MCInstrInfo &_MII)
229 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(_MII) {
230 // Check for 64-bit vs. 32-bit pointer mode.
231 Triple TheTriple(STI.getTargetTriple());
232 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
233 TheTriple.getArch() == Triple::ppc64le);
234 IsDarwin = TheTriple.isMacOSX();
235 // Initialize the set of available features.
236 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
239 virtual bool ParseInstruction(ParseInstructionInfo &Info,
240 StringRef Name, SMLoc NameLoc,
241 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
243 virtual bool ParseDirective(AsmToken DirectiveID);
245 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
247 virtual const MCExpr *applyModifierToExpr(const MCExpr *E,
248 MCSymbolRefExpr::VariantKind,
252 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
254 struct PPCOperand : public MCParsedAsmOperand {
262 SMLoc StartLoc, EndLoc;
276 int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
280 const MCSymbolRefExpr *Sym;
287 struct TLSRegOp TLSReg;
290 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
292 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
294 StartLoc = o.StartLoc;
313 /// getStartLoc - Get the location of the first token of this operand.
314 SMLoc getStartLoc() const { return StartLoc; }
316 /// getEndLoc - Get the location of the last token of this operand.
317 SMLoc getEndLoc() const { return EndLoc; }
319 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
320 bool isPPC64() const { return IsPPC64; }
322 int64_t getImm() const {
323 assert(Kind == Immediate && "Invalid access!");
327 const MCExpr *getExpr() const {
328 assert(Kind == Expression && "Invalid access!");
332 int64_t getExprCRVal() const {
333 assert(Kind == Expression && "Invalid access!");
337 const MCExpr *getTLSReg() const {
338 assert(Kind == TLSRegister && "Invalid access!");
342 unsigned getReg() const {
343 assert(isRegNumber() && "Invalid access!");
344 return (unsigned) Imm.Val;
347 unsigned getCCReg() const {
348 assert(isCCRegNumber() && "Invalid access!");
349 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
352 unsigned getCRBit() const {
353 assert(isCRBitNumber() && "Invalid access!");
354 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
357 unsigned getCRBitMask() const {
358 assert(isCRBitMask() && "Invalid access!");
359 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
362 bool isToken() const { return Kind == Token; }
363 bool isImm() const { return Kind == Immediate || Kind == Expression; }
364 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
365 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
366 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
367 bool isU16Imm() const { return Kind == Expression ||
368 (Kind == Immediate && isUInt<16>(getImm())); }
369 bool isS16Imm() const { return Kind == Expression ||
370 (Kind == Immediate && isInt<16>(getImm())); }
371 bool isS16ImmX4() const { return Kind == Expression ||
372 (Kind == Immediate && isInt<16>(getImm()) &&
373 (getImm() & 3) == 0); }
374 bool isS17Imm() const { return Kind == Expression ||
375 (Kind == Immediate && isInt<17>(getImm())); }
376 bool isTLSReg() const { return Kind == TLSRegister; }
377 bool isDirectBr() const { return Kind == Expression ||
378 (Kind == Immediate && isInt<26>(getImm()) &&
379 (getImm() & 3) == 0); }
380 bool isCondBr() const { return Kind == Expression ||
381 (Kind == Immediate && isInt<16>(getImm()) &&
382 (getImm() & 3) == 0); }
383 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
384 bool isCCRegNumber() const { return (Kind == Expression
385 && isUInt<3>(getExprCRVal())) ||
387 && isUInt<3>(getImm())); }
388 bool isCRBitNumber() const { return (Kind == Expression
389 && isUInt<5>(getExprCRVal())) ||
391 && isUInt<5>(getImm())); }
392 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
393 isPowerOf2_32(getImm()); }
394 bool isMem() const { return false; }
395 bool isReg() const { return false; }
397 void addRegOperands(MCInst &Inst, unsigned N) const {
398 llvm_unreachable("addRegOperands");
401 void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
402 assert(N == 1 && "Invalid number of operands!");
403 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
406 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
407 assert(N == 1 && "Invalid number of operands!");
408 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
411 void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
412 assert(N == 1 && "Invalid number of operands!");
413 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
416 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
417 assert(N == 1 && "Invalid number of operands!");
418 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
421 void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
423 addRegG8RCOperands(Inst, N);
425 addRegGPRCOperands(Inst, N);
428 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
430 addRegG8RCNoX0Operands(Inst, N);
432 addRegGPRCNoR0Operands(Inst, N);
435 void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
436 assert(N == 1 && "Invalid number of operands!");
437 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
440 void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
441 assert(N == 1 && "Invalid number of operands!");
442 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
445 void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
446 assert(N == 1 && "Invalid number of operands!");
447 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
450 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
451 assert(N == 1 && "Invalid number of operands!");
452 Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
455 void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
456 assert(N == 1 && "Invalid number of operands!");
457 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
460 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
461 assert(N == 1 && "Invalid number of operands!");
462 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
465 void addImmOperands(MCInst &Inst, unsigned N) const {
466 assert(N == 1 && "Invalid number of operands!");
467 if (Kind == Immediate)
468 Inst.addOperand(MCOperand::CreateImm(getImm()));
470 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
473 void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
474 assert(N == 1 && "Invalid number of operands!");
475 if (Kind == Immediate)
476 Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
478 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
481 void addTLSRegOperands(MCInst &Inst, unsigned N) const {
482 assert(N == 1 && "Invalid number of operands!");
483 Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
486 StringRef getToken() const {
487 assert(Kind == Token && "Invalid access!");
488 return StringRef(Tok.Data, Tok.Length);
491 virtual void print(raw_ostream &OS) const;
493 static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) {
494 PPCOperand *Op = new PPCOperand(Token);
495 Op->Tok.Data = Str.data();
496 Op->Tok.Length = Str.size();
499 Op->IsPPC64 = IsPPC64;
503 static PPCOperand *CreateTokenWithStringCopy(StringRef Str, SMLoc S,
505 // Allocate extra memory for the string and copy it.
506 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
507 PPCOperand *Op = new (Mem) PPCOperand(Token);
508 Op->Tok.Data = (const char *)(Op + 1);
509 Op->Tok.Length = Str.size();
510 std::memcpy((char *)(Op + 1), Str.data(), Str.size());
513 Op->IsPPC64 = IsPPC64;
517 static PPCOperand *CreateImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
518 PPCOperand *Op = new PPCOperand(Immediate);
522 Op->IsPPC64 = IsPPC64;
526 static PPCOperand *CreateExpr(const MCExpr *Val,
527 SMLoc S, SMLoc E, bool IsPPC64) {
528 PPCOperand *Op = new PPCOperand(Expression);
530 Op->Expr.CRVal = EvaluateCRExpr(Val);
533 Op->IsPPC64 = IsPPC64;
537 static PPCOperand *CreateTLSReg(const MCSymbolRefExpr *Sym,
538 SMLoc S, SMLoc E, bool IsPPC64) {
539 PPCOperand *Op = new PPCOperand(TLSRegister);
540 Op->TLSReg.Sym = Sym;
543 Op->IsPPC64 = IsPPC64;
547 static PPCOperand *CreateFromMCExpr(const MCExpr *Val,
548 SMLoc S, SMLoc E, bool IsPPC64) {
549 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
550 return CreateImm(CE->getValue(), S, E, IsPPC64);
552 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
553 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
554 return CreateTLSReg(SRE, S, E, IsPPC64);
556 return CreateExpr(Val, S, E, IsPPC64);
560 } // end anonymous namespace.
562 void PPCOperand::print(raw_ostream &OS) const {
565 OS << "'" << getToken() << "'";
571 getExpr()->print(OS);
574 getTLSReg()->print(OS);
581 ProcessInstruction(MCInst &Inst,
582 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
583 int Opcode = Inst.getOpcode();
587 TmpInst.setOpcode(PPC::LA);
588 TmpInst.addOperand(Inst.getOperand(0));
589 TmpInst.addOperand(Inst.getOperand(2));
590 TmpInst.addOperand(Inst.getOperand(1));
596 int64_t N = Inst.getOperand(2).getImm();
597 TmpInst.setOpcode(PPC::ADDI);
598 TmpInst.addOperand(Inst.getOperand(0));
599 TmpInst.addOperand(Inst.getOperand(1));
600 TmpInst.addOperand(MCOperand::CreateImm(-N));
606 int64_t N = Inst.getOperand(2).getImm();
607 TmpInst.setOpcode(PPC::ADDIS);
608 TmpInst.addOperand(Inst.getOperand(0));
609 TmpInst.addOperand(Inst.getOperand(1));
610 TmpInst.addOperand(MCOperand::CreateImm(-N));
616 int64_t N = Inst.getOperand(2).getImm();
617 TmpInst.setOpcode(PPC::ADDIC);
618 TmpInst.addOperand(Inst.getOperand(0));
619 TmpInst.addOperand(Inst.getOperand(1));
620 TmpInst.addOperand(MCOperand::CreateImm(-N));
626 int64_t N = Inst.getOperand(2).getImm();
627 TmpInst.setOpcode(PPC::ADDICo);
628 TmpInst.addOperand(Inst.getOperand(0));
629 TmpInst.addOperand(Inst.getOperand(1));
630 TmpInst.addOperand(MCOperand::CreateImm(-N));
637 int64_t N = Inst.getOperand(2).getImm();
638 int64_t B = Inst.getOperand(3).getImm();
639 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
640 TmpInst.addOperand(Inst.getOperand(0));
641 TmpInst.addOperand(Inst.getOperand(1));
642 TmpInst.addOperand(MCOperand::CreateImm(B));
643 TmpInst.addOperand(MCOperand::CreateImm(0));
644 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
651 int64_t N = Inst.getOperand(2).getImm();
652 int64_t B = Inst.getOperand(3).getImm();
653 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
654 TmpInst.addOperand(Inst.getOperand(0));
655 TmpInst.addOperand(Inst.getOperand(1));
656 TmpInst.addOperand(MCOperand::CreateImm(B + N));
657 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
658 TmpInst.addOperand(MCOperand::CreateImm(31));
665 int64_t N = Inst.getOperand(2).getImm();
666 int64_t B = Inst.getOperand(3).getImm();
667 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
668 TmpInst.addOperand(Inst.getOperand(0));
669 TmpInst.addOperand(Inst.getOperand(0));
670 TmpInst.addOperand(Inst.getOperand(1));
671 TmpInst.addOperand(MCOperand::CreateImm(32 - B));
672 TmpInst.addOperand(MCOperand::CreateImm(B));
673 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
680 int64_t N = Inst.getOperand(2).getImm();
681 int64_t B = Inst.getOperand(3).getImm();
682 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
683 TmpInst.addOperand(Inst.getOperand(0));
684 TmpInst.addOperand(Inst.getOperand(0));
685 TmpInst.addOperand(Inst.getOperand(1));
686 TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
687 TmpInst.addOperand(MCOperand::CreateImm(B));
688 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
695 int64_t N = Inst.getOperand(2).getImm();
696 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
697 TmpInst.addOperand(Inst.getOperand(0));
698 TmpInst.addOperand(Inst.getOperand(1));
699 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
700 TmpInst.addOperand(MCOperand::CreateImm(0));
701 TmpInst.addOperand(MCOperand::CreateImm(31));
708 int64_t N = Inst.getOperand(2).getImm();
709 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
710 TmpInst.addOperand(Inst.getOperand(0));
711 TmpInst.addOperand(Inst.getOperand(1));
712 TmpInst.addOperand(MCOperand::CreateImm(N));
713 TmpInst.addOperand(MCOperand::CreateImm(0));
714 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
721 int64_t N = Inst.getOperand(2).getImm();
722 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
723 TmpInst.addOperand(Inst.getOperand(0));
724 TmpInst.addOperand(Inst.getOperand(1));
725 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
726 TmpInst.addOperand(MCOperand::CreateImm(N));
727 TmpInst.addOperand(MCOperand::CreateImm(31));
734 int64_t N = Inst.getOperand(2).getImm();
735 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
736 TmpInst.addOperand(Inst.getOperand(0));
737 TmpInst.addOperand(Inst.getOperand(1));
738 TmpInst.addOperand(MCOperand::CreateImm(0));
739 TmpInst.addOperand(MCOperand::CreateImm(0));
740 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
745 case PPC::CLRLSLWIo: {
747 int64_t B = Inst.getOperand(2).getImm();
748 int64_t N = Inst.getOperand(3).getImm();
749 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
750 TmpInst.addOperand(Inst.getOperand(0));
751 TmpInst.addOperand(Inst.getOperand(1));
752 TmpInst.addOperand(MCOperand::CreateImm(N));
753 TmpInst.addOperand(MCOperand::CreateImm(B - N));
754 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
761 int64_t N = Inst.getOperand(2).getImm();
762 int64_t B = Inst.getOperand(3).getImm();
763 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
764 TmpInst.addOperand(Inst.getOperand(0));
765 TmpInst.addOperand(Inst.getOperand(1));
766 TmpInst.addOperand(MCOperand::CreateImm(B));
767 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
774 int64_t N = Inst.getOperand(2).getImm();
775 int64_t B = Inst.getOperand(3).getImm();
776 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
777 TmpInst.addOperand(Inst.getOperand(0));
778 TmpInst.addOperand(Inst.getOperand(1));
779 TmpInst.addOperand(MCOperand::CreateImm(B + N));
780 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
787 int64_t N = Inst.getOperand(2).getImm();
788 int64_t B = Inst.getOperand(3).getImm();
789 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
790 TmpInst.addOperand(Inst.getOperand(0));
791 TmpInst.addOperand(Inst.getOperand(0));
792 TmpInst.addOperand(Inst.getOperand(1));
793 TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
794 TmpInst.addOperand(MCOperand::CreateImm(B));
801 int64_t N = Inst.getOperand(2).getImm();
802 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
803 TmpInst.addOperand(Inst.getOperand(0));
804 TmpInst.addOperand(Inst.getOperand(1));
805 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
806 TmpInst.addOperand(MCOperand::CreateImm(0));
813 int64_t N = Inst.getOperand(2).getImm();
814 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
815 TmpInst.addOperand(Inst.getOperand(0));
816 TmpInst.addOperand(Inst.getOperand(1));
817 TmpInst.addOperand(MCOperand::CreateImm(N));
818 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
825 int64_t N = Inst.getOperand(2).getImm();
826 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
827 TmpInst.addOperand(Inst.getOperand(0));
828 TmpInst.addOperand(Inst.getOperand(1));
829 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
830 TmpInst.addOperand(MCOperand::CreateImm(N));
837 int64_t N = Inst.getOperand(2).getImm();
838 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
839 TmpInst.addOperand(Inst.getOperand(0));
840 TmpInst.addOperand(Inst.getOperand(1));
841 TmpInst.addOperand(MCOperand::CreateImm(0));
842 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
847 case PPC::CLRLSLDIo: {
849 int64_t B = Inst.getOperand(2).getImm();
850 int64_t N = Inst.getOperand(3).getImm();
851 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
852 TmpInst.addOperand(Inst.getOperand(0));
853 TmpInst.addOperand(Inst.getOperand(1));
854 TmpInst.addOperand(MCOperand::CreateImm(N));
855 TmpInst.addOperand(MCOperand::CreateImm(B - N));
863 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
864 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
865 MCStreamer &Out, unsigned &ErrorInfo,
866 bool MatchingInlineAsm) {
869 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
872 // Post-process instructions (typically extended mnemonics)
873 ProcessInstruction(Inst, Operands);
875 Out.EmitInstruction(Inst);
877 case Match_MissingFeature:
878 return Error(IDLoc, "instruction use requires an option to be enabled");
879 case Match_MnemonicFail:
880 return Error(IDLoc, "unrecognized instruction mnemonic");
881 case Match_InvalidOperand: {
882 SMLoc ErrorLoc = IDLoc;
883 if (ErrorInfo != ~0U) {
884 if (ErrorInfo >= Operands.size())
885 return Error(IDLoc, "too few operands for instruction");
887 ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc();
888 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
891 return Error(ErrorLoc, "invalid operand for instruction");
895 llvm_unreachable("Implement any new match types added!");
899 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
900 if (Tok.is(AsmToken::Identifier)) {
901 StringRef Name = Tok.getString();
903 if (Name.equals_lower("lr")) {
904 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
907 } else if (Name.equals_lower("ctr")) {
908 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
911 } else if (Name.equals_lower("vrsave")) {
915 } else if (Name.startswith_lower("r") &&
916 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
917 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
919 } else if (Name.startswith_lower("f") &&
920 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
921 RegNo = FRegs[IntVal];
923 } else if (Name.startswith_lower("v") &&
924 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
925 RegNo = VRegs[IntVal];
927 } else if (Name.startswith_lower("cr") &&
928 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
929 RegNo = CRRegs[IntVal];
938 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
939 const AsmToken &Tok = Parser.getTok();
940 StartLoc = Tok.getLoc();
941 EndLoc = Tok.getEndLoc();
945 if (!MatchRegisterName(Tok, RegNo, IntVal)) {
946 Parser.Lex(); // Eat identifier token.
950 return Error(StartLoc, "invalid register name");
953 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
954 /// the expression and check for VK_PPC_LO/HI/HA
955 /// symbol variants. If all symbols with modifier use the same
956 /// variant, return the corresponding PPCMCExpr::VariantKind,
957 /// and a modified expression using the default symbol variant.
958 /// Otherwise, return NULL.
959 const MCExpr *PPCAsmParser::
960 ExtractModifierFromExpr(const MCExpr *E,
961 PPCMCExpr::VariantKind &Variant) {
962 MCContext &Context = getParser().getContext();
963 Variant = PPCMCExpr::VK_PPC_None;
965 switch (E->getKind()) {
967 case MCExpr::Constant:
970 case MCExpr::SymbolRef: {
971 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
973 switch (SRE->getKind()) {
974 case MCSymbolRefExpr::VK_PPC_LO:
975 Variant = PPCMCExpr::VK_PPC_LO;
977 case MCSymbolRefExpr::VK_PPC_HI:
978 Variant = PPCMCExpr::VK_PPC_HI;
980 case MCSymbolRefExpr::VK_PPC_HA:
981 Variant = PPCMCExpr::VK_PPC_HA;
983 case MCSymbolRefExpr::VK_PPC_HIGHER:
984 Variant = PPCMCExpr::VK_PPC_HIGHER;
986 case MCSymbolRefExpr::VK_PPC_HIGHERA:
987 Variant = PPCMCExpr::VK_PPC_HIGHERA;
989 case MCSymbolRefExpr::VK_PPC_HIGHEST:
990 Variant = PPCMCExpr::VK_PPC_HIGHEST;
992 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
993 Variant = PPCMCExpr::VK_PPC_HIGHESTA;
999 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
1002 case MCExpr::Unary: {
1003 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1004 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1007 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1010 case MCExpr::Binary: {
1011 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1012 PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1013 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1014 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1019 if (!LHS) LHS = BE->getLHS();
1020 if (!RHS) RHS = BE->getRHS();
1022 if (LHSVariant == PPCMCExpr::VK_PPC_None)
1023 Variant = RHSVariant;
1024 else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1025 Variant = LHSVariant;
1026 else if (LHSVariant == RHSVariant)
1027 Variant = LHSVariant;
1031 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1035 llvm_unreachable("Invalid expression kind!");
1038 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1039 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having
1040 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1041 /// FIXME: This is a hack.
1042 const MCExpr *PPCAsmParser::
1043 FixupVariantKind(const MCExpr *E) {
1044 MCContext &Context = getParser().getContext();
1046 switch (E->getKind()) {
1047 case MCExpr::Target:
1048 case MCExpr::Constant:
1051 case MCExpr::SymbolRef: {
1052 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1053 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1055 switch (SRE->getKind()) {
1056 case MCSymbolRefExpr::VK_TLSGD:
1057 Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1059 case MCSymbolRefExpr::VK_TLSLD:
1060 Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1065 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context);
1068 case MCExpr::Unary: {
1069 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1070 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1071 if (Sub == UE->getSubExpr())
1073 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1076 case MCExpr::Binary: {
1077 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1078 const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1079 const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1080 if (LHS == BE->getLHS() && RHS == BE->getRHS())
1082 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1086 llvm_unreachable("Invalid expression kind!");
1089 /// ParseExpression. This differs from the default "parseExpression" in that
1090 /// it handles modifiers.
1092 ParseExpression(const MCExpr *&EVal) {
1095 return ParseDarwinExpression(EVal);
1098 // Handle \code @l/@ha \endcode
1099 if (getParser().parseExpression(EVal))
1102 EVal = FixupVariantKind(EVal);
1104 PPCMCExpr::VariantKind Variant;
1105 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1107 EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
1112 /// ParseDarwinExpression. (MachO Platforms)
1113 /// This differs from the default "parseExpression" in that it handles detection
1114 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present,
1115 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1116 /// syntax form so it is done here. TODO: Determine if there is merit in arranging
1117 /// for this to be done at a higher level.
1119 ParseDarwinExpression(const MCExpr *&EVal) {
1120 PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1121 switch (getLexer().getKind()) {
1124 case AsmToken::Identifier:
1125 // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1126 // something starting with any other char should be part of the
1127 // asm syntax. If handwritten asm includes an identifier like lo16,
1128 // then all bets are off - but no-one would do that, right?
1129 StringRef poss = Parser.getTok().getString();
1130 if (poss.equals_lower("lo16")) {
1131 Variant = PPCMCExpr::VK_PPC_LO;
1132 } else if (poss.equals_lower("hi16")) {
1133 Variant = PPCMCExpr::VK_PPC_HI;
1134 } else if (poss.equals_lower("ha16")) {
1135 Variant = PPCMCExpr::VK_PPC_HA;
1137 if (Variant != PPCMCExpr::VK_PPC_None) {
1138 Parser.Lex(); // Eat the xx16
1139 if (getLexer().isNot(AsmToken::LParen))
1140 return Error(Parser.getTok().getLoc(), "expected '('");
1141 Parser.Lex(); // Eat the '('
1146 if (getParser().parseExpression(EVal))
1149 if (Variant != PPCMCExpr::VK_PPC_None) {
1150 if (getLexer().isNot(AsmToken::RParen))
1151 return Error(Parser.getTok().getLoc(), "expected ')'");
1152 Parser.Lex(); // Eat the ')'
1153 EVal = PPCMCExpr::Create(Variant, EVal, false, getParser().getContext());
1159 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1162 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1163 SMLoc S = Parser.getTok().getLoc();
1164 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1168 // Attempt to parse the next token as an immediate
1169 switch (getLexer().getKind()) {
1170 // Special handling for register names. These are interpreted
1171 // as immediates corresponding to the register number.
1172 case AsmToken::Percent:
1173 Parser.Lex(); // Eat the '%'.
1176 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1177 Parser.Lex(); // Eat the identifier token.
1178 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1179 Operands.push_back(Op);
1182 return Error(S, "invalid register name");
1184 case AsmToken::Identifier:
1185 // Note that non-register-name identifiers from the compiler will begin
1186 // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include
1187 // identifiers like r31foo - so we fall through in the event that parsing
1188 // a register name fails.
1192 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1193 Parser.Lex(); // Eat the identifier token.
1194 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1195 Operands.push_back(Op);
1199 // Fall-through to process non-register-name identifiers as expression.
1200 // All other expressions
1201 case AsmToken::LParen:
1202 case AsmToken::Plus:
1203 case AsmToken::Minus:
1204 case AsmToken::Integer:
1206 case AsmToken::Dollar:
1207 if (!ParseExpression(EVal))
1211 return Error(S, "unknown operand");
1214 // Push the parsed operand into the list of operands
1215 Op = PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64());
1216 Operands.push_back(Op);
1218 // Check whether this is a TLS call expression
1219 bool TLSCall = false;
1220 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1221 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1223 if (TLSCall && getLexer().is(AsmToken::LParen)) {
1224 const MCExpr *TLSSym;
1226 Parser.Lex(); // Eat the '('.
1227 S = Parser.getTok().getLoc();
1228 if (ParseExpression(TLSSym))
1229 return Error(S, "invalid TLS call expression");
1230 if (getLexer().isNot(AsmToken::RParen))
1231 return Error(Parser.getTok().getLoc(), "missing ')'");
1232 E = Parser.getTok().getLoc();
1233 Parser.Lex(); // Eat the ')'.
1235 Op = PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64());
1236 Operands.push_back(Op);
1239 // Otherwise, check for D-form memory operands
1240 if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1241 Parser.Lex(); // Eat the '('.
1242 S = Parser.getTok().getLoc();
1245 switch (getLexer().getKind()) {
1246 case AsmToken::Percent:
1247 Parser.Lex(); // Eat the '%'.
1249 if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1250 return Error(S, "invalid register name");
1251 Parser.Lex(); // Eat the identifier token.
1254 case AsmToken::Integer:
1256 if (getParser().parseAbsoluteExpression(IntVal) ||
1257 IntVal < 0 || IntVal > 31)
1258 return Error(S, "invalid register number");
1260 return Error(S, "unexpected integer value");
1264 case AsmToken::Identifier:
1267 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1268 Parser.Lex(); // Eat the identifier token.
1275 return Error(S, "invalid memory operand");
1278 if (getLexer().isNot(AsmToken::RParen))
1279 return Error(Parser.getTok().getLoc(), "missing ')'");
1280 E = Parser.getTok().getLoc();
1281 Parser.Lex(); // Eat the ')'.
1283 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1284 Operands.push_back(Op);
1290 /// Parse an instruction mnemonic followed by its operands.
1292 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1293 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1294 // The first operand is the token for the instruction name.
1295 // If the next character is a '+' or '-', we need to add it to the
1296 // instruction name, to match what TableGen is doing.
1297 std::string NewOpcode;
1298 if (getLexer().is(AsmToken::Plus)) {
1304 if (getLexer().is(AsmToken::Minus)) {
1310 // If the instruction ends in a '.', we need to create a separate
1311 // token for it, to match what TableGen is doing.
1312 size_t Dot = Name.find('.');
1313 StringRef Mnemonic = Name.slice(0, Dot);
1314 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1316 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1318 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1319 if (Dot != StringRef::npos) {
1320 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1321 StringRef DotStr = Name.slice(Dot, StringRef::npos);
1322 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1324 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1326 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1329 // If there are no more operands then finish
1330 if (getLexer().is(AsmToken::EndOfStatement))
1333 // Parse the first operand
1334 if (ParseOperand(Operands))
1337 while (getLexer().isNot(AsmToken::EndOfStatement) &&
1338 getLexer().is(AsmToken::Comma)) {
1339 // Consume the comma token
1342 // Parse the next operand
1343 if (ParseOperand(Operands))
1350 /// ParseDirective parses the PPC specific directives
1351 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1352 StringRef IDVal = DirectiveID.getIdentifier();
1354 if (IDVal == ".word")
1355 return ParseDirectiveWord(2, DirectiveID.getLoc());
1356 if (IDVal == ".llong")
1357 return ParseDirectiveWord(8, DirectiveID.getLoc());
1359 return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1360 if (IDVal == ".machine")
1361 return ParseDirectiveMachine(DirectiveID.getLoc());
1363 if (IDVal == ".machine")
1364 return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1369 /// ParseDirectiveWord
1370 /// ::= .word [ expression (, expression)* ]
1371 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1372 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1374 const MCExpr *Value;
1375 if (getParser().parseExpression(Value))
1378 getParser().getStreamer().EmitValue(Value, Size);
1380 if (getLexer().is(AsmToken::EndOfStatement))
1383 if (getLexer().isNot(AsmToken::Comma))
1384 return Error(L, "unexpected token in directive");
1393 /// ParseDirectiveTC
1394 /// ::= .tc [ symbol (, expression)* ]
1395 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1396 // Skip TC symbol, which is only used with XCOFF.
1397 while (getLexer().isNot(AsmToken::EndOfStatement)
1398 && getLexer().isNot(AsmToken::Comma))
1400 if (getLexer().isNot(AsmToken::Comma))
1401 return Error(L, "unexpected token in directive");
1404 // Align to word size.
1405 getParser().getStreamer().EmitValueToAlignment(Size);
1407 // Emit expressions.
1408 return ParseDirectiveWord(Size, L);
1411 /// ParseDirectiveMachine (ELF platforms)
1412 /// ::= .machine [ cpu | "push" | "pop" ]
1413 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1414 if (getLexer().isNot(AsmToken::Identifier) &&
1415 getLexer().isNot(AsmToken::String))
1416 return Error(L, "unexpected token in directive");
1418 StringRef CPU = Parser.getTok().getIdentifier();
1421 // FIXME: Right now, the parser always allows any available
1422 // instruction, so the .machine directive is not useful.
1423 // Implement ".machine any" (by doing nothing) for the benefit
1424 // of existing assembler code. Likewise, we can then implement
1425 // ".machine push" and ".machine pop" as no-op.
1426 if (CPU != "any" && CPU != "push" && CPU != "pop")
1427 return Error(L, "unrecognized machine type");
1429 if (getLexer().isNot(AsmToken::EndOfStatement))
1430 return Error(L, "unexpected token in directive");
1435 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1436 /// ::= .machine cpu-identifier
1437 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1438 if (getLexer().isNot(AsmToken::Identifier) &&
1439 getLexer().isNot(AsmToken::String))
1440 return Error(L, "unexpected token in directive");
1442 StringRef CPU = Parser.getTok().getIdentifier();
1445 // FIXME: this is only the 'default' set of cpu variants.
1446 // However we don't act on this information at present, this is simply
1447 // allowing parsing to proceed with minimal sanity checking.
1448 if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64")
1449 return Error(L, "unrecognized cpu type");
1451 if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc"))
1452 return Error(L, "wrong cpu type specified for 64bit");
1453 if (!isPPC64() && CPU == "ppc64")
1454 return Error(L, "wrong cpu type specified for 32bit");
1456 if (getLexer().isNot(AsmToken::EndOfStatement))
1457 return Error(L, "unexpected token in directive");
1462 /// Force static initialization.
1463 extern "C" void LLVMInitializePowerPCAsmParser() {
1464 RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1465 RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1466 RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1469 #define GET_REGISTER_MATCHER
1470 #define GET_MATCHER_IMPLEMENTATION
1471 #include "PPCGenAsmMatcher.inc"
1473 // Define this matcher function after the auto-generated include so we
1474 // have the match class enum definitions.
1475 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
1477 // If the kind is a token for a literal immediate, check if our asm
1478 // operand matches. This is for InstAliases which have a fixed-value
1479 // immediate in the syntax.
1482 case MCK_0: ImmVal = 0; break;
1483 case MCK_1: ImmVal = 1; break;
1484 case MCK_2: ImmVal = 2; break;
1485 case MCK_3: ImmVal = 3; break;
1486 default: return Match_InvalidOperand;
1489 PPCOperand *Op = static_cast<PPCOperand*>(AsmOp);
1490 if (Op->isImm() && Op->getImm() == ImmVal)
1491 return Match_Success;
1493 return Match_InvalidOperand;
1497 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1498 MCSymbolRefExpr::VariantKind Variant,
1501 case MCSymbolRefExpr::VK_PPC_LO:
1502 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1503 case MCSymbolRefExpr::VK_PPC_HI:
1504 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1505 case MCSymbolRefExpr::VK_PPC_HA:
1506 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1507 case MCSymbolRefExpr::VK_PPC_HIGHER:
1508 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1509 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1510 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1511 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1512 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1513 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1514 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);