1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "llvm/MC/MCTargetAsmParser.h"
13 #include "llvm/MC/MCStreamer.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCRegisterInfo.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
18 #include "llvm/MC/MCParser/MCAsmLexer.h"
19 #include "llvm/MC/MCParser/MCAsmParser.h"
20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/SmallString.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/StringSwitch.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
34 static unsigned RRegs[32] = {
35 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
36 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
37 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
38 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
39 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
40 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
41 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
42 PPC::R28, PPC::R29, PPC::R30, PPC::R31
44 static unsigned RRegsNoR0[32] = {
46 PPC::R1, PPC::R2, PPC::R3,
47 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
48 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
49 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
50 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
51 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
52 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
53 PPC::R28, PPC::R29, PPC::R30, PPC::R31
55 static unsigned XRegs[32] = {
56 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
57 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
58 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
59 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
60 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
61 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
62 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
63 PPC::X28, PPC::X29, PPC::X30, PPC::X31
65 static unsigned XRegsNoX0[32] = {
67 PPC::X1, PPC::X2, PPC::X3,
68 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
69 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
70 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
71 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
72 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
73 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
74 PPC::X28, PPC::X29, PPC::X30, PPC::X31
76 static unsigned FRegs[32] = {
77 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
78 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
79 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
80 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
81 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
82 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
83 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
84 PPC::F28, PPC::F29, PPC::F30, PPC::F31
86 static unsigned VRegs[32] = {
87 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
88 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
89 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
90 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
91 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
92 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
93 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
94 PPC::V28, PPC::V29, PPC::V30, PPC::V31
96 static unsigned CRBITRegs[32] = {
97 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
98 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
99 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
100 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
101 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
102 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
103 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
104 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
106 static unsigned CRRegs[8] = {
107 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
108 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
111 // Evaluate an expression containing condition register
112 // or condition register field symbols. Returns positive
113 // value on success, or -1 on error.
115 EvaluateCRExpr(const MCExpr *E) {
116 switch (E->getKind()) {
120 case MCExpr::Constant: {
121 int64_t Res = cast<MCConstantExpr>(E)->getValue();
122 return Res < 0 ? -1 : Res;
125 case MCExpr::SymbolRef: {
126 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
127 StringRef Name = SRE->getSymbol().getName();
129 if (Name == "lt") return 0;
130 if (Name == "gt") return 1;
131 if (Name == "eq") return 2;
132 if (Name == "so") return 3;
133 if (Name == "un") return 3;
135 if (Name == "cr0") return 0;
136 if (Name == "cr1") return 1;
137 if (Name == "cr2") return 2;
138 if (Name == "cr3") return 3;
139 if (Name == "cr4") return 4;
140 if (Name == "cr5") return 5;
141 if (Name == "cr6") return 6;
142 if (Name == "cr7") return 7;
150 case MCExpr::Binary: {
151 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
152 int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
153 int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
156 if (LHSVal < 0 || RHSVal < 0)
159 switch (BE->getOpcode()) {
161 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
162 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
165 return Res < 0 ? -1 : Res;
169 llvm_unreachable("Invalid expression kind!");
174 class PPCAsmParser : public MCTargetAsmParser {
175 MCSubtargetInfo &STI;
179 MCAsmParser &getParser() const { return Parser; }
180 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
182 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
183 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
185 bool isPPC64() const { return IsPPC64; }
187 bool MatchRegisterName(const AsmToken &Tok,
188 unsigned &RegNo, int64_t &IntVal);
190 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
192 const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
193 PPCMCExpr::VariantKind &Variant);
194 const MCExpr *FixupVariantKind(const MCExpr *E);
195 bool ParseExpression(const MCExpr *&EVal);
197 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
199 bool ParseDirectiveWord(unsigned Size, SMLoc L);
200 bool ParseDirectiveTC(unsigned Size, SMLoc L);
201 bool ParseDirectiveMachine(SMLoc L);
203 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
204 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
205 MCStreamer &Out, unsigned &ErrorInfo,
206 bool MatchingInlineAsm);
208 void ProcessInstruction(MCInst &Inst,
209 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
211 /// @name Auto-generated Match Functions
214 #define GET_ASSEMBLER_HEADER
215 #include "PPCGenAsmMatcher.inc"
221 PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
222 const MCInstrInfo &MII)
223 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
224 // Check for 64-bit vs. 32-bit pointer mode.
225 Triple TheTriple(STI.getTargetTriple());
226 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
227 TheTriple.getArch() == Triple::ppc64le);
228 // Initialize the set of available features.
229 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
232 virtual bool ParseInstruction(ParseInstructionInfo &Info,
233 StringRef Name, SMLoc NameLoc,
234 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
236 virtual bool ParseDirective(AsmToken DirectiveID);
238 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
240 virtual const MCExpr *applyModifierToExpr(const MCExpr *E,
241 MCSymbolRefExpr::VariantKind,
245 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
247 struct PPCOperand : public MCParsedAsmOperand {
255 SMLoc StartLoc, EndLoc;
269 int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
273 const MCSymbolRefExpr *Sym;
280 struct TLSRegOp TLSReg;
283 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
285 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
287 StartLoc = o.StartLoc;
306 /// getStartLoc - Get the location of the first token of this operand.
307 SMLoc getStartLoc() const { return StartLoc; }
309 /// getEndLoc - Get the location of the last token of this operand.
310 SMLoc getEndLoc() const { return EndLoc; }
312 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
313 bool isPPC64() const { return IsPPC64; }
315 int64_t getImm() const {
316 assert(Kind == Immediate && "Invalid access!");
320 const MCExpr *getExpr() const {
321 assert(Kind == Expression && "Invalid access!");
325 int64_t getExprCRVal() const {
326 assert(Kind == Expression && "Invalid access!");
330 const MCExpr *getTLSReg() const {
331 assert(Kind == TLSRegister && "Invalid access!");
335 unsigned getReg() const {
336 assert(isRegNumber() && "Invalid access!");
337 return (unsigned) Imm.Val;
340 unsigned getCCReg() const {
341 assert(isCCRegNumber() && "Invalid access!");
342 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
345 unsigned getCRBit() const {
346 assert(isCRBitNumber() && "Invalid access!");
347 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
350 unsigned getCRBitMask() const {
351 assert(isCRBitMask() && "Invalid access!");
352 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
355 bool isToken() const { return Kind == Token; }
356 bool isImm() const { return Kind == Immediate || Kind == Expression; }
357 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
358 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
359 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
360 bool isU16Imm() const { return Kind == Expression ||
361 (Kind == Immediate && isUInt<16>(getImm())); }
362 bool isS16Imm() const { return Kind == Expression ||
363 (Kind == Immediate && isInt<16>(getImm())); }
364 bool isS16ImmX4() const { return Kind == Expression ||
365 (Kind == Immediate && isInt<16>(getImm()) &&
366 (getImm() & 3) == 0); }
367 bool isS17Imm() const { return Kind == Expression ||
368 (Kind == Immediate && isInt<17>(getImm())); }
369 bool isTLSReg() const { return Kind == TLSRegister; }
370 bool isDirectBr() const { return Kind == Expression ||
371 (Kind == Immediate && isInt<26>(getImm()) &&
372 (getImm() & 3) == 0); }
373 bool isCondBr() const { return Kind == Expression ||
374 (Kind == Immediate && isInt<16>(getImm()) &&
375 (getImm() & 3) == 0); }
376 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
377 bool isCCRegNumber() const { return (Kind == Expression
378 && isUInt<3>(getExprCRVal())) ||
380 && isUInt<3>(getImm())); }
381 bool isCRBitNumber() const { return (Kind == Expression
382 && isUInt<5>(getExprCRVal())) ||
384 && isUInt<5>(getImm())); }
385 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
386 isPowerOf2_32(getImm()); }
387 bool isMem() const { return false; }
388 bool isReg() const { return false; }
390 void addRegOperands(MCInst &Inst, unsigned N) const {
391 llvm_unreachable("addRegOperands");
394 void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
395 assert(N == 1 && "Invalid number of operands!");
396 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
399 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
400 assert(N == 1 && "Invalid number of operands!");
401 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
404 void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
405 assert(N == 1 && "Invalid number of operands!");
406 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
409 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
410 assert(N == 1 && "Invalid number of operands!");
411 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
414 void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
416 addRegG8RCOperands(Inst, N);
418 addRegGPRCOperands(Inst, N);
421 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
423 addRegG8RCNoX0Operands(Inst, N);
425 addRegGPRCNoR0Operands(Inst, N);
428 void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
429 assert(N == 1 && "Invalid number of operands!");
430 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
433 void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
434 assert(N == 1 && "Invalid number of operands!");
435 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
438 void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
439 assert(N == 1 && "Invalid number of operands!");
440 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
443 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
444 assert(N == 1 && "Invalid number of operands!");
445 Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
448 void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
449 assert(N == 1 && "Invalid number of operands!");
450 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
453 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
454 assert(N == 1 && "Invalid number of operands!");
455 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
458 void addImmOperands(MCInst &Inst, unsigned N) const {
459 assert(N == 1 && "Invalid number of operands!");
460 if (Kind == Immediate)
461 Inst.addOperand(MCOperand::CreateImm(getImm()));
463 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
466 void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
467 assert(N == 1 && "Invalid number of operands!");
468 if (Kind == Immediate)
469 Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
471 Inst.addOperand(MCOperand::CreateExpr(getExpr()));
474 void addTLSRegOperands(MCInst &Inst, unsigned N) const {
475 assert(N == 1 && "Invalid number of operands!");
476 Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
479 StringRef getToken() const {
480 assert(Kind == Token && "Invalid access!");
481 return StringRef(Tok.Data, Tok.Length);
484 virtual void print(raw_ostream &OS) const;
486 static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) {
487 PPCOperand *Op = new PPCOperand(Token);
488 Op->Tok.Data = Str.data();
489 Op->Tok.Length = Str.size();
492 Op->IsPPC64 = IsPPC64;
496 static PPCOperand *CreateTokenWithStringCopy(StringRef Str, SMLoc S,
498 // Allocate extra memory for the string and copy it.
499 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
500 PPCOperand *Op = new (Mem) PPCOperand(Token);
501 Op->Tok.Data = (const char *)(Op + 1);
502 Op->Tok.Length = Str.size();
503 std::memcpy((char *)(Op + 1), Str.data(), Str.size());
506 Op->IsPPC64 = IsPPC64;
510 static PPCOperand *CreateImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
511 PPCOperand *Op = new PPCOperand(Immediate);
515 Op->IsPPC64 = IsPPC64;
519 static PPCOperand *CreateExpr(const MCExpr *Val,
520 SMLoc S, SMLoc E, bool IsPPC64) {
521 PPCOperand *Op = new PPCOperand(Expression);
523 Op->Expr.CRVal = EvaluateCRExpr(Val);
526 Op->IsPPC64 = IsPPC64;
530 static PPCOperand *CreateTLSReg(const MCSymbolRefExpr *Sym,
531 SMLoc S, SMLoc E, bool IsPPC64) {
532 PPCOperand *Op = new PPCOperand(TLSRegister);
533 Op->TLSReg.Sym = Sym;
536 Op->IsPPC64 = IsPPC64;
540 static PPCOperand *CreateFromMCExpr(const MCExpr *Val,
541 SMLoc S, SMLoc E, bool IsPPC64) {
542 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
543 return CreateImm(CE->getValue(), S, E, IsPPC64);
545 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
546 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
547 return CreateTLSReg(SRE, S, E, IsPPC64);
549 return CreateExpr(Val, S, E, IsPPC64);
553 } // end anonymous namespace.
555 void PPCOperand::print(raw_ostream &OS) const {
558 OS << "'" << getToken() << "'";
564 getExpr()->print(OS);
567 getTLSReg()->print(OS);
574 ProcessInstruction(MCInst &Inst,
575 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
576 int Opcode = Inst.getOpcode();
580 TmpInst.setOpcode(PPC::LA);
581 TmpInst.addOperand(Inst.getOperand(0));
582 TmpInst.addOperand(Inst.getOperand(2));
583 TmpInst.addOperand(Inst.getOperand(1));
589 int64_t N = Inst.getOperand(2).getImm();
590 TmpInst.setOpcode(PPC::ADDI);
591 TmpInst.addOperand(Inst.getOperand(0));
592 TmpInst.addOperand(Inst.getOperand(1));
593 TmpInst.addOperand(MCOperand::CreateImm(-N));
599 int64_t N = Inst.getOperand(2).getImm();
600 TmpInst.setOpcode(PPC::ADDIS);
601 TmpInst.addOperand(Inst.getOperand(0));
602 TmpInst.addOperand(Inst.getOperand(1));
603 TmpInst.addOperand(MCOperand::CreateImm(-N));
609 int64_t N = Inst.getOperand(2).getImm();
610 TmpInst.setOpcode(PPC::ADDIC);
611 TmpInst.addOperand(Inst.getOperand(0));
612 TmpInst.addOperand(Inst.getOperand(1));
613 TmpInst.addOperand(MCOperand::CreateImm(-N));
619 int64_t N = Inst.getOperand(2).getImm();
620 TmpInst.setOpcode(PPC::ADDICo);
621 TmpInst.addOperand(Inst.getOperand(0));
622 TmpInst.addOperand(Inst.getOperand(1));
623 TmpInst.addOperand(MCOperand::CreateImm(-N));
630 int64_t N = Inst.getOperand(2).getImm();
631 int64_t B = Inst.getOperand(3).getImm();
632 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
633 TmpInst.addOperand(Inst.getOperand(0));
634 TmpInst.addOperand(Inst.getOperand(1));
635 TmpInst.addOperand(MCOperand::CreateImm(B));
636 TmpInst.addOperand(MCOperand::CreateImm(0));
637 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
644 int64_t N = Inst.getOperand(2).getImm();
645 int64_t B = Inst.getOperand(3).getImm();
646 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
647 TmpInst.addOperand(Inst.getOperand(0));
648 TmpInst.addOperand(Inst.getOperand(1));
649 TmpInst.addOperand(MCOperand::CreateImm(B + N));
650 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
651 TmpInst.addOperand(MCOperand::CreateImm(31));
658 int64_t N = Inst.getOperand(2).getImm();
659 int64_t B = Inst.getOperand(3).getImm();
660 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
661 TmpInst.addOperand(Inst.getOperand(0));
662 TmpInst.addOperand(Inst.getOperand(0));
663 TmpInst.addOperand(Inst.getOperand(1));
664 TmpInst.addOperand(MCOperand::CreateImm(32 - B));
665 TmpInst.addOperand(MCOperand::CreateImm(B));
666 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
673 int64_t N = Inst.getOperand(2).getImm();
674 int64_t B = Inst.getOperand(3).getImm();
675 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
676 TmpInst.addOperand(Inst.getOperand(0));
677 TmpInst.addOperand(Inst.getOperand(0));
678 TmpInst.addOperand(Inst.getOperand(1));
679 TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
680 TmpInst.addOperand(MCOperand::CreateImm(B));
681 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
688 int64_t N = Inst.getOperand(2).getImm();
689 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
690 TmpInst.addOperand(Inst.getOperand(0));
691 TmpInst.addOperand(Inst.getOperand(1));
692 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
693 TmpInst.addOperand(MCOperand::CreateImm(0));
694 TmpInst.addOperand(MCOperand::CreateImm(31));
701 int64_t N = Inst.getOperand(2).getImm();
702 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
703 TmpInst.addOperand(Inst.getOperand(0));
704 TmpInst.addOperand(Inst.getOperand(1));
705 TmpInst.addOperand(MCOperand::CreateImm(N));
706 TmpInst.addOperand(MCOperand::CreateImm(0));
707 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
714 int64_t N = Inst.getOperand(2).getImm();
715 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
716 TmpInst.addOperand(Inst.getOperand(0));
717 TmpInst.addOperand(Inst.getOperand(1));
718 TmpInst.addOperand(MCOperand::CreateImm(32 - N));
719 TmpInst.addOperand(MCOperand::CreateImm(N));
720 TmpInst.addOperand(MCOperand::CreateImm(31));
727 int64_t N = Inst.getOperand(2).getImm();
728 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
729 TmpInst.addOperand(Inst.getOperand(0));
730 TmpInst.addOperand(Inst.getOperand(1));
731 TmpInst.addOperand(MCOperand::CreateImm(0));
732 TmpInst.addOperand(MCOperand::CreateImm(0));
733 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
738 case PPC::CLRLSLWIo: {
740 int64_t B = Inst.getOperand(2).getImm();
741 int64_t N = Inst.getOperand(3).getImm();
742 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
743 TmpInst.addOperand(Inst.getOperand(0));
744 TmpInst.addOperand(Inst.getOperand(1));
745 TmpInst.addOperand(MCOperand::CreateImm(N));
746 TmpInst.addOperand(MCOperand::CreateImm(B - N));
747 TmpInst.addOperand(MCOperand::CreateImm(31 - N));
754 int64_t N = Inst.getOperand(2).getImm();
755 int64_t B = Inst.getOperand(3).getImm();
756 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
757 TmpInst.addOperand(Inst.getOperand(0));
758 TmpInst.addOperand(Inst.getOperand(1));
759 TmpInst.addOperand(MCOperand::CreateImm(B));
760 TmpInst.addOperand(MCOperand::CreateImm(N - 1));
767 int64_t N = Inst.getOperand(2).getImm();
768 int64_t B = Inst.getOperand(3).getImm();
769 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
770 TmpInst.addOperand(Inst.getOperand(0));
771 TmpInst.addOperand(Inst.getOperand(1));
772 TmpInst.addOperand(MCOperand::CreateImm(B + N));
773 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
780 int64_t N = Inst.getOperand(2).getImm();
781 int64_t B = Inst.getOperand(3).getImm();
782 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
783 TmpInst.addOperand(Inst.getOperand(0));
784 TmpInst.addOperand(Inst.getOperand(0));
785 TmpInst.addOperand(Inst.getOperand(1));
786 TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
787 TmpInst.addOperand(MCOperand::CreateImm(B));
794 int64_t N = Inst.getOperand(2).getImm();
795 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
796 TmpInst.addOperand(Inst.getOperand(0));
797 TmpInst.addOperand(Inst.getOperand(1));
798 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
799 TmpInst.addOperand(MCOperand::CreateImm(0));
806 int64_t N = Inst.getOperand(2).getImm();
807 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
808 TmpInst.addOperand(Inst.getOperand(0));
809 TmpInst.addOperand(Inst.getOperand(1));
810 TmpInst.addOperand(MCOperand::CreateImm(N));
811 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
818 int64_t N = Inst.getOperand(2).getImm();
819 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
820 TmpInst.addOperand(Inst.getOperand(0));
821 TmpInst.addOperand(Inst.getOperand(1));
822 TmpInst.addOperand(MCOperand::CreateImm(64 - N));
823 TmpInst.addOperand(MCOperand::CreateImm(N));
830 int64_t N = Inst.getOperand(2).getImm();
831 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
832 TmpInst.addOperand(Inst.getOperand(0));
833 TmpInst.addOperand(Inst.getOperand(1));
834 TmpInst.addOperand(MCOperand::CreateImm(0));
835 TmpInst.addOperand(MCOperand::CreateImm(63 - N));
840 case PPC::CLRLSLDIo: {
842 int64_t B = Inst.getOperand(2).getImm();
843 int64_t N = Inst.getOperand(3).getImm();
844 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
845 TmpInst.addOperand(Inst.getOperand(0));
846 TmpInst.addOperand(Inst.getOperand(1));
847 TmpInst.addOperand(MCOperand::CreateImm(N));
848 TmpInst.addOperand(MCOperand::CreateImm(B - N));
856 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
857 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
858 MCStreamer &Out, unsigned &ErrorInfo,
859 bool MatchingInlineAsm) {
862 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
865 // Post-process instructions (typically extended mnemonics)
866 ProcessInstruction(Inst, Operands);
868 Out.EmitInstruction(Inst);
870 case Match_MissingFeature:
871 return Error(IDLoc, "instruction use requires an option to be enabled");
872 case Match_MnemonicFail:
873 return Error(IDLoc, "unrecognized instruction mnemonic");
874 case Match_InvalidOperand: {
875 SMLoc ErrorLoc = IDLoc;
876 if (ErrorInfo != ~0U) {
877 if (ErrorInfo >= Operands.size())
878 return Error(IDLoc, "too few operands for instruction");
880 ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc();
881 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
884 return Error(ErrorLoc, "invalid operand for instruction");
888 llvm_unreachable("Implement any new match types added!");
892 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
893 if (Tok.is(AsmToken::Identifier)) {
894 StringRef Name = Tok.getString();
896 if (Name.equals_lower("lr")) {
897 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
900 } else if (Name.equals_lower("ctr")) {
901 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
904 } else if (Name.equals_lower("vrsave")) {
908 } else if (Name.substr(0, 1).equals_lower("r") &&
909 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
910 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
912 } else if (Name.substr(0, 1).equals_lower("f") &&
913 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
914 RegNo = FRegs[IntVal];
916 } else if (Name.substr(0, 1).equals_lower("v") &&
917 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
918 RegNo = VRegs[IntVal];
920 } else if (Name.substr(0, 2).equals_lower("cr") &&
921 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
922 RegNo = CRRegs[IntVal];
931 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
932 const AsmToken &Tok = Parser.getTok();
933 StartLoc = Tok.getLoc();
934 EndLoc = Tok.getEndLoc();
938 if (!MatchRegisterName(Tok, RegNo, IntVal)) {
939 Parser.Lex(); // Eat identifier token.
943 return Error(StartLoc, "invalid register name");
946 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
947 /// the expression and check for VK_PPC_LO/HI/HA
948 /// symbol variants. If all symbols with modifier use the same
949 /// variant, return the corresponding PPCMCExpr::VariantKind,
950 /// and a modified expression using the default symbol variant.
951 /// Otherwise, return NULL.
952 const MCExpr *PPCAsmParser::
953 ExtractModifierFromExpr(const MCExpr *E,
954 PPCMCExpr::VariantKind &Variant) {
955 MCContext &Context = getParser().getContext();
956 Variant = PPCMCExpr::VK_PPC_None;
958 switch (E->getKind()) {
960 case MCExpr::Constant:
963 case MCExpr::SymbolRef: {
964 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
966 switch (SRE->getKind()) {
967 case MCSymbolRefExpr::VK_PPC_LO:
968 Variant = PPCMCExpr::VK_PPC_LO;
970 case MCSymbolRefExpr::VK_PPC_HI:
971 Variant = PPCMCExpr::VK_PPC_HI;
973 case MCSymbolRefExpr::VK_PPC_HA:
974 Variant = PPCMCExpr::VK_PPC_HA;
976 case MCSymbolRefExpr::VK_PPC_HIGHER:
977 Variant = PPCMCExpr::VK_PPC_HIGHER;
979 case MCSymbolRefExpr::VK_PPC_HIGHERA:
980 Variant = PPCMCExpr::VK_PPC_HIGHERA;
982 case MCSymbolRefExpr::VK_PPC_HIGHEST:
983 Variant = PPCMCExpr::VK_PPC_HIGHEST;
985 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
986 Variant = PPCMCExpr::VK_PPC_HIGHESTA;
992 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
995 case MCExpr::Unary: {
996 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
997 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1000 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1003 case MCExpr::Binary: {
1004 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1005 PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1006 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1007 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1012 if (!LHS) LHS = BE->getLHS();
1013 if (!RHS) RHS = BE->getRHS();
1015 if (LHSVariant == PPCMCExpr::VK_PPC_None)
1016 Variant = RHSVariant;
1017 else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1018 Variant = LHSVariant;
1019 else if (LHSVariant == RHSVariant)
1020 Variant = LHSVariant;
1024 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1028 llvm_unreachable("Invalid expression kind!");
1031 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1032 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having
1033 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1034 /// FIXME: This is a hack.
1035 const MCExpr *PPCAsmParser::
1036 FixupVariantKind(const MCExpr *E) {
1037 MCContext &Context = getParser().getContext();
1039 switch (E->getKind()) {
1040 case MCExpr::Target:
1041 case MCExpr::Constant:
1044 case MCExpr::SymbolRef: {
1045 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1046 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1048 switch (SRE->getKind()) {
1049 case MCSymbolRefExpr::VK_TLSGD:
1050 Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1052 case MCSymbolRefExpr::VK_TLSLD:
1053 Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1058 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context);
1061 case MCExpr::Unary: {
1062 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1063 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1064 if (Sub == UE->getSubExpr())
1066 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1069 case MCExpr::Binary: {
1070 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1071 const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1072 const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1073 if (LHS == BE->getLHS() && RHS == BE->getRHS())
1075 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1079 llvm_unreachable("Invalid expression kind!");
1082 /// Parse an expression. This differs from the default "parseExpression"
1083 /// in that it handles complex \code @l/@ha \endcode modifiers.
1085 ParseExpression(const MCExpr *&EVal) {
1086 if (getParser().parseExpression(EVal))
1089 EVal = FixupVariantKind(EVal);
1091 PPCMCExpr::VariantKind Variant;
1092 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1094 EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
1100 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1101 SMLoc S = Parser.getTok().getLoc();
1102 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1106 // Attempt to parse the next token as an immediate
1107 switch (getLexer().getKind()) {
1108 // Special handling for register names. These are interpreted
1109 // as immediates corresponding to the register number.
1110 case AsmToken::Percent:
1111 Parser.Lex(); // Eat the '%'.
1114 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1115 Parser.Lex(); // Eat the identifier token.
1116 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1117 Operands.push_back(Op);
1120 return Error(S, "invalid register name");
1122 // All other expressions
1123 case AsmToken::LParen:
1124 case AsmToken::Plus:
1125 case AsmToken::Minus:
1126 case AsmToken::Integer:
1127 case AsmToken::Identifier:
1129 case AsmToken::Dollar:
1130 if (!ParseExpression(EVal))
1134 return Error(S, "unknown operand");
1137 // Push the parsed operand into the list of operands
1138 Op = PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64());
1139 Operands.push_back(Op);
1141 // Check whether this is a TLS call expression
1142 bool TLSCall = false;
1143 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1144 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1146 if (TLSCall && getLexer().is(AsmToken::LParen)) {
1147 const MCExpr *TLSSym;
1149 Parser.Lex(); // Eat the '('.
1150 S = Parser.getTok().getLoc();
1151 if (ParseExpression(TLSSym))
1152 return Error(S, "invalid TLS call expression");
1153 if (getLexer().isNot(AsmToken::RParen))
1154 return Error(Parser.getTok().getLoc(), "missing ')'");
1155 E = Parser.getTok().getLoc();
1156 Parser.Lex(); // Eat the ')'.
1158 Op = PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64());
1159 Operands.push_back(Op);
1162 // Otherwise, check for D-form memory operands
1163 if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1164 Parser.Lex(); // Eat the '('.
1165 S = Parser.getTok().getLoc();
1168 switch (getLexer().getKind()) {
1169 case AsmToken::Percent:
1170 Parser.Lex(); // Eat the '%'.
1172 if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1173 return Error(S, "invalid register name");
1174 Parser.Lex(); // Eat the identifier token.
1177 case AsmToken::Integer:
1178 if (getParser().parseAbsoluteExpression(IntVal) ||
1179 IntVal < 0 || IntVal > 31)
1180 return Error(S, "invalid register number");
1184 return Error(S, "invalid memory operand");
1187 if (getLexer().isNot(AsmToken::RParen))
1188 return Error(Parser.getTok().getLoc(), "missing ')'");
1189 E = Parser.getTok().getLoc();
1190 Parser.Lex(); // Eat the ')'.
1192 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1193 Operands.push_back(Op);
1199 /// Parse an instruction mnemonic followed by its operands.
1201 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1202 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1203 // The first operand is the token for the instruction name.
1204 // If the next character is a '+' or '-', we need to add it to the
1205 // instruction name, to match what TableGen is doing.
1206 std::string NewOpcode;
1207 if (getLexer().is(AsmToken::Plus)) {
1213 if (getLexer().is(AsmToken::Minus)) {
1219 // If the instruction ends in a '.', we need to create a separate
1220 // token for it, to match what TableGen is doing.
1221 size_t Dot = Name.find('.');
1222 StringRef Mnemonic = Name.slice(0, Dot);
1223 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1225 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1227 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1228 if (Dot != StringRef::npos) {
1229 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1230 StringRef DotStr = Name.slice(Dot, StringRef::npos);
1231 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1233 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1235 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1238 // If there are no more operands then finish
1239 if (getLexer().is(AsmToken::EndOfStatement))
1242 // Parse the first operand
1243 if (ParseOperand(Operands))
1246 while (getLexer().isNot(AsmToken::EndOfStatement) &&
1247 getLexer().is(AsmToken::Comma)) {
1248 // Consume the comma token
1251 // Parse the next operand
1252 if (ParseOperand(Operands))
1259 /// ParseDirective parses the PPC specific directives
1260 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1261 StringRef IDVal = DirectiveID.getIdentifier();
1262 if (IDVal == ".word")
1263 return ParseDirectiveWord(2, DirectiveID.getLoc());
1264 if (IDVal == ".llong")
1265 return ParseDirectiveWord(8, DirectiveID.getLoc());
1267 return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1268 if (IDVal == ".machine")
1269 return ParseDirectiveMachine(DirectiveID.getLoc());
1273 /// ParseDirectiveWord
1274 /// ::= .word [ expression (, expression)* ]
1275 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1276 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1278 const MCExpr *Value;
1279 if (getParser().parseExpression(Value))
1282 getParser().getStreamer().EmitValue(Value, Size);
1284 if (getLexer().is(AsmToken::EndOfStatement))
1287 if (getLexer().isNot(AsmToken::Comma))
1288 return Error(L, "unexpected token in directive");
1297 /// ParseDirectiveTC
1298 /// ::= .tc [ symbol (, expression)* ]
1299 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1300 // Skip TC symbol, which is only used with XCOFF.
1301 while (getLexer().isNot(AsmToken::EndOfStatement)
1302 && getLexer().isNot(AsmToken::Comma))
1304 if (getLexer().isNot(AsmToken::Comma))
1305 return Error(L, "unexpected token in directive");
1308 // Align to word size.
1309 getParser().getStreamer().EmitValueToAlignment(Size);
1311 // Emit expressions.
1312 return ParseDirectiveWord(Size, L);
1315 /// ParseDirectiveMachine
1316 /// ::= .machine [ cpu | "push" | "pop" ]
1317 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1318 if (getLexer().isNot(AsmToken::Identifier) &&
1319 getLexer().isNot(AsmToken::String))
1320 return Error(L, "unexpected token in directive");
1322 StringRef CPU = Parser.getTok().getIdentifier();
1325 // FIXME: Right now, the parser always allows any available
1326 // instruction, so the .machine directive is not useful.
1327 // Implement ".machine any" (by doing nothing) for the benefit
1328 // of existing assembler code. Likewise, we can then implement
1329 // ".machine push" and ".machine pop" as no-op.
1330 if (CPU != "any" && CPU != "push" && CPU != "pop")
1331 return Error(L, "unrecognized machine type");
1333 if (getLexer().isNot(AsmToken::EndOfStatement))
1334 return Error(L, "unexpected token in directive");
1339 /// Force static initialization.
1340 extern "C" void LLVMInitializePowerPCAsmParser() {
1341 RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1342 RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1343 RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1346 #define GET_REGISTER_MATCHER
1347 #define GET_MATCHER_IMPLEMENTATION
1348 #include "PPCGenAsmMatcher.inc"
1350 // Define this matcher function after the auto-generated include so we
1351 // have the match class enum definitions.
1352 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
1354 // If the kind is a token for a literal immediate, check if our asm
1355 // operand matches. This is for InstAliases which have a fixed-value
1356 // immediate in the syntax.
1359 case MCK_0: ImmVal = 0; break;
1360 case MCK_1: ImmVal = 1; break;
1361 default: return Match_InvalidOperand;
1364 PPCOperand *Op = static_cast<PPCOperand*>(AsmOp);
1365 if (Op->isImm() && Op->getImm() == ImmVal)
1366 return Match_Success;
1368 return Match_InvalidOperand;
1372 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1373 MCSymbolRefExpr::VariantKind Variant,
1376 case MCSymbolRefExpr::VK_PPC_LO:
1377 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1378 case MCSymbolRefExpr::VK_PPC_HI:
1379 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1380 case MCSymbolRefExpr::VK_PPC_HA:
1381 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1382 case MCSymbolRefExpr::VK_PPC_HIGHER:
1383 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1384 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1385 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1386 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1387 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1388 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1389 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);