1 //===- PTXInstrInfo.td - PTX Instruction defs -----------------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PTX instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "PTXInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Instruction Pattern Stuff
22 //===----------------------------------------------------------------------===//
24 def load_global : PatFrag<(ops node:$ptr), (load node:$ptr), [{
26 const PointerType *PT;
27 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
28 (PT = dyn_cast<PointerType>(Src->getType())))
29 return PT->getAddressSpace() == PTX::GLOBAL;
33 def load_constant : PatFrag<(ops node:$ptr), (load node:$ptr), [{
35 const PointerType *PT;
36 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
37 (PT = dyn_cast<PointerType>(Src->getType())))
38 return PT->getAddressSpace() == PTX::CONSTANT;
42 def load_local : PatFrag<(ops node:$ptr), (load node:$ptr), [{
44 const PointerType *PT;
45 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
46 (PT = dyn_cast<PointerType>(Src->getType())))
47 return PT->getAddressSpace() == PTX::LOCAL;
51 def load_parameter : PatFrag<(ops node:$ptr), (load node:$ptr), [{
53 const PointerType *PT;
54 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
55 (PT = dyn_cast<PointerType>(Src->getType())))
56 return PT->getAddressSpace() == PTX::PARAMETER;
60 def load_shared : PatFrag<(ops node:$ptr), (load node:$ptr), [{
62 const PointerType *PT;
63 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
64 (PT = dyn_cast<PointerType>(Src->getType())))
65 return PT->getAddressSpace() == PTX::SHARED;
70 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
72 const PointerType *PT;
73 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
74 (PT = dyn_cast<PointerType>(Src->getType())))
75 return PT->getAddressSpace() == PTX::GLOBAL;
80 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
82 const PointerType *PT;
83 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
84 (PT = dyn_cast<PointerType>(Src->getType())))
85 return PT->getAddressSpace() == PTX::LOCAL;
90 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
92 const PointerType *PT;
93 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
94 (PT = dyn_cast<PointerType>(Src->getType())))
95 return PT->getAddressSpace() == PTX::PARAMETER;
100 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
102 const PointerType *PT;
103 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
104 (PT = dyn_cast<PointerType>(Src->getType())))
105 return PT->getAddressSpace() == PTX::SHARED;
110 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
111 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [], []>;
112 def ADDRii : ComplexPattern<i32, 2, "SelectADDRii", [], []>;
115 def MEMri : Operand<i32> {
116 let PrintMethod = "printMemOperand";
117 let MIOperandInfo = (ops RRegs32, i32imm);
119 def MEMii : Operand<i32> {
120 let PrintMethod = "printMemOperand";
121 let MIOperandInfo = (ops i32imm, i32imm);
123 def MEMpi : Operand<i32> {
124 let PrintMethod = "printParamOperand";
125 let MIOperandInfo = (ops i32imm);
128 //===----------------------------------------------------------------------===//
129 // PTX Specific Node Definitions
130 //===----------------------------------------------------------------------===//
132 // PTX allow generic 3-reg shifts like shl r0, r1, r2
133 def PTXshl : SDNode<"ISD::SHL", SDTIntBinOp>;
134 def PTXsrl : SDNode<"ISD::SRL", SDTIntBinOp>;
135 def PTXsra : SDNode<"ISD::SRA", SDTIntBinOp>;
138 : SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>;
140 : SDNode<"PTXISD::RET", SDTNone, [SDNPHasChain]>;
142 //===----------------------------------------------------------------------===//
143 // Instruction Class Templates
144 //===----------------------------------------------------------------------===//
146 // Three-operand f32 instruction template
147 multiclass FLOAT3<string opcstr, SDNode opnode> {
148 def rr : InstPTX<(outs RRegf32:$d),
149 (ins RRegf32:$a, RRegf32:$b),
150 !strconcat(opcstr, ".%type\t$d, $a, $b"),
151 [(set RRegf32:$d, (opnode RRegf32:$a, RRegf32:$b))]>;
152 def ri : InstPTX<(outs RRegf32:$d),
153 (ins RRegf32:$a, f32imm:$b),
154 !strconcat(opcstr, ".%type\t$d, $a, $b"),
155 [(set RRegf32:$d, (opnode RRegf32:$a, fpimm:$b))]>;
158 multiclass INT3<string opcstr, SDNode opnode> {
159 def rr : InstPTX<(outs RRegs32:$d),
160 (ins RRegs32:$a, RRegs32:$b),
161 !strconcat(opcstr, ".%type\t$d, $a, $b"),
162 [(set RRegs32:$d, (opnode RRegs32:$a, RRegs32:$b))]>;
163 def ri : InstPTX<(outs RRegs32:$d),
164 (ins RRegs32:$a, i32imm:$b),
165 !strconcat(opcstr, ".%type\t$d, $a, $b"),
166 [(set RRegs32:$d, (opnode RRegs32:$a, imm:$b))]>;
169 // no %type directive, non-communtable
170 multiclass INT3ntnc<string opcstr, SDNode opnode> {
171 def rr : InstPTX<(outs RRegs32:$d),
172 (ins RRegs32:$a, RRegs32:$b),
173 !strconcat(opcstr, "\t$d, $a, $b"),
174 [(set RRegs32:$d, (opnode RRegs32:$a, RRegs32:$b))]>;
175 def ri : InstPTX<(outs RRegs32:$d),
176 (ins RRegs32:$a, i32imm:$b),
177 !strconcat(opcstr, "\t$d, $a, $b"),
178 [(set RRegs32:$d, (opnode RRegs32:$a, imm:$b))]>;
179 def ir : InstPTX<(outs RRegs32:$d),
180 (ins i32imm:$a, RRegs32:$b),
181 !strconcat(opcstr, "\t$d, $a, $b"),
182 [(set RRegs32:$d, (opnode imm:$a, RRegs32:$b))]>;
185 multiclass PTX_LD<string opstr, RegisterClass RC, PatFrag pat_load> {
186 def rr : InstPTX<(outs RC:$d),
188 !strconcat(opstr, ".%type\t$d, [$a]"),
189 [(set RC:$d, (pat_load ADDRrr:$a))]>;
190 def ri : InstPTX<(outs RC:$d),
192 !strconcat(opstr, ".%type\t$d, [$a]"),
193 [(set RC:$d, (pat_load ADDRri:$a))]>;
194 def ii : InstPTX<(outs RC:$d),
196 !strconcat(opstr, ".%type\t$d, [$a]"),
197 [(set RC:$d, (pat_load ADDRii:$a))]>;
200 multiclass PTX_ST<string opstr, RegisterClass RC, PatFrag pat_store> {
201 def rr : InstPTX<(outs),
202 (ins RC:$d, MEMri:$a),
203 !strconcat(opstr, ".%type\t[$a], $d"),
204 [(pat_store RC:$d, ADDRrr:$a)]>;
205 def ri : InstPTX<(outs),
206 (ins RC:$d, MEMri:$a),
207 !strconcat(opstr, ".%type\t[$a], $d"),
208 [(pat_store RC:$d, ADDRri:$a)]>;
209 def ii : InstPTX<(outs),
210 (ins RC:$d, MEMii:$a),
211 !strconcat(opstr, ".%type\t[$a], $d"),
212 [(pat_store RC:$d, ADDRii:$a)]>;
215 //===----------------------------------------------------------------------===//
217 //===----------------------------------------------------------------------===//
219 ///===- Floating-Point Arithmetic Instructions ----------------------------===//
221 defm FADD : FLOAT3<"add", fadd>;
222 defm FSUB : FLOAT3<"sub", fsub>;
223 defm FMUL : FLOAT3<"mul", fmul>;
225 ///===- Integer Arithmetic Instructions -----------------------------------===//
227 defm ADD : INT3<"add", add>;
228 defm SUB : INT3<"sub", sub>;
230 ///===- Logic and Shift Instructions --------------------------------------===//
232 defm SHL : INT3ntnc<"shl.b32", PTXshl>;
233 defm SRL : INT3ntnc<"shr.u32", PTXsrl>;
234 defm SRA : INT3ntnc<"shr.s32", PTXsra>;
236 ///===- Data Movement and Conversion Instructions -------------------------===//
238 let neverHasSideEffects = 1 in {
239 // rely on isMoveInstr to separate MOVpp, MOVrr, etc.
241 : InstPTX<(outs Preds:$d), (ins Preds:$a), "mov.pred\t$d, $a", []>;
243 : InstPTX<(outs RRegs32:$d), (ins RRegs32:$a), "mov.%type\t$d, $a", []>;
245 : InstPTX<(outs RRegf32:$d), (ins RRegf32:$a), "mov.f32\t$d, $a", []>;
248 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
250 : InstPTX<(outs Preds:$d), (ins i1imm:$a), "mov.pred\t$d, $a",
251 [(set Preds:$d, imm:$a)]>;
253 : InstPTX<(outs RRegs32:$d), (ins i32imm:$a), "mov.s32\t$d, $a",
254 [(set RRegs32:$d, imm:$a)]>;
256 : InstPTX<(outs RRegf32:$d), (ins f32imm:$a), "mov.f32\t$d, $a",
257 [(set RRegf32:$d, fpimm:$a)]>;
261 defm LDg : PTX_LD<"ld.global", RRegs32, load_global>;
262 defm LDc : PTX_LD<"ld.const", RRegs32, load_constant>;
263 defm LDl : PTX_LD<"ld.local", RRegs32, load_local>;
264 defm LDp : PTX_LD<"ld.param", RRegs32, load_parameter>;
265 defm LDs : PTX_LD<"ld.shared", RRegs32, load_shared>;
267 def LDpi : InstPTX<(outs RRegs32:$d), (ins MEMpi:$a),
268 "ld.param.%type\t$d, [$a]", []>;
270 // Floating-point loads
271 defm FLDg : PTX_LD<"ld.global", RRegf32, load_global>;
272 defm FLDc : PTX_LD<"ld.const", RRegf32, load_constant>;
273 defm FLDl : PTX_LD<"ld.local", RRegf32, load_local>;
274 defm FLDp : PTX_LD<"ld.param", RRegf32, load_parameter>;
275 defm FLDs : PTX_LD<"ld.shared", RRegf32, load_shared>;
277 def FLDpi : InstPTX<(outs RRegf32:$d), (ins MEMpi:$a),
278 "ld.param.%type\t$d, [$a]", []>;
281 defm STg : PTX_ST<"st.global", RRegs32, store_global>;
282 defm STl : PTX_ST<"st.local", RRegs32, store_local>;
283 // Store to parameter state space requires PTX 2.0 or higher?
284 // defm STp : PTX_ST<"st.param", RRegs32, store_parameter>;
285 defm STs : PTX_ST<"st.shared", RRegs32, store_shared>;
287 // Floating-point stores
288 defm FSTg : PTX_ST<"st.global", RRegf32, store_global>;
289 defm FSTl : PTX_ST<"st.local", RRegf32, store_local>;
290 // Store to parameter state space requires PTX 2.0 or higher?
291 // defm FSTp : PTX_ST<"st.param", RRegf32, store_parameter>;
292 defm FSTs : PTX_ST<"st.shared", RRegf32, store_shared>;
294 ///===- Control Flow Instructions -----------------------------------------===//
296 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
297 def EXIT : InstPTX<(outs), (ins), "exit", [(PTXexit)]>;
298 def RET : InstPTX<(outs), (ins), "ret", [(PTXret)]>;