1 //===- PTXInstrInfo.td - PTX Instruction defs -----------------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PTX instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "PTXInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Code Generation Predicates
22 //===----------------------------------------------------------------------===//
25 def Use32BitAddresses : Predicate<"!getSubtarget().is64Bit()">;
26 def Use64BitAddresses : Predicate<"getSubtarget().is64Bit()">;
28 // Shader Model Support
29 def SupportsSM13 : Predicate<"getSubtarget().supportsSM13()">;
30 def DoesNotSupportSM13 : Predicate<"!getSubtarget().supportsSM13()">;
31 def SupportsSM20 : Predicate<"getSubtarget().supportsSM20()">;
32 def DoesNotSupportSM20 : Predicate<"!getSubtarget().supportsSM20()">;
34 // PTX Version Support
35 def SupportsPTX21 : Predicate<"getSubtarget().supportsPTX21()">;
36 def DoesNotSupportPTX21 : Predicate<"!getSubtarget().supportsPTX21()">;
37 def SupportsPTX22 : Predicate<"getSubtarget().supportsPTX22()">;
38 def DoesNotSupportPTX22 : Predicate<"!getSubtarget().supportsPTX22()">;
39 def SupportsPTX23 : Predicate<"getSubtarget().supportsPTX23()">;
40 def DoesNotSupportPTX23 : Predicate<"!getSubtarget().supportsPTX23()">;
42 //===----------------------------------------------------------------------===//
43 // Instruction Pattern Stuff
44 //===----------------------------------------------------------------------===//
46 def load_global : PatFrag<(ops node:$ptr), (load node:$ptr), [{
48 const PointerType *PT;
49 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
50 (PT = dyn_cast<PointerType>(Src->getType())))
51 return PT->getAddressSpace() == PTX::GLOBAL;
55 def load_constant : PatFrag<(ops node:$ptr), (load node:$ptr), [{
57 const PointerType *PT;
58 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
59 (PT = dyn_cast<PointerType>(Src->getType())))
60 return PT->getAddressSpace() == PTX::CONSTANT;
64 def load_local : PatFrag<(ops node:$ptr), (load node:$ptr), [{
66 const PointerType *PT;
67 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
68 (PT = dyn_cast<PointerType>(Src->getType())))
69 return PT->getAddressSpace() == PTX::LOCAL;
73 def load_parameter : PatFrag<(ops node:$ptr), (load node:$ptr), [{
75 const PointerType *PT;
76 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
77 (PT = dyn_cast<PointerType>(Src->getType())))
78 return PT->getAddressSpace() == PTX::PARAMETER;
82 def load_shared : PatFrag<(ops node:$ptr), (load node:$ptr), [{
84 const PointerType *PT;
85 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
86 (PT = dyn_cast<PointerType>(Src->getType())))
87 return PT->getAddressSpace() == PTX::SHARED;
92 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
94 const PointerType *PT;
95 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
96 (PT = dyn_cast<PointerType>(Src->getType())))
97 return PT->getAddressSpace() == PTX::GLOBAL;
102 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
104 const PointerType *PT;
105 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
106 (PT = dyn_cast<PointerType>(Src->getType())))
107 return PT->getAddressSpace() == PTX::LOCAL;
112 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
114 const PointerType *PT;
115 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
116 (PT = dyn_cast<PointerType>(Src->getType())))
117 return PT->getAddressSpace() == PTX::PARAMETER;
122 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
124 const PointerType *PT;
125 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
126 (PT = dyn_cast<PointerType>(Src->getType())))
127 return PT->getAddressSpace() == PTX::SHARED;
132 def ADDRrr32 : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
133 def ADDRrr64 : ComplexPattern<i64, 2, "SelectADDRrr", [], []>;
134 def ADDRri32 : ComplexPattern<i32, 2, "SelectADDRri", [], []>;
135 def ADDRri64 : ComplexPattern<i64, 2, "SelectADDRri", [], []>;
136 def ADDRii32 : ComplexPattern<i32, 2, "SelectADDRii", [], []>;
137 def ADDRii64 : ComplexPattern<i64, 2, "SelectADDRii", [], []>;
140 def MEMri32 : Operand<i32> {
141 let PrintMethod = "printMemOperand";
142 let MIOperandInfo = (ops RRegu32, i32imm);
144 def MEMri64 : Operand<i64> {
145 let PrintMethod = "printMemOperand";
146 let MIOperandInfo = (ops RRegu64, i64imm);
148 def MEMii32 : Operand<i32> {
149 let PrintMethod = "printMemOperand";
150 let MIOperandInfo = (ops i32imm, i32imm);
152 def MEMii64 : Operand<i64> {
153 let PrintMethod = "printMemOperand";
154 let MIOperandInfo = (ops i64imm, i64imm);
156 // The operand here does not correspond to an actual address, so we
157 // can use i32 in 64-bit address modes.
158 def MEMpi : Operand<i32> {
159 let PrintMethod = "printParamOperand";
160 let MIOperandInfo = (ops i32imm);
163 // Branch & call targets have OtherVT type.
164 def brtarget : Operand<OtherVT>;
165 def calltarget : Operand<i32>;
167 //===----------------------------------------------------------------------===//
168 // PTX Specific Node Definitions
169 //===----------------------------------------------------------------------===//
171 // PTX allow generic 3-reg shifts like shl r0, r1, r2
172 def PTXshl : SDNode<"ISD::SHL", SDTIntBinOp>;
173 def PTXsrl : SDNode<"ISD::SRL", SDTIntBinOp>;
174 def PTXsra : SDNode<"ISD::SRA", SDTIntBinOp>;
177 : SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>;
179 : SDNode<"PTXISD::RET", SDTNone, [SDNPHasChain]>;
181 : SDNode<"PTXISD::COPY_ADDRESS", SDTypeProfile<1, 1, []>, []>;
183 //===----------------------------------------------------------------------===//
184 // Instruction Class Templates
185 //===----------------------------------------------------------------------===//
187 //===- Floating-Point Instructions - 2 Operand Form -----------------------===//
188 multiclass PTX_FLOAT_2OP<string opcstr, SDNode opnode> {
189 def rr32 : InstPTX<(outs RRegf32:$d),
191 !strconcat(opcstr, ".f32\t$d, $a"),
192 [(set RRegf32:$d, (opnode RRegf32:$a))]>;
193 def ri32 : InstPTX<(outs RRegf32:$d),
195 !strconcat(opcstr, ".f32\t$d, $a"),
196 [(set RRegf32:$d, (opnode fpimm:$a))]>;
197 def rr64 : InstPTX<(outs RRegf64:$d),
199 !strconcat(opcstr, ".f64\t$d, $a"),
200 [(set RRegf64:$d, (opnode RRegf64:$a))]>;
201 def ri64 : InstPTX<(outs RRegf64:$d),
203 !strconcat(opcstr, ".f64\t$d, $a"),
204 [(set RRegf64:$d, (opnode fpimm:$a))]>;
207 //===- Floating-Point Instructions - 3 Operand Form -----------------------===//
208 multiclass PTX_FLOAT_3OP<string opcstr, SDNode opnode> {
209 def rr32 : InstPTX<(outs RRegf32:$d),
210 (ins RRegf32:$a, RRegf32:$b),
211 !strconcat(opcstr, ".f32\t$d, $a, $b"),
212 [(set RRegf32:$d, (opnode RRegf32:$a, RRegf32:$b))]>;
213 def ri32 : InstPTX<(outs RRegf32:$d),
214 (ins RRegf32:$a, f32imm:$b),
215 !strconcat(opcstr, ".f32\t$d, $a, $b"),
216 [(set RRegf32:$d, (opnode RRegf32:$a, fpimm:$b))]>;
217 def rr64 : InstPTX<(outs RRegf64:$d),
218 (ins RRegf64:$a, RRegf64:$b),
219 !strconcat(opcstr, ".f64\t$d, $a, $b"),
220 [(set RRegf64:$d, (opnode RRegf64:$a, RRegf64:$b))]>;
221 def ri64 : InstPTX<(outs RRegf64:$d),
222 (ins RRegf64:$a, f64imm:$b),
223 !strconcat(opcstr, ".f64\t$d, $a, $b"),
224 [(set RRegf64:$d, (opnode RRegf64:$a, fpimm:$b))]>;
227 //===- Floating-Point Instructions - 4 Operand Form -----------------------===//
228 multiclass PTX_FLOAT_4OP<string opcstr, SDNode opnode1, SDNode opnode2> {
229 def rrr32 : InstPTX<(outs RRegf32:$d),
230 (ins RRegf32:$a, RRegf32:$b, RRegf32:$c),
231 !strconcat(opcstr, ".f32\t$d, $a, $b, $c"),
232 [(set RRegf32:$d, (opnode2 (opnode1 RRegf32:$a,
235 def rri32 : InstPTX<(outs RRegf32:$d),
236 (ins RRegf32:$a, RRegf32:$b, f32imm:$c),
237 !strconcat(opcstr, ".f32\t$d, $a, $b, $c"),
238 [(set RRegf32:$d, (opnode2 (opnode1 RRegf32:$a,
241 def rrr64 : InstPTX<(outs RRegf64:$d),
242 (ins RRegf64:$a, RRegf64:$b, RRegf64:$c),
243 !strconcat(opcstr, ".f64\t$d, $a, $b, $c"),
244 [(set RRegf64:$d, (opnode2 (opnode1 RRegf64:$a,
247 def rri64 : InstPTX<(outs RRegf64:$d),
248 (ins RRegf64:$a, RRegf64:$b, f64imm:$c),
249 !strconcat(opcstr, ".f64\t$d, $a, $b, $c"),
250 [(set RRegf64:$d, (opnode2 (opnode1 RRegf64:$a,
255 multiclass INT3<string opcstr, SDNode opnode> {
256 def rr16 : InstPTX<(outs RRegu16:$d),
257 (ins RRegu16:$a, RRegu16:$b),
258 !strconcat(opcstr, ".u16\t$d, $a, $b"),
259 [(set RRegu16:$d, (opnode RRegu16:$a, RRegu16:$b))]>;
260 def ri16 : InstPTX<(outs RRegu16:$d),
261 (ins RRegu16:$a, i16imm:$b),
262 !strconcat(opcstr, ".u16\t$d, $a, $b"),
263 [(set RRegu16:$d, (opnode RRegu16:$a, imm:$b))]>;
264 def rr32 : InstPTX<(outs RRegu32:$d),
265 (ins RRegu32:$a, RRegu32:$b),
266 !strconcat(opcstr, ".u32\t$d, $a, $b"),
267 [(set RRegu32:$d, (opnode RRegu32:$a, RRegu32:$b))]>;
268 def ri32 : InstPTX<(outs RRegu32:$d),
269 (ins RRegu32:$a, i32imm:$b),
270 !strconcat(opcstr, ".u32\t$d, $a, $b"),
271 [(set RRegu32:$d, (opnode RRegu32:$a, imm:$b))]>;
272 def rr64 : InstPTX<(outs RRegu64:$d),
273 (ins RRegu64:$a, RRegu64:$b),
274 !strconcat(opcstr, ".u64\t$d, $a, $b"),
275 [(set RRegu64:$d, (opnode RRegu64:$a, RRegu64:$b))]>;
276 def ri64 : InstPTX<(outs RRegu64:$d),
277 (ins RRegu64:$a, i64imm:$b),
278 !strconcat(opcstr, ".u64\t$d, $a, $b"),
279 [(set RRegu64:$d, (opnode RRegu64:$a, imm:$b))]>;
282 multiclass PTX_LOGIC<string opcstr, SDNode opnode> {
283 def ripreds : InstPTX<(outs Preds:$d),
284 (ins Preds:$a, i1imm:$b),
285 !strconcat(opcstr, ".pred\t$d, $a, $b"),
286 [(set Preds:$d, (opnode Preds:$a, imm:$b))]>;
287 def rrpreds : InstPTX<(outs Preds:$d),
288 (ins Preds:$a, Preds:$b),
289 !strconcat(opcstr, ".pred\t$d, $a, $b"),
290 [(set Preds:$d, (opnode Preds:$a, Preds:$b))]>;
291 def rr16 : InstPTX<(outs RRegu16:$d),
292 (ins RRegu16:$a, RRegu16:$b),
293 !strconcat(opcstr, ".b16\t$d, $a, $b"),
294 [(set RRegu16:$d, (opnode RRegu16:$a, RRegu16:$b))]>;
295 def ri16 : InstPTX<(outs RRegu16:$d),
296 (ins RRegu16:$a, i16imm:$b),
297 !strconcat(opcstr, ".b16\t$d, $a, $b"),
298 [(set RRegu16:$d, (opnode RRegu16:$a, imm:$b))]>;
299 def rr32 : InstPTX<(outs RRegu32:$d),
300 (ins RRegu32:$a, RRegu32:$b),
301 !strconcat(opcstr, ".b32\t$d, $a, $b"),
302 [(set RRegu32:$d, (opnode RRegu32:$a, RRegu32:$b))]>;
303 def ri32 : InstPTX<(outs RRegu32:$d),
304 (ins RRegu32:$a, i32imm:$b),
305 !strconcat(opcstr, ".b32\t$d, $a, $b"),
306 [(set RRegu32:$d, (opnode RRegu32:$a, imm:$b))]>;
307 def rr64 : InstPTX<(outs RRegu64:$d),
308 (ins RRegu64:$a, RRegu64:$b),
309 !strconcat(opcstr, ".b64\t$d, $a, $b"),
310 [(set RRegu64:$d, (opnode RRegu64:$a, RRegu64:$b))]>;
311 def ri64 : InstPTX<(outs RRegu64:$d),
312 (ins RRegu64:$a, i64imm:$b),
313 !strconcat(opcstr, ".b64\t$d, $a, $b"),
314 [(set RRegu64:$d, (opnode RRegu64:$a, imm:$b))]>;
317 multiclass INT3ntnc<string opcstr, SDNode opnode> {
318 def rr16 : InstPTX<(outs RRegu16:$d),
319 (ins RRegu16:$a, RRegu16:$b),
320 !strconcat(opcstr, "16\t$d, $a, $b"),
321 [(set RRegu16:$d, (opnode RRegu16:$a, RRegu16:$b))]>;
322 def rr32 : InstPTX<(outs RRegu32:$d),
323 (ins RRegu32:$a, RRegu32:$b),
324 !strconcat(opcstr, "32\t$d, $a, $b"),
325 [(set RRegu32:$d, (opnode RRegu32:$a, RRegu32:$b))]>;
326 def rr64 : InstPTX<(outs RRegu64:$d),
327 (ins RRegu64:$a, RRegu64:$b),
328 !strconcat(opcstr, "64\t$d, $a, $b"),
329 [(set RRegu64:$d, (opnode RRegu64:$a, RRegu64:$b))]>;
330 def ri16 : InstPTX<(outs RRegu16:$d),
331 (ins RRegu16:$a, i16imm:$b),
332 !strconcat(opcstr, "16\t$d, $a, $b"),
333 [(set RRegu16:$d, (opnode RRegu16:$a, imm:$b))]>;
334 def ri32 : InstPTX<(outs RRegu32:$d),
335 (ins RRegu32:$a, i32imm:$b),
336 !strconcat(opcstr, "32\t$d, $a, $b"),
337 [(set RRegu32:$d, (opnode RRegu32:$a, imm:$b))]>;
338 def ri64 : InstPTX<(outs RRegu64:$d),
339 (ins RRegu64:$a, i64imm:$b),
340 !strconcat(opcstr, "64\t$d, $a, $b"),
341 [(set RRegu64:$d, (opnode RRegu64:$a, imm:$b))]>;
342 def ir16 : InstPTX<(outs RRegu16:$d),
343 (ins i16imm:$a, RRegu16:$b),
344 !strconcat(opcstr, "16\t$d, $a, $b"),
345 [(set RRegu16:$d, (opnode imm:$a, RRegu16:$b))]>;
346 def ir32 : InstPTX<(outs RRegu32:$d),
347 (ins i32imm:$a, RRegu32:$b),
348 !strconcat(opcstr, "32\t$d, $a, $b"),
349 [(set RRegu32:$d, (opnode imm:$a, RRegu32:$b))]>;
350 def ir64 : InstPTX<(outs RRegu64:$d),
351 (ins i64imm:$a, RRegu64:$b),
352 !strconcat(opcstr, "64\t$d, $a, $b"),
353 [(set RRegu64:$d, (opnode imm:$a, RRegu64:$b))]>;
356 multiclass PTX_SETP_I<RegisterClass RC, string regclsname, Operand immcls,
357 CondCode cmp, string cmpstr> {
358 // TODO support 5-operand format: p|q, a, b, c
361 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b),
362 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
363 [(set Preds:$p, (setcc RC:$a, RC:$b, cmp))]>;
365 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b),
366 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
367 [(set Preds:$p, (setcc RC:$a, imm:$b, cmp))]>;
370 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
371 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, $c"),
372 [(set Preds:$p, (and (setcc RC:$a, RC:$b, cmp), Preds:$c))]>;
374 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b, Preds:$c),
375 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, $c"),
376 [(set Preds:$p, (and (setcc RC:$a, imm:$b, cmp), Preds:$c))]>;
378 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
379 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, $c"),
380 [(set Preds:$p, (or (setcc RC:$a, RC:$b, cmp), Preds:$c))]>;
382 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b, Preds:$c),
383 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, $c"),
384 [(set Preds:$p, (or (setcc RC:$a, imm:$b, cmp), Preds:$c))]>;
386 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
387 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, $c"),
388 [(set Preds:$p, (xor (setcc RC:$a, RC:$b, cmp), Preds:$c))]>;
390 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b, Preds:$c),
391 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, $c"),
392 [(set Preds:$p, (xor (setcc RC:$a, imm:$b, cmp), Preds:$c))]>;
395 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
396 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, !$c"),
397 [(set Preds:$p, (and (setcc RC:$a, RC:$b, cmp), (not Preds:$c)))]>;
399 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b, Preds:$c),
400 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, !$c"),
401 [(set Preds:$p, (and (setcc RC:$a, imm:$b, cmp), (not Preds:$c)))]>;
403 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
404 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, !$c"),
405 [(set Preds:$p, (or (setcc RC:$a, RC:$b, cmp), (not Preds:$c)))]>;
407 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b, Preds:$c),
408 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, !$c"),
409 [(set Preds:$p, (or (setcc RC:$a, imm:$b, cmp), (not Preds:$c)))]>;
411 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
412 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, !$c"),
413 [(set Preds:$p, (xor (setcc RC:$a, RC:$b, cmp), (not Preds:$c)))]>;
415 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b, Preds:$c),
416 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, !$c"),
417 [(set Preds:$p, (xor (setcc RC:$a, imm:$b, cmp), (not Preds:$c)))]>;
420 multiclass PTX_SETP_FP<RegisterClass RC, string regclsname,
421 CondCode ucmp, CondCode ocmp, string cmpstr> {
422 // TODO support 5-operand format: p|q, a, b, c
425 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b),
426 !strconcat("setp.", cmpstr, "u.", regclsname, "\t$p, $a, $b"),
427 [(set Preds:$p, (setcc RC:$a, RC:$b, ucmp))]>;
429 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b),
430 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
431 [(set Preds:$p, (setcc RC:$a, RC:$b, ocmp))]>;
434 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
435 !strconcat("setp.", cmpstr, "u.and.", regclsname, "\t$p, $a, $b, $c"),
436 [(set Preds:$p, (and (setcc RC:$a, RC:$b, ucmp), Preds:$c))]>;
438 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
439 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, $c"),
440 [(set Preds:$p, (and (setcc RC:$a, RC:$b, ocmp), Preds:$c))]>;
443 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
444 !strconcat("setp.", cmpstr, "u.or.", regclsname, "\t$p, $a, $b, $c"),
445 [(set Preds:$p, (or (setcc RC:$a, RC:$b, ucmp), Preds:$c))]>;
447 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
448 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, $c"),
449 [(set Preds:$p, (or (setcc RC:$a, RC:$b, ocmp), Preds:$c))]>;
452 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
453 !strconcat("setp.", cmpstr, "u.xor.", regclsname, "\t$p, $a, $b, $c"),
454 [(set Preds:$p, (xor (setcc RC:$a, RC:$b, ucmp), Preds:$c))]>;
456 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
457 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, $c"),
458 [(set Preds:$p, (xor (setcc RC:$a, RC:$b, ocmp), Preds:$c))]>;
461 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
462 !strconcat("setp.", cmpstr, "u.and.", regclsname, "\t$p, $a, $b, !$c"),
463 [(set Preds:$p, (and (setcc RC:$a, RC:$b, ucmp), (not Preds:$c)))]>;
465 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
466 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, !$c"),
467 [(set Preds:$p, (and (setcc RC:$a, RC:$b, ocmp), (not Preds:$c)))]>;
470 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
471 !strconcat("setp.", cmpstr, "u.or.", regclsname, "\t$p, $a, $b, !$c"),
472 [(set Preds:$p, (or (setcc RC:$a, RC:$b, ucmp), (not Preds:$c)))]>;
474 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
475 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, !$c"),
476 [(set Preds:$p, (or (setcc RC:$a, RC:$b, ocmp), (not Preds:$c)))]>;
479 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
480 !strconcat("setp.", cmpstr, "u.xor.", regclsname, "\t$p, $a, $b, !$c"),
481 [(set Preds:$p, (xor (setcc RC:$a, RC:$b, ucmp), (not Preds:$c)))]>;
483 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
484 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, !$c"),
485 [(set Preds:$p, (xor (setcc RC:$a, RC:$b, ocmp), (not Preds:$c)))]>;
488 multiclass PTX_SELP<RegisterClass RC, string regclsname> {
490 : InstPTX<(outs RC:$r), (ins Preds:$a, RC:$b, RC:$c),
491 !strconcat("selp.", regclsname, "\t$r, $b, $c, $a"),
492 [(set RC:$r, (select Preds:$a, RC:$b, RC:$c))]>;
495 multiclass PTX_LD<string opstr, string typestr, RegisterClass RC, PatFrag pat_load> {
496 def rr32 : InstPTX<(outs RC:$d),
498 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
499 [(set RC:$d, (pat_load ADDRrr32:$a))]>, Requires<[Use32BitAddresses]>;
500 def rr64 : InstPTX<(outs RC:$d),
502 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
503 [(set RC:$d, (pat_load ADDRrr64:$a))]>, Requires<[Use64BitAddresses]>;
504 def ri32 : InstPTX<(outs RC:$d),
506 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
507 [(set RC:$d, (pat_load ADDRri32:$a))]>, Requires<[Use32BitAddresses]>;
508 def ri64 : InstPTX<(outs RC:$d),
510 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
511 [(set RC:$d, (pat_load ADDRri64:$a))]>, Requires<[Use64BitAddresses]>;
512 def ii32 : InstPTX<(outs RC:$d),
514 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
515 [(set RC:$d, (pat_load ADDRii32:$a))]>, Requires<[Use32BitAddresses]>;
516 def ii64 : InstPTX<(outs RC:$d),
518 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
519 [(set RC:$d, (pat_load ADDRii64:$a))]>, Requires<[Use64BitAddresses]>;
522 multiclass PTX_LD_ALL<string opstr, PatFrag pat_load> {
523 defm u16 : PTX_LD<opstr, ".u16", RRegu16, pat_load>;
524 defm u32 : PTX_LD<opstr, ".u32", RRegu32, pat_load>;
525 defm u64 : PTX_LD<opstr, ".u64", RRegu64, pat_load>;
526 defm f32 : PTX_LD<opstr, ".f32", RRegf32, pat_load>;
527 defm f64 : PTX_LD<opstr, ".f64", RRegf64, pat_load>;
530 multiclass PTX_ST<string opstr, string typestr, RegisterClass RC, PatFrag pat_store> {
531 def rr32 : InstPTX<(outs),
532 (ins RC:$d, MEMri32:$a),
533 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
534 [(pat_store RC:$d, ADDRrr32:$a)]>, Requires<[Use32BitAddresses]>;
535 def rr64 : InstPTX<(outs),
536 (ins RC:$d, MEMri64:$a),
537 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
538 [(pat_store RC:$d, ADDRrr64:$a)]>, Requires<[Use64BitAddresses]>;
539 def ri32 : InstPTX<(outs),
540 (ins RC:$d, MEMri32:$a),
541 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
542 [(pat_store RC:$d, ADDRri32:$a)]>, Requires<[Use32BitAddresses]>;
543 def ri64 : InstPTX<(outs),
544 (ins RC:$d, MEMri64:$a),
545 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
546 [(pat_store RC:$d, ADDRri64:$a)]>, Requires<[Use64BitAddresses]>;
547 def ii32 : InstPTX<(outs),
548 (ins RC:$d, MEMii32:$a),
549 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
550 [(pat_store RC:$d, ADDRii32:$a)]>, Requires<[Use32BitAddresses]>;
551 def ii64 : InstPTX<(outs),
552 (ins RC:$d, MEMii64:$a),
553 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
554 [(pat_store RC:$d, ADDRii64:$a)]>, Requires<[Use64BitAddresses]>;
557 multiclass PTX_ST_ALL<string opstr, PatFrag pat_store> {
558 defm u16 : PTX_ST<opstr, ".u16", RRegu16, pat_store>;
559 defm u32 : PTX_ST<opstr, ".u32", RRegu32, pat_store>;
560 defm u64 : PTX_ST<opstr, ".u64", RRegu64, pat_store>;
561 defm f32 : PTX_ST<opstr, ".f32", RRegf32, pat_store>;
562 defm f64 : PTX_ST<opstr, ".f64", RRegf64, pat_store>;
565 //===----------------------------------------------------------------------===//
567 //===----------------------------------------------------------------------===//
569 ///===- Integer Arithmetic Instructions -----------------------------------===//
571 defm ADD : INT3<"add", add>;
572 defm SUB : INT3<"sub", sub>;
573 defm MUL : INT3<"mul.lo", mul>; // FIXME: Allow 32x32 -> 64 multiplies
574 defm DIV : INT3<"div", udiv>;
575 defm REM : INT3<"rem", urem>;
577 ///===- Floating-Point Arithmetic Instructions ----------------------------===//
579 // Standard Unary Operations
580 defm FNEG : PTX_FLOAT_2OP<"neg", fneg>;
582 // Standard Binary Operations
583 defm FADD : PTX_FLOAT_3OP<"add", fadd>;
584 defm FSUB : PTX_FLOAT_3OP<"sub", fsub>;
585 defm FMUL : PTX_FLOAT_3OP<"mul", fmul>;
587 // TODO: Allow user selection of rounding modes for fdiv.
588 // For division, we need to have f32 and f64 differently.
589 // For f32, we just always use .approx since it is supported on all hardware
590 // for PTX 1.4+, which is our minimum target.
591 def FDIVrr32 : InstPTX<(outs RRegf32:$d),
592 (ins RRegf32:$a, RRegf32:$b),
593 "div.approx.f32\t$d, $a, $b",
594 [(set RRegf32:$d, (fdiv RRegf32:$a, RRegf32:$b))]>;
595 def FDIVri32 : InstPTX<(outs RRegf32:$d),
596 (ins RRegf32:$a, f32imm:$b),
597 "div.approx.f32\t$d, $a, $b",
598 [(set RRegf32:$d, (fdiv RRegf32:$a, fpimm:$b))]>;
600 // For f64, we must specify a rounding for sm 1.3+ but *not* for sm 1.0.
601 def FDIVrr64SM13 : InstPTX<(outs RRegf64:$d),
602 (ins RRegf64:$a, RRegf64:$b),
603 "div.rn.f64\t$d, $a, $b",
604 [(set RRegf64:$d, (fdiv RRegf64:$a, RRegf64:$b))]>,
605 Requires<[SupportsSM13]>;
606 def FDIVri64SM13 : InstPTX<(outs RRegf64:$d),
607 (ins RRegf64:$a, f64imm:$b),
608 "div.rn.f64\t$d, $a, $b",
609 [(set RRegf64:$d, (fdiv RRegf64:$a, fpimm:$b))]>,
610 Requires<[SupportsSM13]>;
611 def FDIVrr64SM10 : InstPTX<(outs RRegf64:$d),
612 (ins RRegf64:$a, RRegf64:$b),
613 "div.f64\t$d, $a, $b",
614 [(set RRegf64:$d, (fdiv RRegf64:$a, RRegf64:$b))]>,
615 Requires<[DoesNotSupportSM13]>;
616 def FDIVri64SM10 : InstPTX<(outs RRegf64:$d),
617 (ins RRegf64:$a, f64imm:$b),
618 "div.f64\t$d, $a, $b",
619 [(set RRegf64:$d, (fdiv RRegf64:$a, fpimm:$b))]>,
620 Requires<[DoesNotSupportSM13]>;
624 // Multi-operation hybrid instructions
626 // The selection of mad/fma is tricky. In some cases, they are the *same*
627 // instruction, but in other cases we may prefer one or the other. Also,
628 // different PTX versions differ on whether rounding mode flags are required.
629 // In the short term, mad is supported on all PTX versions and we use a
630 // default rounding mode no matter what shader model or PTX version.
631 // TODO: Allow the rounding mode to be selectable through llc.
632 defm FMADSM13 : PTX_FLOAT_4OP<"mad.rn", fmul, fadd>, Requires<[SupportsSM13]>;
633 defm FMAD : PTX_FLOAT_4OP<"mad", fmul, fadd>, Requires<[DoesNotSupportSM13]>;
635 ///===- Floating-Point Intrinsic Instructions -----------------------------===//
637 def FSQRT32 : InstPTX<(outs RRegf32:$d),
639 "sqrt.rn.f32\t$d, $a",
640 [(set RRegf32:$d, (fsqrt RRegf32:$a))]>;
642 def FSQRT64 : InstPTX<(outs RRegf64:$d),
644 "sqrt.rn.f64\t$d, $a",
645 [(set RRegf64:$d, (fsqrt RRegf64:$a))]>;
647 def FSIN32 : InstPTX<(outs RRegf32:$d),
649 "sin.approx.f32\t$d, $a",
650 [(set RRegf32:$d, (fsin RRegf32:$a))]>;
652 def FSIN64 : InstPTX<(outs RRegf64:$d),
654 "sin.approx.f64\t$d, $a",
655 [(set RRegf64:$d, (fsin RRegf64:$a))]>;
657 def FCOS32 : InstPTX<(outs RRegf32:$d),
659 "cos.approx.f32\t$d, $a",
660 [(set RRegf32:$d, (fcos RRegf32:$a))]>;
662 def FCOS64 : InstPTX<(outs RRegf64:$d),
664 "cos.approx.f64\t$d, $a",
665 [(set RRegf64:$d, (fcos RRegf64:$a))]>;
668 ///===- Comparison and Selection Instructions -----------------------------===//
672 defm SETPEQu16 : PTX_SETP_I<RRegu16, "u16", i16imm, SETEQ, "eq">;
673 defm SETPNEu16 : PTX_SETP_I<RRegu16, "u16", i16imm, SETNE, "ne">;
674 defm SETPLTu16 : PTX_SETP_I<RRegu16, "u16", i16imm, SETULT, "lt">;
675 defm SETPLEu16 : PTX_SETP_I<RRegu16, "u16", i16imm, SETULE, "le">;
676 defm SETPGTu16 : PTX_SETP_I<RRegu16, "u16", i16imm, SETUGT, "gt">;
677 defm SETPGEu16 : PTX_SETP_I<RRegu16, "u16", i16imm, SETUGE, "ge">;
681 defm SETPEQu32 : PTX_SETP_I<RRegu32, "u32", i32imm, SETEQ, "eq">;
682 defm SETPNEu32 : PTX_SETP_I<RRegu32, "u32", i32imm, SETNE, "ne">;
683 defm SETPLTu32 : PTX_SETP_I<RRegu32, "u32", i32imm, SETULT, "lt">;
684 defm SETPLEu32 : PTX_SETP_I<RRegu32, "u32", i32imm, SETULE, "le">;
685 defm SETPGTu32 : PTX_SETP_I<RRegu32, "u32", i32imm, SETUGT, "gt">;
686 defm SETPGEu32 : PTX_SETP_I<RRegu32, "u32", i32imm, SETUGE, "ge">;
690 defm SETPEQu64 : PTX_SETP_I<RRegu64, "u64", i64imm, SETEQ, "eq">;
691 defm SETPNEu64 : PTX_SETP_I<RRegu64, "u64", i64imm, SETNE, "ne">;
692 defm SETPLTu64 : PTX_SETP_I<RRegu64, "u64", i64imm, SETULT, "lt">;
693 defm SETPLEu64 : PTX_SETP_I<RRegu64, "u64", i64imm, SETULE, "le">;
694 defm SETPGTu64 : PTX_SETP_I<RRegu64, "u64", i64imm, SETUGT, "gt">;
695 defm SETPGEu64 : PTX_SETP_I<RRegu64, "u64", i64imm, SETUGE, "ge">;
699 defm SETPEQf32 : PTX_SETP_FP<RRegf32, "f32", SETUEQ, SETOEQ, "eq">;
700 defm SETPNEf32 : PTX_SETP_FP<RRegf32, "f32", SETUNE, SETONE, "ne">;
701 defm SETPLTf32 : PTX_SETP_FP<RRegf32, "f32", SETULT, SETOLT, "lt">;
702 defm SETPLEf32 : PTX_SETP_FP<RRegf32, "f32", SETULE, SETOLE, "le">;
703 defm SETPGTf32 : PTX_SETP_FP<RRegf32, "f32", SETUGT, SETOGT, "gt">;
704 defm SETPGEf32 : PTX_SETP_FP<RRegf32, "f32", SETUGE, SETOGE, "ge">;
708 defm SETPEQf64 : PTX_SETP_FP<RRegf64, "f64", SETUEQ, SETOEQ, "eq">;
709 defm SETPNEf64 : PTX_SETP_FP<RRegf64, "f64", SETUNE, SETONE, "ne">;
710 defm SETPLTf64 : PTX_SETP_FP<RRegf64, "f64", SETULT, SETOLT, "lt">;
711 defm SETPLEf64 : PTX_SETP_FP<RRegf64, "f64", SETULE, SETOLE, "le">;
712 defm SETPGTf64 : PTX_SETP_FP<RRegf64, "f64", SETUGT, SETOGT, "gt">;
713 defm SETPGEf64 : PTX_SETP_FP<RRegf64, "f64", SETUGE, SETOGE, "ge">;
717 defm PTX_SELPu16 : PTX_SELP<RRegu16, "u16">;
718 defm PTX_SELPu32 : PTX_SELP<RRegu32, "u32">;
719 defm PTX_SELPu64 : PTX_SELP<RRegu64, "u64">;
720 defm PTX_SELPf32 : PTX_SELP<RRegf32, "f32">;
721 defm PTX_SELPf64 : PTX_SELP<RRegf64, "f64">;
723 ///===- Logic and Shift Instructions --------------------------------------===//
725 defm SHL : INT3ntnc<"shl.b", PTXshl>;
726 defm SRL : INT3ntnc<"shr.u", PTXsrl>;
727 defm SRA : INT3ntnc<"shr.s", PTXsra>;
729 defm AND : PTX_LOGIC<"and", and>;
730 defm OR : PTX_LOGIC<"or", or>;
731 defm XOR : PTX_LOGIC<"xor", xor>;
733 ///===- Data Movement and Conversion Instructions -------------------------===//
735 let neverHasSideEffects = 1 in {
737 : InstPTX<(outs Preds:$d), (ins Preds:$a), "mov.pred\t$d, $a", []>;
739 : InstPTX<(outs RRegu16:$d), (ins RRegu16:$a), "mov.u16\t$d, $a", []>;
741 : InstPTX<(outs RRegu32:$d), (ins RRegu32:$a), "mov.u32\t$d, $a", []>;
743 : InstPTX<(outs RRegu64:$d), (ins RRegu64:$a), "mov.u64\t$d, $a", []>;
745 : InstPTX<(outs RRegf32:$d), (ins RRegf32:$a), "mov.f32\t$d, $a", []>;
747 : InstPTX<(outs RRegf64:$d), (ins RRegf64:$a), "mov.f64\t$d, $a", []>;
750 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
752 : InstPTX<(outs Preds:$d), (ins i1imm:$a), "mov.pred\t$d, $a",
753 [(set Preds:$d, imm:$a)]>;
755 : InstPTX<(outs RRegu16:$d), (ins i16imm:$a), "mov.u16\t$d, $a",
756 [(set RRegu16:$d, imm:$a)]>;
758 : InstPTX<(outs RRegu32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
759 [(set RRegu32:$d, imm:$a)]>;
761 : InstPTX<(outs RRegu64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
762 [(set RRegu64:$d, imm:$a)]>;
764 : InstPTX<(outs RRegf32:$d), (ins f32imm:$a), "mov.f32\t$d, $a",
765 [(set RRegf32:$d, fpimm:$a)]>;
767 : InstPTX<(outs RRegf64:$d), (ins f64imm:$a), "mov.f64\t$d, $a",
768 [(set RRegf64:$d, fpimm:$a)]>;
771 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
773 : InstPTX<(outs RRegu32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
774 [(set RRegu32:$d, (PTXcopyaddress tglobaladdr:$a))]>;
776 : InstPTX<(outs RRegu64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
777 [(set RRegu64:$d, (PTXcopyaddress tglobaladdr:$a))]>;
781 defm LDg : PTX_LD_ALL<"ld.global", load_global>;
782 defm LDc : PTX_LD_ALL<"ld.const", load_constant>;
783 defm LDl : PTX_LD_ALL<"ld.local", load_local>;
784 defm LDs : PTX_LD_ALL<"ld.shared", load_shared>;
786 // This is a special instruction that is manually inserted for kernel parameters
787 def LDpiU16 : InstPTX<(outs RRegu16:$d), (ins MEMpi:$a),
788 "ld.param.u16\t$d, [$a]", []>;
789 def LDpiU32 : InstPTX<(outs RRegu32:$d), (ins MEMpi:$a),
790 "ld.param.u32\t$d, [$a]", []>;
791 def LDpiU64 : InstPTX<(outs RRegu64:$d), (ins MEMpi:$a),
792 "ld.param.u64\t$d, [$a]", []>;
793 def LDpiF32 : InstPTX<(outs RRegf32:$d), (ins MEMpi:$a),
794 "ld.param.f32\t$d, [$a]", []>;
795 def LDpiF64 : InstPTX<(outs RRegf64:$d), (ins MEMpi:$a),
796 "ld.param.f64\t$d, [$a]", []>;
799 defm STg : PTX_ST_ALL<"st.global", store_global>;
800 defm STl : PTX_ST_ALL<"st.local", store_local>;
801 defm STs : PTX_ST_ALL<"st.shared", store_shared>;
803 // defm STp : PTX_ST_ALL<"st.param", store_parameter>;
804 // defm LDp : PTX_LD_ALL<"ld.param", load_parameter>;
805 // TODO: Do something with st.param if/when it is needed.
807 // Conversion to pred
810 : InstPTX<(outs Preds:$d), (ins RRegu16:$a), "cvt.pred.u16\t$d, $a",
811 [(set Preds:$d, (trunc RRegu16:$a))]>;
814 : InstPTX<(outs Preds:$d), (ins RRegu32:$a), "cvt.pred.u32\t$d, $a",
815 [(set Preds:$d, (trunc RRegu32:$a))]>;
818 : InstPTX<(outs Preds:$d), (ins RRegu64:$a), "cvt.pred.u64\t$d, $a",
819 [(set Preds:$d, (trunc RRegu64:$a))]>;
822 : InstPTX<(outs Preds:$d), (ins RRegf32:$a), "cvt.rni.pred.f32\t$d, $a",
823 [(set Preds:$d, (fp_to_uint RRegf32:$a))]>;
826 : InstPTX<(outs Preds:$d), (ins RRegf64:$a), "cvt.rni.pred.f64\t$d, $a",
827 [(set Preds:$d, (fp_to_uint RRegf64:$a))]>;
832 : InstPTX<(outs RRegu16:$d), (ins Preds:$a), "cvt.u16.pred\t$d, $a",
833 [(set RRegu16:$d, (zext Preds:$a))]>;
836 : InstPTX<(outs RRegu16:$d), (ins RRegu32:$a), "cvt.u16.u32\t$d, $a",
837 [(set RRegu16:$d, (trunc RRegu32:$a))]>;
840 : InstPTX<(outs RRegu16:$d), (ins RRegu64:$a), "cvt.u16.u64\t$d, $a",
841 [(set RRegu16:$d, (trunc RRegu64:$a))]>;
844 : InstPTX<(outs RRegu16:$d), (ins RRegf32:$a), "cvt.rni.u16.f32\t$d, $a",
845 [(set RRegu16:$d, (fp_to_uint RRegf32:$a))]>;
848 : InstPTX<(outs RRegu16:$d), (ins RRegf64:$a), "cvt.rni.u16.f64\t$d, $a",
849 [(set RRegu16:$d, (fp_to_uint RRegf64:$a))]>;
854 : InstPTX<(outs RRegu32:$d), (ins Preds:$a), "cvt.u32.pred\t$d, $a",
855 [(set RRegu32:$d, (zext Preds:$a))]>;
858 : InstPTX<(outs RRegu32:$d), (ins RRegu16:$a), "cvt.u32.u16\t$d, $a",
859 [(set RRegu32:$d, (zext RRegu16:$a))]>;
862 : InstPTX<(outs RRegu32:$d), (ins RRegu64:$a), "cvt.u32.u64\t$d, $a",
863 [(set RRegu32:$d, (trunc RRegu64:$a))]>;
866 : InstPTX<(outs RRegu32:$d), (ins RRegf32:$a), "cvt.rni.u32.f32\t$d, $a",
867 [(set RRegu32:$d, (fp_to_uint RRegf32:$a))]>;
870 : InstPTX<(outs RRegu32:$d), (ins RRegf64:$a), "cvt.rni.u32.f64\t$d, $a",
871 [(set RRegu32:$d, (fp_to_uint RRegf64:$a))]>;
876 : InstPTX<(outs RRegu64:$d), (ins Preds:$a), "cvt.u64.pred\t$d, $a",
877 [(set RRegu64:$d, (zext Preds:$a))]>;
880 : InstPTX<(outs RRegu64:$d), (ins RRegu16:$a), "cvt.u64.u16\t$d, $a",
881 [(set RRegu64:$d, (zext RRegu16:$a))]>;
884 : InstPTX<(outs RRegu64:$d), (ins RRegu32:$a), "cvt.u64.u32\t$d, $a",
885 [(set RRegu64:$d, (zext RRegu32:$a))]>;
888 : InstPTX<(outs RRegu64:$d), (ins RRegf32:$a), "cvt.rni.u64.f32\t$d, $a",
889 [(set RRegu64:$d, (fp_to_uint RRegf32:$a))]>;
892 : InstPTX<(outs RRegu64:$d), (ins RRegf64:$a), "cvt.rni.u64.f64\t$d, $a",
893 [(set RRegu64:$d, (fp_to_uint RRegf64:$a))]>;
898 : InstPTX<(outs RRegf32:$d), (ins Preds:$a), "cvt.rn.f32.pred\t$d, $a",
899 [(set RRegf32:$d, (uint_to_fp Preds:$a))]>;
902 : InstPTX<(outs RRegf32:$d), (ins RRegu16:$a), "cvt.rn.f32.u16\t$d, $a",
903 [(set RRegf32:$d, (uint_to_fp RRegu16:$a))]>;
906 : InstPTX<(outs RRegf32:$d), (ins RRegu32:$a), "cvt.rn.f32.u32\t$d, $a",
907 [(set RRegf32:$d, (uint_to_fp RRegu32:$a))]>;
910 : InstPTX<(outs RRegf32:$d), (ins RRegu64:$a), "cvt.rn.f32.u64\t$d, $a",
911 [(set RRegf32:$d, (uint_to_fp RRegu64:$a))]>;
914 : InstPTX<(outs RRegf32:$d), (ins RRegf64:$a), "cvt.rn.f32.f64\t$d, $a",
915 [(set RRegf32:$d, (fround RRegf64:$a))]>;
920 : InstPTX<(outs RRegf64:$d), (ins Preds:$a), "cvt.rn.f64.pred\t$d, $a",
921 [(set RRegf64:$d, (uint_to_fp Preds:$a))]>;
924 : InstPTX<(outs RRegf64:$d), (ins RRegu16:$a), "cvt.rn.f64.u16\t$d, $a",
925 [(set RRegf64:$d, (uint_to_fp RRegu16:$a))]>;
928 : InstPTX<(outs RRegf64:$d), (ins RRegu32:$a), "cvt.rn.f64.u32\t$d, $a",
929 [(set RRegf64:$d, (uint_to_fp RRegu32:$a))]>;
932 : InstPTX<(outs RRegf64:$d), (ins RRegu64:$a), "cvt.rn.f64.u64\t$d, $a",
933 [(set RRegf64:$d, (uint_to_fp RRegu64:$a))]>;
936 : InstPTX<(outs RRegf64:$d), (ins RRegf32:$a), "cvt.f64.f32\t$d, $a",
937 [(set RRegf64:$d, (fextend RRegf32:$a))]>;
939 ///===- Control Flow Instructions -----------------------------------------===//
941 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
943 : InstPTX<(outs), (ins brtarget:$d), "bra\t$d", [(br bb:$d)]>;
946 let isBranch = 1, isTerminator = 1 in {
947 // FIXME: The pattern part is blank because I cannot (or do not yet know
948 // how to) use the first operand of PredicateOperand (a Preds register) here
950 : InstPTX<(outs), (ins brtarget:$d), "bra\t$d",
951 [/*(brcond pred:$_p, bb:$d)*/]>;
954 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
955 def EXIT : InstPTX<(outs), (ins), "exit", [(PTXexit)]>;
956 def RET : InstPTX<(outs), (ins), "ret", [(PTXret)]>;
959 ///===- Intrinsic Instructions --------------------------------------------===//
961 include "PTXIntrinsicInstrInfo.td"