1 //===- PTXInstrInfo.td - PTX Instruction defs -----------------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PTX instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "PTXInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Code Generation Predicates
22 //===----------------------------------------------------------------------===//
25 def Use32BitAddresses : Predicate<"!getSubtarget().use64BitAddresses()">;
26 def Use64BitAddresses : Predicate<"getSubtarget().use64BitAddresses()">;
28 // Shader Model Support
29 def SupportsSM13 : Predicate<"getSubtarget().supportsSM13()">;
30 def DoesNotSupportSM13 : Predicate<"!getSubtarget().supportsSM13()">;
31 def SupportsSM20 : Predicate<"getSubtarget().supportsSM20()">;
32 def DoesNotSupportSM20 : Predicate<"!getSubtarget().supportsSM20()">;
34 // PTX Version Support
35 def SupportsPTX21 : Predicate<"getSubtarget().supportsPTX21()">;
36 def DoesNotSupportPTX21 : Predicate<"!getSubtarget().supportsPTX21()">;
37 def SupportsPTX22 : Predicate<"getSubtarget().supportsPTX22()">;
38 def DoesNotSupportPTX22 : Predicate<"!getSubtarget().supportsPTX22()">;
40 //===----------------------------------------------------------------------===//
41 // Instruction Pattern Stuff
42 //===----------------------------------------------------------------------===//
44 def load_global : PatFrag<(ops node:$ptr), (load node:$ptr), [{
46 const PointerType *PT;
47 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
48 (PT = dyn_cast<PointerType>(Src->getType())))
49 return PT->getAddressSpace() == PTX::GLOBAL;
53 def load_constant : PatFrag<(ops node:$ptr), (load node:$ptr), [{
55 const PointerType *PT;
56 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
57 (PT = dyn_cast<PointerType>(Src->getType())))
58 return PT->getAddressSpace() == PTX::CONSTANT;
62 def load_local : PatFrag<(ops node:$ptr), (load node:$ptr), [{
64 const PointerType *PT;
65 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
66 (PT = dyn_cast<PointerType>(Src->getType())))
67 return PT->getAddressSpace() == PTX::LOCAL;
71 def load_parameter : PatFrag<(ops node:$ptr), (load node:$ptr), [{
73 const PointerType *PT;
74 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
75 (PT = dyn_cast<PointerType>(Src->getType())))
76 return PT->getAddressSpace() == PTX::PARAMETER;
80 def load_shared : PatFrag<(ops node:$ptr), (load node:$ptr), [{
82 const PointerType *PT;
83 if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
84 (PT = dyn_cast<PointerType>(Src->getType())))
85 return PT->getAddressSpace() == PTX::SHARED;
90 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
92 const PointerType *PT;
93 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
94 (PT = dyn_cast<PointerType>(Src->getType())))
95 return PT->getAddressSpace() == PTX::GLOBAL;
100 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
102 const PointerType *PT;
103 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
104 (PT = dyn_cast<PointerType>(Src->getType())))
105 return PT->getAddressSpace() == PTX::LOCAL;
110 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
112 const PointerType *PT;
113 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
114 (PT = dyn_cast<PointerType>(Src->getType())))
115 return PT->getAddressSpace() == PTX::PARAMETER;
120 : PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
122 const PointerType *PT;
123 if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
124 (PT = dyn_cast<PointerType>(Src->getType())))
125 return PT->getAddressSpace() == PTX::SHARED;
130 def ADDRrr32 : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
131 def ADDRrr64 : ComplexPattern<i64, 2, "SelectADDRrr", [], []>;
132 def ADDRri32 : ComplexPattern<i32, 2, "SelectADDRri", [], []>;
133 def ADDRri64 : ComplexPattern<i64, 2, "SelectADDRri", [], []>;
134 def ADDRii32 : ComplexPattern<i32, 2, "SelectADDRii", [], []>;
135 def ADDRii64 : ComplexPattern<i64, 2, "SelectADDRii", [], []>;
138 def MEMri32 : Operand<i32> {
139 let PrintMethod = "printMemOperand";
140 let MIOperandInfo = (ops RRegu32, i32imm);
142 def MEMri64 : Operand<i64> {
143 let PrintMethod = "printMemOperand";
144 let MIOperandInfo = (ops RRegu64, i64imm);
146 def MEMii32 : Operand<i32> {
147 let PrintMethod = "printMemOperand";
148 let MIOperandInfo = (ops i32imm, i32imm);
150 def MEMii64 : Operand<i64> {
151 let PrintMethod = "printMemOperand";
152 let MIOperandInfo = (ops i64imm, i64imm);
154 // The operand here does not correspond to an actual address, so we
155 // can use i32 in 64-bit address modes.
156 def MEMpi : Operand<i32> {
157 let PrintMethod = "printParamOperand";
158 let MIOperandInfo = (ops i32imm);
161 // Branch & call targets have OtherVT type.
162 def brtarget : Operand<OtherVT>;
163 def calltarget : Operand<i32>;
165 //===----------------------------------------------------------------------===//
166 // PTX Specific Node Definitions
167 //===----------------------------------------------------------------------===//
169 // PTX allow generic 3-reg shifts like shl r0, r1, r2
170 def PTXshl : SDNode<"ISD::SHL", SDTIntBinOp>;
171 def PTXsrl : SDNode<"ISD::SRL", SDTIntBinOp>;
172 def PTXsra : SDNode<"ISD::SRA", SDTIntBinOp>;
175 : SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>;
177 : SDNode<"PTXISD::RET", SDTNone, [SDNPHasChain]>;
179 : SDNode<"PTXISD::COPY_ADDRESS", SDTypeProfile<1, 1, []>, []>;
181 //===----------------------------------------------------------------------===//
182 // Instruction Class Templates
183 //===----------------------------------------------------------------------===//
185 //===- Floating-Point Instructions - 3 Operand Form -----------------------===//
186 multiclass PTX_FLOAT_3OP<string opcstr, SDNode opnode> {
187 def rr32 : InstPTX<(outs RRegf32:$d),
188 (ins RRegf32:$a, RRegf32:$b),
189 !strconcat(opcstr, ".f32\t$d, $a, $b"),
190 [(set RRegf32:$d, (opnode RRegf32:$a, RRegf32:$b))]>;
191 def ri32 : InstPTX<(outs RRegf32:$d),
192 (ins RRegf32:$a, f32imm:$b),
193 !strconcat(opcstr, ".f32\t$d, $a, $b"),
194 [(set RRegf32:$d, (opnode RRegf32:$a, fpimm:$b))]>;
195 def rr64 : InstPTX<(outs RRegf64:$d),
196 (ins RRegf64:$a, RRegf64:$b),
197 !strconcat(opcstr, ".f64\t$d, $a, $b"),
198 [(set RRegf64:$d, (opnode RRegf64:$a, RRegf64:$b))]>;
199 def ri64 : InstPTX<(outs RRegf64:$d),
200 (ins RRegf64:$a, f64imm:$b),
201 !strconcat(opcstr, ".f64\t$d, $a, $b"),
202 [(set RRegf64:$d, (opnode RRegf64:$a, fpimm:$b))]>;
205 //===- Floating-Point Instructions - 4 Operand Form -----------------------===//
206 multiclass PTX_FLOAT_4OP<string opcstr, SDNode opnode1, SDNode opnode2> {
207 def rrr32 : InstPTX<(outs RRegf32:$d),
208 (ins RRegf32:$a, RRegf32:$b, RRegf32:$c),
209 !strconcat(opcstr, ".f32\t$d, $a, $b, $c"),
210 [(set RRegf32:$d, (opnode2 (opnode1 RRegf32:$a,
213 def rri32 : InstPTX<(outs RRegf32:$d),
214 (ins RRegf32:$a, RRegf32:$b, f32imm:$c),
215 !strconcat(opcstr, ".f32\t$d, $a, $b, $c"),
216 [(set RRegf32:$d, (opnode2 (opnode1 RRegf32:$a,
219 def rrr64 : InstPTX<(outs RRegf64:$d),
220 (ins RRegf64:$a, RRegf64:$b, RRegf64:$c),
221 !strconcat(opcstr, ".f64\t$d, $a, $b, $c"),
222 [(set RRegf64:$d, (opnode2 (opnode1 RRegf64:$a,
225 def rri64 : InstPTX<(outs RRegf64:$d),
226 (ins RRegf64:$a, RRegf64:$b, f64imm:$c),
227 !strconcat(opcstr, ".f64\t$d, $a, $b, $c"),
228 [(set RRegf64:$d, (opnode2 (opnode1 RRegf64:$a,
233 multiclass INT3<string opcstr, SDNode opnode> {
234 def rr16 : InstPTX<(outs RRegu16:$d),
235 (ins RRegu16:$a, RRegu16:$b),
236 !strconcat(opcstr, ".u16\t$d, $a, $b"),
237 [(set RRegu16:$d, (opnode RRegu16:$a, RRegu16:$b))]>;
238 def ri16 : InstPTX<(outs RRegu16:$d),
239 (ins RRegu16:$a, i16imm:$b),
240 !strconcat(opcstr, ".u16\t$d, $a, $b"),
241 [(set RRegu16:$d, (opnode RRegu16:$a, imm:$b))]>;
242 def rr32 : InstPTX<(outs RRegu32:$d),
243 (ins RRegu32:$a, RRegu32:$b),
244 !strconcat(opcstr, ".u32\t$d, $a, $b"),
245 [(set RRegu32:$d, (opnode RRegu32:$a, RRegu32:$b))]>;
246 def ri32 : InstPTX<(outs RRegu32:$d),
247 (ins RRegu32:$a, i32imm:$b),
248 !strconcat(opcstr, ".u32\t$d, $a, $b"),
249 [(set RRegu32:$d, (opnode RRegu32:$a, imm:$b))]>;
250 def rr64 : InstPTX<(outs RRegu64:$d),
251 (ins RRegu64:$a, RRegu64:$b),
252 !strconcat(opcstr, ".u64\t$d, $a, $b"),
253 [(set RRegu64:$d, (opnode RRegu64:$a, RRegu64:$b))]>;
254 def ri64 : InstPTX<(outs RRegu64:$d),
255 (ins RRegu64:$a, i64imm:$b),
256 !strconcat(opcstr, ".u64\t$d, $a, $b"),
257 [(set RRegu64:$d, (opnode RRegu64:$a, imm:$b))]>;
260 multiclass PTX_LOGIC<string opcstr, SDNode opnode> {
261 def rr16 : InstPTX<(outs RRegu16:$d),
262 (ins RRegu16:$a, RRegu16:$b),
263 !strconcat(opcstr, ".b16\t$d, $a, $b"),
264 [(set RRegu16:$d, (opnode RRegu16:$a, RRegu16:$b))]>;
265 def ri16 : InstPTX<(outs RRegu16:$d),
266 (ins RRegu16:$a, i16imm:$b),
267 !strconcat(opcstr, ".b16\t$d, $a, $b"),
268 [(set RRegu16:$d, (opnode RRegu16:$a, imm:$b))]>;
269 def rr32 : InstPTX<(outs RRegu32:$d),
270 (ins RRegu32:$a, RRegu32:$b),
271 !strconcat(opcstr, ".b32\t$d, $a, $b"),
272 [(set RRegu32:$d, (opnode RRegu32:$a, RRegu32:$b))]>;
273 def ri32 : InstPTX<(outs RRegu32:$d),
274 (ins RRegu32:$a, i32imm:$b),
275 !strconcat(opcstr, ".b32\t$d, $a, $b"),
276 [(set RRegu32:$d, (opnode RRegu32:$a, imm:$b))]>;
277 def rr64 : InstPTX<(outs RRegu64:$d),
278 (ins RRegu64:$a, RRegu64:$b),
279 !strconcat(opcstr, ".b64\t$d, $a, $b"),
280 [(set RRegu64:$d, (opnode RRegu64:$a, RRegu64:$b))]>;
281 def ri64 : InstPTX<(outs RRegu64:$d),
282 (ins RRegu64:$a, i64imm:$b),
283 !strconcat(opcstr, ".b64\t$d, $a, $b"),
284 [(set RRegu64:$d, (opnode RRegu64:$a, imm:$b))]>;
287 multiclass INT3ntnc<string opcstr, SDNode opnode> {
288 def rr16 : InstPTX<(outs RRegu16:$d),
289 (ins RRegu16:$a, RRegu16:$b),
290 !strconcat(opcstr, "16\t$d, $a, $b"),
291 [(set RRegu16:$d, (opnode RRegu16:$a, RRegu16:$b))]>;
292 def rr32 : InstPTX<(outs RRegu32:$d),
293 (ins RRegu32:$a, RRegu32:$b),
294 !strconcat(opcstr, "32\t$d, $a, $b"),
295 [(set RRegu32:$d, (opnode RRegu32:$a, RRegu32:$b))]>;
296 def rr64 : InstPTX<(outs RRegu64:$d),
297 (ins RRegu64:$a, RRegu64:$b),
298 !strconcat(opcstr, "64\t$d, $a, $b"),
299 [(set RRegu64:$d, (opnode RRegu64:$a, RRegu64:$b))]>;
300 def ri16 : InstPTX<(outs RRegu16:$d),
301 (ins RRegu16:$a, i16imm:$b),
302 !strconcat(opcstr, "16\t$d, $a, $b"),
303 [(set RRegu16:$d, (opnode RRegu16:$a, imm:$b))]>;
304 def ri32 : InstPTX<(outs RRegu32:$d),
305 (ins RRegu32:$a, i32imm:$b),
306 !strconcat(opcstr, "32\t$d, $a, $b"),
307 [(set RRegu32:$d, (opnode RRegu32:$a, imm:$b))]>;
308 def ri64 : InstPTX<(outs RRegu64:$d),
309 (ins RRegu64:$a, i64imm:$b),
310 !strconcat(opcstr, "64\t$d, $a, $b"),
311 [(set RRegu64:$d, (opnode RRegu64:$a, imm:$b))]>;
312 def ir16 : InstPTX<(outs RRegu16:$d),
313 (ins i16imm:$a, RRegu16:$b),
314 !strconcat(opcstr, "16\t$d, $a, $b"),
315 [(set RRegu16:$d, (opnode imm:$a, RRegu16:$b))]>;
316 def ir32 : InstPTX<(outs RRegu32:$d),
317 (ins i32imm:$a, RRegu32:$b),
318 !strconcat(opcstr, "32\t$d, $a, $b"),
319 [(set RRegu32:$d, (opnode imm:$a, RRegu32:$b))]>;
320 def ir64 : InstPTX<(outs RRegu64:$d),
321 (ins i64imm:$a, RRegu64:$b),
322 !strconcat(opcstr, "64\t$d, $a, $b"),
323 [(set RRegu64:$d, (opnode imm:$a, RRegu64:$b))]>;
326 multiclass PTX_SETP_I<RegisterClass RC, string regclsname, Operand immcls,
327 CondCode cmp, string cmpstr> {
328 // TODO support 5-operand format: p|q, a, b, c
331 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b),
332 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
333 [(set Preds:$p, (setcc RC:$a, RC:$b, cmp))]>;
335 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b),
336 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
337 [(set Preds:$p, (setcc RC:$a, imm:$b, cmp))]>;
340 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
341 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, $c"),
342 [(set Preds:$p, (and (setcc RC:$a, RC:$b, cmp), Preds:$c))]>;
344 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b, Preds:$c),
345 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, $c"),
346 [(set Preds:$p, (and (setcc RC:$a, imm:$b, cmp), Preds:$c))]>;
348 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
349 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, $c"),
350 [(set Preds:$p, (or (setcc RC:$a, RC:$b, cmp), Preds:$c))]>;
352 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b, Preds:$c),
353 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, $c"),
354 [(set Preds:$p, (or (setcc RC:$a, imm:$b, cmp), Preds:$c))]>;
356 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
357 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, $c"),
358 [(set Preds:$p, (xor (setcc RC:$a, RC:$b, cmp), Preds:$c))]>;
360 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b, Preds:$c),
361 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, $c"),
362 [(set Preds:$p, (xor (setcc RC:$a, imm:$b, cmp), Preds:$c))]>;
365 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
366 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, !$c"),
367 [(set Preds:$p, (and (setcc RC:$a, RC:$b, cmp), (not Preds:$c)))]>;
369 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b, Preds:$c),
370 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, !$c"),
371 [(set Preds:$p, (and (setcc RC:$a, imm:$b, cmp), (not Preds:$c)))]>;
373 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
374 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, !$c"),
375 [(set Preds:$p, (or (setcc RC:$a, RC:$b, cmp), (not Preds:$c)))]>;
377 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b, Preds:$c),
378 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, !$c"),
379 [(set Preds:$p, (or (setcc RC:$a, imm:$b, cmp), (not Preds:$c)))]>;
381 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
382 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, !$c"),
383 [(set Preds:$p, (xor (setcc RC:$a, RC:$b, cmp), (not Preds:$c)))]>;
385 : InstPTX<(outs Preds:$p), (ins RC:$a, immcls:$b, Preds:$c),
386 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, !$c"),
387 [(set Preds:$p, (xor (setcc RC:$a, imm:$b, cmp), (not Preds:$c)))]>;
390 multiclass PTX_SETP_FP<RegisterClass RC, string regclsname,
391 CondCode ucmp, CondCode ocmp, string cmpstr> {
392 // TODO support 5-operand format: p|q, a, b, c
395 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b),
396 !strconcat("setp.", cmpstr, "u.", regclsname, "\t$p, $a, $b"),
397 [(set Preds:$p, (setcc RC:$a, RC:$b, ucmp))]>;
399 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b),
400 !strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
401 [(set Preds:$p, (setcc RC:$a, RC:$b, ocmp))]>;
404 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
405 !strconcat("setp.", cmpstr, "u.and.", regclsname, "\t$p, $a, $b, $c"),
406 [(set Preds:$p, (and (setcc RC:$a, RC:$b, ucmp), Preds:$c))]>;
408 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
409 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, $c"),
410 [(set Preds:$p, (and (setcc RC:$a, RC:$b, ocmp), Preds:$c))]>;
413 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
414 !strconcat("setp.", cmpstr, "u.or.", regclsname, "\t$p, $a, $b, $c"),
415 [(set Preds:$p, (or (setcc RC:$a, RC:$b, ucmp), Preds:$c))]>;
417 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
418 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, $c"),
419 [(set Preds:$p, (or (setcc RC:$a, RC:$b, ocmp), Preds:$c))]>;
422 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
423 !strconcat("setp.", cmpstr, "u.xor.", regclsname, "\t$p, $a, $b, $c"),
424 [(set Preds:$p, (xor (setcc RC:$a, RC:$b, ucmp), Preds:$c))]>;
426 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
427 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, $c"),
428 [(set Preds:$p, (xor (setcc RC:$a, RC:$b, ocmp), Preds:$c))]>;
431 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
432 !strconcat("setp.", cmpstr, "u.and.", regclsname, "\t$p, $a, $b, !$c"),
433 [(set Preds:$p, (and (setcc RC:$a, RC:$b, ucmp), (not Preds:$c)))]>;
435 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
436 !strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, !$c"),
437 [(set Preds:$p, (and (setcc RC:$a, RC:$b, ocmp), (not Preds:$c)))]>;
440 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
441 !strconcat("setp.", cmpstr, "u.or.", regclsname, "\t$p, $a, $b, !$c"),
442 [(set Preds:$p, (or (setcc RC:$a, RC:$b, ucmp), (not Preds:$c)))]>;
444 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
445 !strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, !$c"),
446 [(set Preds:$p, (or (setcc RC:$a, RC:$b, ocmp), (not Preds:$c)))]>;
449 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
450 !strconcat("setp.", cmpstr, "u.xor.", regclsname, "\t$p, $a, $b, !$c"),
451 [(set Preds:$p, (xor (setcc RC:$a, RC:$b, ucmp), (not Preds:$c)))]>;
453 : InstPTX<(outs Preds:$p), (ins RC:$a, RC:$b, Preds:$c),
454 !strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, !$c"),
455 [(set Preds:$p, (xor (setcc RC:$a, RC:$b, ocmp), (not Preds:$c)))]>;
458 multiclass PTX_LD<string opstr, string typestr, RegisterClass RC, PatFrag pat_load> {
459 def rr32 : InstPTX<(outs RC:$d),
461 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
462 [(set RC:$d, (pat_load ADDRrr32:$a))]>, Requires<[Use32BitAddresses]>;
463 def rr64 : InstPTX<(outs RC:$d),
465 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
466 [(set RC:$d, (pat_load ADDRrr64:$a))]>, Requires<[Use64BitAddresses]>;
467 def ri32 : InstPTX<(outs RC:$d),
469 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
470 [(set RC:$d, (pat_load ADDRri32:$a))]>, Requires<[Use32BitAddresses]>;
471 def ri64 : InstPTX<(outs RC:$d),
473 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
474 [(set RC:$d, (pat_load ADDRri64:$a))]>, Requires<[Use64BitAddresses]>;
475 def ii32 : InstPTX<(outs RC:$d),
477 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
478 [(set RC:$d, (pat_load ADDRii32:$a))]>, Requires<[Use32BitAddresses]>;
479 def ii64 : InstPTX<(outs RC:$d),
481 !strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
482 [(set RC:$d, (pat_load ADDRii64:$a))]>, Requires<[Use64BitAddresses]>;
485 multiclass PTX_LD_ALL<string opstr, PatFrag pat_load> {
486 defm u16 : PTX_LD<opstr, ".u16", RRegu16, pat_load>;
487 defm u32 : PTX_LD<opstr, ".u32", RRegu32, pat_load>;
488 defm u64 : PTX_LD<opstr, ".u64", RRegu64, pat_load>;
489 defm f32 : PTX_LD<opstr, ".f32", RRegf32, pat_load>;
490 defm f64 : PTX_LD<opstr, ".f64", RRegf64, pat_load>;
493 multiclass PTX_ST<string opstr, string typestr, RegisterClass RC, PatFrag pat_store> {
494 def rr32 : InstPTX<(outs),
495 (ins RC:$d, MEMri32:$a),
496 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
497 [(pat_store RC:$d, ADDRrr32:$a)]>, Requires<[Use32BitAddresses]>;
498 def rr64 : InstPTX<(outs),
499 (ins RC:$d, MEMri64:$a),
500 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
501 [(pat_store RC:$d, ADDRrr64:$a)]>, Requires<[Use64BitAddresses]>;
502 def ri32 : InstPTX<(outs),
503 (ins RC:$d, MEMri32:$a),
504 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
505 [(pat_store RC:$d, ADDRri32:$a)]>, Requires<[Use32BitAddresses]>;
506 def ri64 : InstPTX<(outs),
507 (ins RC:$d, MEMri64:$a),
508 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
509 [(pat_store RC:$d, ADDRri64:$a)]>, Requires<[Use64BitAddresses]>;
510 def ii32 : InstPTX<(outs),
511 (ins RC:$d, MEMii32:$a),
512 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
513 [(pat_store RC:$d, ADDRii32:$a)]>, Requires<[Use32BitAddresses]>;
514 def ii64 : InstPTX<(outs),
515 (ins RC:$d, MEMii64:$a),
516 !strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
517 [(pat_store RC:$d, ADDRii64:$a)]>, Requires<[Use64BitAddresses]>;
520 multiclass PTX_ST_ALL<string opstr, PatFrag pat_store> {
521 defm u16 : PTX_ST<opstr, ".u16", RRegu16, pat_store>;
522 defm u32 : PTX_ST<opstr, ".u32", RRegu32, pat_store>;
523 defm u64 : PTX_ST<opstr, ".u64", RRegu64, pat_store>;
524 defm f32 : PTX_ST<opstr, ".f32", RRegf32, pat_store>;
525 defm f64 : PTX_ST<opstr, ".f64", RRegf64, pat_store>;
528 //===----------------------------------------------------------------------===//
530 //===----------------------------------------------------------------------===//
532 ///===- Integer Arithmetic Instructions -----------------------------------===//
534 defm ADD : INT3<"add", add>;
535 defm SUB : INT3<"sub", sub>;
536 defm MUL : INT3<"mul.lo", mul>; // FIXME: Allow 32x32 -> 64 multiplies
537 defm DIV : INT3<"div", udiv>;
538 defm REM : INT3<"rem", urem>;
540 ///===- Floating-Point Arithmetic Instructions ----------------------------===//
542 // Standard Binary Operations
543 defm FADD : PTX_FLOAT_3OP<"add", fadd>;
544 defm FSUB : PTX_FLOAT_3OP<"sub", fsub>;
545 defm FMUL : PTX_FLOAT_3OP<"mul", fmul>;
547 // TODO: Allow user selection of rounding modes for fdiv.
548 // For division, we need to have f32 and f64 differently.
549 // For f32, we just always use .approx since it is supported on all hardware
550 // for PTX 1.4+, which is our minimum target.
551 def FDIVrr32 : InstPTX<(outs RRegf32:$d),
552 (ins RRegf32:$a, RRegf32:$b),
553 "div.approx.f32\t$d, $a, $b",
554 [(set RRegf32:$d, (fdiv RRegf32:$a, RRegf32:$b))]>;
555 def FDIVri32 : InstPTX<(outs RRegf32:$d),
556 (ins RRegf32:$a, f32imm:$b),
557 "div.approx.f32\t$d, $a, $b",
558 [(set RRegf32:$d, (fdiv RRegf32:$a, fpimm:$b))]>;
560 // For f64, we must specify a rounding for sm 1.3+ but *not* for sm 1.0.
561 def FDIVrr64SM13 : InstPTX<(outs RRegf64:$d),
562 (ins RRegf64:$a, RRegf64:$b),
563 "div.rn.f64\t$d, $a, $b",
564 [(set RRegf64:$d, (fdiv RRegf64:$a, RRegf64:$b))]>,
565 Requires<[SupportsSM13]>;
566 def FDIVri64SM13 : InstPTX<(outs RRegf64:$d),
567 (ins RRegf64:$a, f64imm:$b),
568 "div.rn.f64\t$d, $a, $b",
569 [(set RRegf64:$d, (fdiv RRegf64:$a, fpimm:$b))]>,
570 Requires<[SupportsSM13]>;
571 def FDIVrr64SM10 : InstPTX<(outs RRegf64:$d),
572 (ins RRegf64:$a, RRegf64:$b),
573 "div.f64\t$d, $a, $b",
574 [(set RRegf64:$d, (fdiv RRegf64:$a, RRegf64:$b))]>,
575 Requires<[DoesNotSupportSM13]>;
576 def FDIVri64SM10 : InstPTX<(outs RRegf64:$d),
577 (ins RRegf64:$a, f64imm:$b),
578 "div.f64\t$d, $a, $b",
579 [(set RRegf64:$d, (fdiv RRegf64:$a, fpimm:$b))]>,
580 Requires<[DoesNotSupportSM13]>;
584 // Multi-operation hybrid instructions
586 // The selection of mad/fma is tricky. In some cases, they are the *same*
587 // instruction, but in other cases we may prefer one or the other. Also,
588 // different PTX versions differ on whether rounding mode flags are required.
589 // In the short term, mad is supported on all PTX versions and we use a
590 // default rounding mode no matter what shader model or PTX version.
591 // TODO: Allow the rounding mode to be selectable through llc.
592 defm FMADSM13 : PTX_FLOAT_4OP<"mad.rn", fmul, fadd>, Requires<[SupportsSM13]>;
593 defm FMAD : PTX_FLOAT_4OP<"mad", fmul, fadd>, Requires<[DoesNotSupportSM13]>;
595 ///===- Floating-Point Intrinsic Instructions -----------------------------===//
597 def FSQRT32 : InstPTX<(outs RRegf32:$d),
599 "sqrt.rn.f32\t$d, $a",
600 [(set RRegf32:$d, (fsqrt RRegf32:$a))]>;
602 def FSQRT64 : InstPTX<(outs RRegf64:$d),
604 "sqrt.rn.f64\t$d, $a",
605 [(set RRegf64:$d, (fsqrt RRegf64:$a))]>;
607 def FSIN32 : InstPTX<(outs RRegf32:$d),
609 "sin.approx.f32\t$d, $a",
610 [(set RRegf32:$d, (fsin RRegf32:$a))]>;
612 def FSIN64 : InstPTX<(outs RRegf64:$d),
614 "sin.approx.f64\t$d, $a",
615 [(set RRegf64:$d, (fsin RRegf64:$a))]>;
617 def FCOS32 : InstPTX<(outs RRegf32:$d),
619 "cos.approx.f32\t$d, $a",
620 [(set RRegf32:$d, (fcos RRegf32:$a))]>;
622 def FCOS64 : InstPTX<(outs RRegf64:$d),
624 "cos.approx.f64\t$d, $a",
625 [(set RRegf64:$d, (fcos RRegf64:$a))]>;
628 ///===- Comparison and Selection Instructions -----------------------------===//
632 defm SETPEQu16 : PTX_SETP_I<RRegu16, "u16", i16imm, SETEQ, "eq">;
633 defm SETPNEu16 : PTX_SETP_I<RRegu16, "u16", i16imm, SETNE, "ne">;
634 defm SETPLTu16 : PTX_SETP_I<RRegu16, "u16", i16imm, SETULT, "lt">;
635 defm SETPLEu16 : PTX_SETP_I<RRegu16, "u16", i16imm, SETULE, "le">;
636 defm SETPGTu16 : PTX_SETP_I<RRegu16, "u16", i16imm, SETUGT, "gt">;
637 defm SETPGEu16 : PTX_SETP_I<RRegu16, "u16", i16imm, SETUGE, "ge">;
641 defm SETPEQu32 : PTX_SETP_I<RRegu32, "u32", i32imm, SETEQ, "eq">;
642 defm SETPNEu32 : PTX_SETP_I<RRegu32, "u32", i32imm, SETNE, "ne">;
643 defm SETPLTu32 : PTX_SETP_I<RRegu32, "u32", i32imm, SETULT, "lt">;
644 defm SETPLEu32 : PTX_SETP_I<RRegu32, "u32", i32imm, SETULE, "le">;
645 defm SETPGTu32 : PTX_SETP_I<RRegu32, "u32", i32imm, SETUGT, "gt">;
646 defm SETPGEu32 : PTX_SETP_I<RRegu32, "u32", i32imm, SETUGE, "ge">;
650 defm SETPEQu64 : PTX_SETP_I<RRegu64, "u64", i64imm, SETEQ, "eq">;
651 defm SETPNEu64 : PTX_SETP_I<RRegu64, "u64", i64imm, SETNE, "ne">;
652 defm SETPLTu64 : PTX_SETP_I<RRegu64, "u64", i64imm, SETULT, "lt">;
653 defm SETPLEu64 : PTX_SETP_I<RRegu64, "u64", i64imm, SETULE, "le">;
654 defm SETPGTu64 : PTX_SETP_I<RRegu64, "u64", i64imm, SETUGT, "gt">;
655 defm SETPGEu64 : PTX_SETP_I<RRegu64, "u64", i64imm, SETUGE, "ge">;
659 defm SETPEQf32 : PTX_SETP_FP<RRegf32, "f32", SETUEQ, SETOEQ, "eq">;
660 defm SETPNEf32 : PTX_SETP_FP<RRegf32, "f32", SETUNE, SETONE, "ne">;
661 defm SETPLTf32 : PTX_SETP_FP<RRegf32, "f32", SETULT, SETOLT, "lt">;
662 defm SETPLEf32 : PTX_SETP_FP<RRegf32, "f32", SETULE, SETOLE, "le">;
663 defm SETPGTf32 : PTX_SETP_FP<RRegf32, "f32", SETUGT, SETOGT, "gt">;
664 defm SETPGEf32 : PTX_SETP_FP<RRegf32, "f32", SETUGE, SETOGE, "ge">;
668 defm SETPEQf64 : PTX_SETP_FP<RRegf64, "f64", SETUEQ, SETOEQ, "eq">;
669 defm SETPNEf64 : PTX_SETP_FP<RRegf64, "f64", SETUNE, SETONE, "ne">;
670 defm SETPLTf64 : PTX_SETP_FP<RRegf64, "f64", SETULT, SETOLT, "lt">;
671 defm SETPLEf64 : PTX_SETP_FP<RRegf64, "f64", SETULE, SETOLE, "le">;
672 defm SETPGTf64 : PTX_SETP_FP<RRegf64, "f64", SETUGT, SETOGT, "gt">;
673 defm SETPGEf64 : PTX_SETP_FP<RRegf64, "f64", SETUGE, SETOGE, "ge">;
675 ///===- Logic and Shift Instructions --------------------------------------===//
677 defm SHL : INT3ntnc<"shl.b", PTXshl>;
678 defm SRL : INT3ntnc<"shr.u", PTXsrl>;
679 defm SRA : INT3ntnc<"shr.s", PTXsra>;
681 defm AND : PTX_LOGIC<"and", and>;
682 defm OR : PTX_LOGIC<"or", or>;
683 defm XOR : PTX_LOGIC<"xor", xor>;
685 ///===- Data Movement and Conversion Instructions -------------------------===//
687 let neverHasSideEffects = 1 in {
689 : InstPTX<(outs Preds:$d), (ins Preds:$a), "mov.pred\t$d, $a", []>;
691 : InstPTX<(outs RRegu16:$d), (ins RRegu16:$a), "mov.u16\t$d, $a", []>;
693 : InstPTX<(outs RRegu32:$d), (ins RRegu32:$a), "mov.u32\t$d, $a", []>;
695 : InstPTX<(outs RRegu64:$d), (ins RRegu64:$a), "mov.u64\t$d, $a", []>;
697 : InstPTX<(outs RRegf32:$d), (ins RRegf32:$a), "mov.f32\t$d, $a", []>;
699 : InstPTX<(outs RRegf64:$d), (ins RRegf64:$a), "mov.f64\t$d, $a", []>;
702 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
704 : InstPTX<(outs Preds:$d), (ins i1imm:$a), "mov.pred\t$d, $a",
705 [(set Preds:$d, imm:$a)]>;
707 : InstPTX<(outs RRegu16:$d), (ins i16imm:$a), "mov.u16\t$d, $a",
708 [(set RRegu16:$d, imm:$a)]>;
710 : InstPTX<(outs RRegu32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
711 [(set RRegu32:$d, imm:$a)]>;
713 : InstPTX<(outs RRegu64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
714 [(set RRegu64:$d, imm:$a)]>;
716 : InstPTX<(outs RRegf32:$d), (ins f32imm:$a), "mov.f32\t$d, $a",
717 [(set RRegf32:$d, fpimm:$a)]>;
719 : InstPTX<(outs RRegf64:$d), (ins f64imm:$a), "mov.f64\t$d, $a",
720 [(set RRegf64:$d, fpimm:$a)]>;
723 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
725 : InstPTX<(outs RRegu32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
726 [(set RRegu32:$d, (PTXcopyaddress tglobaladdr:$a))]>;
728 : InstPTX<(outs RRegu64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
729 [(set RRegu64:$d, (PTXcopyaddress tglobaladdr:$a))]>;
733 defm LDg : PTX_LD_ALL<"ld.global", load_global>;
734 defm LDc : PTX_LD_ALL<"ld.const", load_constant>;
735 defm LDl : PTX_LD_ALL<"ld.local", load_local>;
736 defm LDs : PTX_LD_ALL<"ld.shared", load_shared>;
738 // This is a special instruction that is manually inserted for kernel parameters
739 def LDpiU16 : InstPTX<(outs RRegu16:$d), (ins MEMpi:$a),
740 "ld.param.u16\t$d, [$a]", []>;
741 def LDpiU32 : InstPTX<(outs RRegu32:$d), (ins MEMpi:$a),
742 "ld.param.u32\t$d, [$a]", []>;
743 def LDpiU64 : InstPTX<(outs RRegu64:$d), (ins MEMpi:$a),
744 "ld.param.u64\t$d, [$a]", []>;
745 def LDpiF32 : InstPTX<(outs RRegf32:$d), (ins MEMpi:$a),
746 "ld.param.f32\t$d, [$a]", []>;
747 def LDpiF64 : InstPTX<(outs RRegf64:$d), (ins MEMpi:$a),
748 "ld.param.f64\t$d, [$a]", []>;
751 defm STg : PTX_ST_ALL<"st.global", store_global>;
752 defm STl : PTX_ST_ALL<"st.local", store_local>;
753 defm STs : PTX_ST_ALL<"st.shared", store_shared>;
755 // defm STp : PTX_ST_ALL<"st.param", store_parameter>;
756 // defm LDp : PTX_LD_ALL<"ld.param", load_parameter>;
757 // TODO: Do something with st.param if/when it is needed.
759 // Conversion to pred
762 : InstPTX<(outs Preds:$d), (ins RRegu16:$a), "cvt.pred.u16\t$d, $a",
763 [(set Preds:$d, (trunc RRegu16:$a))]>;
766 : InstPTX<(outs Preds:$d), (ins RRegu32:$a), "cvt.pred.u32\t$d, $a",
767 [(set Preds:$d, (trunc RRegu32:$a))]>;
770 : InstPTX<(outs Preds:$d), (ins RRegu64:$a), "cvt.pred.u64\t$d, $a",
771 [(set Preds:$d, (trunc RRegu64:$a))]>;
774 : InstPTX<(outs Preds:$d), (ins RRegf32:$a), "cvt.pred.f32\t$d, $a",
775 [(set Preds:$d, (fp_to_uint RRegf32:$a))]>;
778 : InstPTX<(outs Preds:$d), (ins RRegf64:$a), "cvt.pred.f64\t$d, $a",
779 [(set Preds:$d, (fp_to_uint RRegf64:$a))]>;
784 : InstPTX<(outs RRegu16:$d), (ins Preds:$a), "cvt.u16.pred\t$d, $a",
785 [(set RRegu16:$d, (zext Preds:$a))]>;
788 : InstPTX<(outs RRegu16:$d), (ins RRegu32:$a), "cvt.u16.u32\t$d, $a",
789 [(set RRegu16:$d, (trunc RRegu32:$a))]>;
792 : InstPTX<(outs RRegu16:$d), (ins RRegu64:$a), "cvt.u16.u64\t$d, $a",
793 [(set RRegu16:$d, (trunc RRegu64:$a))]>;
796 : InstPTX<(outs RRegu16:$d), (ins RRegf32:$a), "cvt.u16.f32\t$d, $a",
797 [(set RRegu16:$d, (fp_to_uint RRegf32:$a))]>;
800 : InstPTX<(outs RRegu16:$d), (ins RRegf64:$a), "cvt.u16.f64\t$d, $a",
801 [(set RRegu16:$d, (fp_to_uint RRegf64:$a))]>;
806 : InstPTX<(outs RRegu32:$d), (ins Preds:$a), "cvt.u32.pred\t$d, $a",
807 [(set RRegu32:$d, (zext Preds:$a))]>;
810 : InstPTX<(outs RRegu32:$d), (ins RRegu16:$a), "cvt.u32.u16\t$d, $a",
811 [(set RRegu32:$d, (zext RRegu16:$a))]>;
814 : InstPTX<(outs RRegu32:$d), (ins RRegu64:$a), "cvt.u32.u64\t$d, $a",
815 [(set RRegu32:$d, (trunc RRegu64:$a))]>;
818 : InstPTX<(outs RRegu32:$d), (ins RRegf32:$a), "cvt.u32.f32\t$d, $a",
819 [(set RRegu32:$d, (fp_to_uint RRegf32:$a))]>;
822 : InstPTX<(outs RRegu32:$d), (ins RRegf64:$a), "cvt.u32.f64\t$d, $a",
823 [(set RRegu32:$d, (fp_to_uint RRegf64:$a))]>;
828 : InstPTX<(outs RRegu64:$d), (ins Preds:$a), "cvt.u64.pred\t$d, $a",
829 [(set RRegu64:$d, (zext Preds:$a))]>;
832 : InstPTX<(outs RRegu64:$d), (ins RRegu16:$a), "cvt.u64.u16\t$d, $a",
833 [(set RRegu64:$d, (zext RRegu16:$a))]>;
836 : InstPTX<(outs RRegu64:$d), (ins RRegu32:$a), "cvt.u64.u32\t$d, $a",
837 [(set RRegu64:$d, (zext RRegu32:$a))]>;
840 : InstPTX<(outs RRegu64:$d), (ins RRegf32:$a), "cvt.u64.f32\t$d, $a",
841 [(set RRegu64:$d, (fp_to_uint RRegf32:$a))]>;
844 : InstPTX<(outs RRegu64:$d), (ins RRegf64:$a), "cvt.u64.f32\t$d, $a",
845 [(set RRegu64:$d, (fp_to_uint RRegf64:$a))]>;
850 : InstPTX<(outs RRegf32:$d), (ins Preds:$a), "cvt.f32.pred\t$d, $a",
851 [(set RRegf32:$d, (uint_to_fp Preds:$a))]>;
854 : InstPTX<(outs RRegf32:$d), (ins RRegu16:$a), "cvt.f32.u16\t$d, $a",
855 [(set RRegf32:$d, (uint_to_fp RRegu16:$a))]>;
858 : InstPTX<(outs RRegf32:$d), (ins RRegu32:$a), "cvt.f32.u32\t$d, $a",
859 [(set RRegf32:$d, (uint_to_fp RRegu32:$a))]>;
862 : InstPTX<(outs RRegf32:$d), (ins RRegu64:$a), "cvt.f32.u64\t$d, $a",
863 [(set RRegf32:$d, (uint_to_fp RRegu64:$a))]>;
866 : InstPTX<(outs RRegf32:$d), (ins RRegf64:$a), "cvt.f32.f64\t$d, $a",
867 [(set RRegf32:$d, (fround RRegf64:$a))]>;
872 : InstPTX<(outs RRegf64:$d), (ins Preds:$a), "cvt.f64.pred\t$d, $a",
873 [(set RRegf64:$d, (uint_to_fp Preds:$a))]>;
876 : InstPTX<(outs RRegf64:$d), (ins RRegu16:$a), "cvt.f64.u16\t$d, $a",
877 [(set RRegf64:$d, (uint_to_fp RRegu16:$a))]>;
880 : InstPTX<(outs RRegf64:$d), (ins RRegu32:$a), "cvt.f64.u32\t$d, $a",
881 [(set RRegf64:$d, (uint_to_fp RRegu32:$a))]>;
884 : InstPTX<(outs RRegf64:$d), (ins RRegu64:$a), "cvt.f64.u64\t$d, $a",
885 [(set RRegf64:$d, (uint_to_fp RRegu64:$a))]>;
888 : InstPTX<(outs RRegf64:$d), (ins RRegf32:$a), "cvt.f64.f32\t$d, $a",
889 [(set RRegf64:$d, (fextend RRegf32:$a))]>;
891 ///===- Control Flow Instructions -----------------------------------------===//
893 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
895 : InstPTX<(outs), (ins brtarget:$d), "bra\t$d", [(br bb:$d)]>;
898 let isBranch = 1, isTerminator = 1 in {
899 // FIXME: The pattern part is blank because I cannot (or do not yet know
900 // how to) use the first operand of PredicateOperand (a Preds register) here
902 : InstPTX<(outs), (ins brtarget:$d), "bra\t$d",
903 [/*(brcond pred:$_p, bb:$d)*/]>;
906 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
907 def EXIT : InstPTX<(outs), (ins), "exit", [(PTXexit)]>;
908 def RET : InstPTX<(outs), (ins), "ret", [(PTXret)]>;
911 ///===- Intrinsic Instructions --------------------------------------------===//
913 include "PTXIntrinsicInstrInfo.td"