1 //===-- PTXISelDAGToDAG.cpp - A dag to dag inst selector for PTX ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the PTX target.
12 //===----------------------------------------------------------------------===//
15 #include "PTXTargetMachine.h"
16 #include "llvm/CodeGen/SelectionDAGISel.h"
17 #include "llvm/DerivedTypes.h"
22 // PTXDAGToDAGISel - PTX specific code to select PTX machine
23 // instructions for SelectionDAG operations.
24 class PTXDAGToDAGISel : public SelectionDAGISel {
26 PTXDAGToDAGISel(PTXTargetMachine &TM, CodeGenOpt::Level OptLevel);
28 virtual const char *getPassName() const {
29 return "PTX DAG->DAG Pattern Instruction Selection";
32 SDNode *Select(SDNode *Node);
34 // Complex Pattern Selectors.
35 bool SelectADDRri(SDValue &Addr, SDValue &Base, SDValue &Offset);
36 bool SelectADDRii(SDValue &Addr, SDValue &Base, SDValue &Offset);
38 // Include the pieces auto'gened from the target description
39 #include "PTXGenDAGISel.inc"
42 bool isImm (const SDValue &operand);
43 bool SelectImm (const SDValue &operand, SDValue &imm);
44 }; // class PTXDAGToDAGISel
47 // createPTXISelDag - This pass converts a legalized DAG into a
48 // PTX-specific DAG, ready for instruction scheduling
49 FunctionPass *llvm::createPTXISelDag(PTXTargetMachine &TM,
50 CodeGenOpt::Level OptLevel) {
51 return new PTXDAGToDAGISel(TM, OptLevel);
54 PTXDAGToDAGISel::PTXDAGToDAGISel(PTXTargetMachine &TM,
55 CodeGenOpt::Level OptLevel)
56 : SelectionDAGISel(TM, OptLevel) {}
58 SDNode *PTXDAGToDAGISel::Select(SDNode *Node) {
59 // SelectCode() is auto'gened
60 return SelectCode(Node);
63 // Match memory operand of the form [reg+reg] and [reg+imm]
64 bool PTXDAGToDAGISel::SelectADDRri(SDValue &Addr, SDValue &Base,
66 if (Addr.getNumOperands() >= 2 &&
67 isImm(Addr.getOperand(0)) && isImm(Addr.getOperand(1)))
68 return false; // let SelectADDRii handle the [imm+imm] case
70 // try [reg+imm] and [imm+reg]
71 if (Addr.getOpcode() == ISD::ADD)
72 for (int i = 0; i < 2; i ++)
73 if (SelectImm(Addr.getOperand(1-i), Offset)) {
74 Base = Addr.getOperand(i);
78 // okay, it's [reg+reg]
80 Offset = CurDAG->getTargetConstant(0, MVT::i32);
84 // Match memory operand of the form [imm+imm] and [imm]
85 bool PTXDAGToDAGISel::SelectADDRii(SDValue &Addr, SDValue &Base,
87 if (Addr.getOpcode() == ISD::ADD) {
88 return SelectImm(Addr.getOperand(0), Base) &&
89 SelectImm(Addr.getOperand(1), Offset);
92 if (SelectImm(Addr, Base)) {
93 Offset = CurDAG->getTargetConstant(0, MVT::i32);
100 bool PTXDAGToDAGISel::isImm(const SDValue &operand) {
101 return ConstantSDNode::classof(operand.getNode());
104 bool PTXDAGToDAGISel::SelectImm(const SDValue &operand, SDValue &imm) {
105 SDNode *node = operand.getNode();
106 if (!ConstantSDNode::classof(node))
109 ConstantSDNode *CN = cast<ConstantSDNode>(node);
110 imm = CurDAG->getTargetConstant(*CN->getConstantIntValue(), MVT::i32);