lib/Target/PIC16/PIC16InstrInfo.h

   1 //===- PIC16InstrInfo.h - PIC16 Instruction Information----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the niversity of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the PIC16 implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef PIC16INSTRUCTIONINFO_H
  15 #define PIC16INSTRUCTIONINFO_H
  16
  17 #include "PIC16.h"
  18 #include "PIC16RegisterInfo.h"
  19 #include "llvm/Target/TargetInstrInfo.h"
  20
  21 namespace llvm {
  22
  23
  24 class PIC16InstrInfo : public TargetInstrInfoImpl
  25 {
  26   PIC16TargetMachine &TM;
  27   const PIC16RegisterInfo RegInfo;
  28 public:
  29   explicit PIC16InstrInfo(PIC16TargetMachine &TM);
  30
  31   virtual const PIC16RegisterInfo &getRegisterInfo() const { return RegInfo; }
  32
  33   /// isLoadFromStackSlot - If the specified machine instruction is a direct
  34   /// load from a stack slot, return the virtual or physical register number of
  35   /// the destination along with the FrameIndex of the loaded stack slot.  If
  36   /// not, return 0.  This predicate must return 0 if the instruction has
  37   /// any side effects other than loading from the stack slot.
  38   virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
  39                                        int &FrameIndex) const;
  40
  41   /// isStoreToStackSlot - If the specified machine instruction is a direct
  42   /// store to a stack slot, return the virtual or physical register number of
  43   /// the source reg along with the FrameIndex of the loaded stack slot.  If
  44   /// not, return 0.  This predicate must return 0 if the instruction has
  45   /// any side effects other than storing to the stack slot.
  46   virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
  47                                       int &FrameIndex) const;
  48
  49   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
  50                                    MachineBasicBlock::iterator MBBI,
  51                                    unsigned SrcReg, bool isKill, int FrameIndex,
  52                                    const TargetRegisterClass *RC,
  53                                    const TargetRegisterInfo *TRI) const;
  54
  55   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
  56                                     MachineBasicBlock::iterator MBBI,
  57                                     unsigned DestReg, int FrameIndex,
  58                                     const TargetRegisterClass *RC,
  59                                     const TargetRegisterInfo *TRI) const;
  60   virtual void copyPhysReg(MachineBasicBlock &MBB,
  61                            MachineBasicBlock::iterator I, DebugLoc DL,
  62                            unsigned DestReg, unsigned SrcReg,
  63                            bool KillSrc) const;
  64   virtual bool isMoveInstr(const MachineInstr &MI,
  65                            unsigned &SrcReg, unsigned &DstReg,
  66                            unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
  67
  68   virtual
  69   unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
  70                         MachineBasicBlock *FBB,
  71                         const SmallVectorImpl<MachineOperand> &Cond,
  72                         DebugLoc DL) const;
  73   virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
  74                              MachineBasicBlock *&FBB,
  75                              SmallVectorImpl<MachineOperand> &Cond,
  76                              bool AllowModify) const;
  77   };
  78 } // namespace llvm
  79
  80 #endif