1 //===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the NVPTX target.
12 //===----------------------------------------------------------------------===//
14 #include "NVPTXTargetMachine.h"
15 #include "MCTargetDesc/NVPTXMCAsmInfo.h"
17 #include "NVPTXAllocaHoisting.h"
18 #include "NVPTXLowerAggrCopies.h"
19 #include "NVPTXSplitBBatBar.h"
20 #include "llvm/ADT/OwningPtr.h"
21 #include "llvm/Analysis/Passes.h"
22 #include "llvm/Analysis/Verifier.h"
23 #include "llvm/Assembly/PrintModulePass.h"
24 #include "llvm/CodeGen/AsmPrinter.h"
25 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/IR/DataLayout.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCInstrInfo.h"
31 #include "llvm/MC/MCStreamer.h"
32 #include "llvm/MC/MCSubtargetInfo.h"
33 #include "llvm/PassManager.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/FormattedStream.h"
37 #include "llvm/Support/TargetRegistry.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetLowering.h"
41 #include "llvm/Target/TargetLoweringObjectFile.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include "llvm/Target/TargetRegisterInfo.h"
45 #include "llvm/Target/TargetSubtargetInfo.h"
46 #include "llvm/Transforms/Scalar.h"
51 void initializeNVVMReflectPass(PassRegistry&);
52 void initializeGenericToNVVMPass(PassRegistry&);
55 extern "C" void LLVMInitializeNVPTXTarget() {
56 // Register the target.
57 RegisterTargetMachine<NVPTXTargetMachine32> X(TheNVPTXTarget32);
58 RegisterTargetMachine<NVPTXTargetMachine64> Y(TheNVPTXTarget64);
60 // FIXME: This pass is really intended to be invoked during IR optimization,
61 // but it's very NVPTX-specific.
62 initializeNVVMReflectPass(*PassRegistry::getPassRegistry());
63 initializeGenericToNVVMPass(*PassRegistry::getPassRegistry());
66 static std::string computeDataLayout(const NVPTXSubtarget &ST) {
67 std::string Ret = "e";
72 Ret += "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
73 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
79 NVPTXTargetMachine::NVPTXTargetMachine(
80 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
81 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
82 CodeGenOpt::Level OL, bool is64bit)
83 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
84 Subtarget(TT, CPU, FS, is64bit), DL(computeDataLayout(Subtarget)),
85 InstrInfo(*this), TLInfo(*this), TSInfo(*this),
87 *this, is64bit) /*FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0)*/ {
91 void NVPTXTargetMachine32::anchor() {}
93 NVPTXTargetMachine32::NVPTXTargetMachine32(
94 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
95 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
97 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
99 void NVPTXTargetMachine64::anchor() {}
101 NVPTXTargetMachine64::NVPTXTargetMachine64(
102 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
103 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
104 CodeGenOpt::Level OL)
105 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
108 class NVPTXPassConfig : public TargetPassConfig {
110 NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM)
111 : TargetPassConfig(TM, PM) {}
113 NVPTXTargetMachine &getNVPTXTargetMachine() const {
114 return getTM<NVPTXTargetMachine>();
117 virtual void addIRPasses();
118 virtual bool addInstSelector();
119 virtual bool addPreRegAlloc();
120 virtual bool addPostRegAlloc();
122 virtual FunctionPass *createTargetRegisterAllocator(bool) LLVM_OVERRIDE;
123 virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
124 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
126 } // end anonymous namespace
128 TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
129 NVPTXPassConfig *PassConfig = new NVPTXPassConfig(this, PM);
133 void NVPTXPassConfig::addIRPasses() {
134 // The following passes are known to not play well with virtual regs hanging
135 // around after register allocation (which in our case, is *all* registers).
136 // We explicitly disable them here. We do, however, need some functionality
137 // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
138 // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
139 disablePass(&PrologEpilogCodeInserterID);
140 disablePass(&MachineCopyPropagationID);
141 disablePass(&BranchFolderPassID);
142 disablePass(&TailDuplicateID);
144 TargetPassConfig::addIRPasses();
145 addPass(createGenericToNVVMPass());
148 bool NVPTXPassConfig::addInstSelector() {
149 addPass(createLowerAggrCopies());
150 addPass(createSplitBBatBarPass());
151 addPass(createAllocaHoisting());
152 addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
156 bool NVPTXPassConfig::addPreRegAlloc() { return false; }
157 bool NVPTXPassConfig::addPostRegAlloc() {
158 addPass(createNVPTXPrologEpilogPass());
162 FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
163 return 0; // No reg alloc
166 void NVPTXPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
167 assert(!RegAllocPass && "NVPTX uses no regalloc!");
168 addPass(&PHIEliminationID);
169 addPass(&TwoAddressInstructionPassID);
172 void NVPTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
173 assert(!RegAllocPass && "NVPTX uses no regalloc!");
175 addPass(&ProcessImplicitDefsID);
176 addPass(&LiveVariablesID);
177 addPass(&MachineLoopInfoID);
178 addPass(&PHIEliminationID);
180 addPass(&TwoAddressInstructionPassID);
181 addPass(&RegisterCoalescerID);
183 // PreRA instruction scheduling.
184 if (addPass(&MachineSchedulerID))
185 printAndVerify("After Machine Scheduling");
188 addPass(&StackSlotColoringID);
190 // FIXME: Needs physical registers
191 //addPass(&PostRAMachineLICMID);
193 printAndVerify("After StackSlotColoring");