1 //===- NVPTXRegisterInfo.cpp - NVPTX Register Information -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the NVPTX implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "nvptx-reg-info"
16 #include "NVPTXRegisterInfo.h"
18 #include "NVPTXSubtarget.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/MC/MachineLocation.h"
24 #include "llvm/Target/TargetInstrInfo.h"
31 std::string getNVPTXRegClassName (TargetRegisterClass const *RC) {
32 if (RC == &NVPTX::Float32RegsRegClass) {
35 if (RC == &NVPTX::Float64RegsRegClass) {
38 else if (RC == &NVPTX::Int64RegsRegClass) {
41 else if (RC == &NVPTX::Int32RegsRegClass) {
44 else if (RC == &NVPTX::Int16RegsRegClass) {
47 // Int8Regs become 16-bit registers in PTX
48 else if (RC == &NVPTX::Int8RegsRegClass) {
51 else if (RC == &NVPTX::Int1RegsRegClass) {
54 else if (RC == &NVPTX::SpecialRegsRegClass) {
57 else if (RC == &NVPTX::V2F32RegsRegClass) {
60 else if (RC == &NVPTX::V4F32RegsRegClass) {
63 else if (RC == &NVPTX::V2I32RegsRegClass) {
66 else if (RC == &NVPTX::V4I32RegsRegClass) {
69 else if (RC == &NVPTX::V2F64RegsRegClass) {
72 else if (RC == &NVPTX::V2I64RegsRegClass) {
75 else if (RC == &NVPTX::V2I16RegsRegClass) {
78 else if (RC == &NVPTX::V4I16RegsRegClass) {
81 else if (RC == &NVPTX::V2I8RegsRegClass) {
84 else if (RC == &NVPTX::V4I8RegsRegClass) {
93 std::string getNVPTXRegClassStr (TargetRegisterClass const *RC) {
94 if (RC == &NVPTX::Float32RegsRegClass) {
97 if (RC == &NVPTX::Float64RegsRegClass) {
100 else if (RC == &NVPTX::Int64RegsRegClass) {
103 else if (RC == &NVPTX::Int32RegsRegClass) {
106 else if (RC == &NVPTX::Int16RegsRegClass) {
109 else if (RC == &NVPTX::Int8RegsRegClass) {
112 else if (RC == &NVPTX::Int1RegsRegClass) {
115 else if (RC == &NVPTX::SpecialRegsRegClass) {
118 else if (RC == &NVPTX::V2F32RegsRegClass) {
121 else if (RC == &NVPTX::V4F32RegsRegClass) {
124 else if (RC == &NVPTX::V2I32RegsRegClass) {
127 else if (RC == &NVPTX::V4I32RegsRegClass) {
130 else if (RC == &NVPTX::V2F64RegsRegClass) {
133 else if (RC == &NVPTX::V2I64RegsRegClass) {
136 else if (RC == &NVPTX::V2I16RegsRegClass) {
139 else if (RC == &NVPTX::V4I16RegsRegClass) {
142 else if (RC == &NVPTX::V2I8RegsRegClass) {
145 else if (RC == &NVPTX::V4I8RegsRegClass) {
154 bool isNVPTXVectorRegClass(TargetRegisterClass const *RC) {
155 if (RC->getID() == NVPTX::V2F32RegsRegClassID)
157 if (RC->getID() == NVPTX::V2F64RegsRegClassID)
159 if (RC->getID() == NVPTX::V2I16RegsRegClassID)
161 if (RC->getID() == NVPTX::V2I32RegsRegClassID)
163 if (RC->getID() == NVPTX::V2I64RegsRegClassID)
165 if (RC->getID() == NVPTX::V2I8RegsRegClassID)
167 if (RC->getID() == NVPTX::V4F32RegsRegClassID)
169 if (RC->getID() == NVPTX::V4I16RegsRegClassID)
171 if (RC->getID() == NVPTX::V4I32RegsRegClassID)
173 if (RC->getID() == NVPTX::V4I8RegsRegClassID)
178 std::string getNVPTXElemClassName(TargetRegisterClass const *RC) {
179 if (RC->getID() == NVPTX::V2F32RegsRegClassID)
180 return getNVPTXRegClassName(&NVPTX::Float32RegsRegClass);
181 if (RC->getID() == NVPTX::V2F64RegsRegClassID)
182 return getNVPTXRegClassName(&NVPTX::Float64RegsRegClass);
183 if (RC->getID() == NVPTX::V2I16RegsRegClassID)
184 return getNVPTXRegClassName(&NVPTX::Int16RegsRegClass);
185 if (RC->getID() == NVPTX::V2I32RegsRegClassID)
186 return getNVPTXRegClassName(&NVPTX::Int32RegsRegClass);
187 if (RC->getID() == NVPTX::V2I64RegsRegClassID)
188 return getNVPTXRegClassName(&NVPTX::Int64RegsRegClass);
189 if (RC->getID() == NVPTX::V2I8RegsRegClassID)
190 return getNVPTXRegClassName(&NVPTX::Int8RegsRegClass);
191 if (RC->getID() == NVPTX::V4F32RegsRegClassID)
192 return getNVPTXRegClassName(&NVPTX::Float32RegsRegClass);
193 if (RC->getID() == NVPTX::V4I16RegsRegClassID)
194 return getNVPTXRegClassName(&NVPTX::Int16RegsRegClass);
195 if (RC->getID() == NVPTX::V4I32RegsRegClassID)
196 return getNVPTXRegClassName(&NVPTX::Int32RegsRegClass);
197 if (RC->getID() == NVPTX::V4I8RegsRegClassID)
198 return getNVPTXRegClassName(&NVPTX::Int8RegsRegClass);
199 llvm_unreachable("Not a vector register class");
202 const TargetRegisterClass *getNVPTXElemClass(TargetRegisterClass const *RC) {
203 if (RC->getID() == NVPTX::V2F32RegsRegClassID)
204 return (&NVPTX::Float32RegsRegClass);
205 if (RC->getID() == NVPTX::V2F64RegsRegClassID)
206 return (&NVPTX::Float64RegsRegClass);
207 if (RC->getID() == NVPTX::V2I16RegsRegClassID)
208 return (&NVPTX::Int16RegsRegClass);
209 if (RC->getID() == NVPTX::V2I32RegsRegClassID)
210 return (&NVPTX::Int32RegsRegClass);
211 if (RC->getID() == NVPTX::V2I64RegsRegClassID)
212 return (&NVPTX::Int64RegsRegClass);
213 if (RC->getID() == NVPTX::V2I8RegsRegClassID)
214 return (&NVPTX::Int8RegsRegClass);
215 if (RC->getID() == NVPTX::V4F32RegsRegClassID)
216 return (&NVPTX::Float32RegsRegClass);
217 if (RC->getID() == NVPTX::V4I16RegsRegClassID)
218 return (&NVPTX::Int16RegsRegClass);
219 if (RC->getID() == NVPTX::V4I32RegsRegClassID)
220 return (&NVPTX::Int32RegsRegClass);
221 if (RC->getID() == NVPTX::V4I8RegsRegClassID)
222 return (&NVPTX::Int8RegsRegClass);
223 llvm_unreachable("Not a vector register class");
226 int getNVPTXVectorSize(TargetRegisterClass const *RC) {
227 if (RC->getID() == NVPTX::V2F32RegsRegClassID)
229 if (RC->getID() == NVPTX::V2F64RegsRegClassID)
231 if (RC->getID() == NVPTX::V2I16RegsRegClassID)
233 if (RC->getID() == NVPTX::V2I32RegsRegClassID)
235 if (RC->getID() == NVPTX::V2I64RegsRegClassID)
237 if (RC->getID() == NVPTX::V2I8RegsRegClassID)
239 if (RC->getID() == NVPTX::V4F32RegsRegClassID)
241 if (RC->getID() == NVPTX::V4I16RegsRegClassID)
243 if (RC->getID() == NVPTX::V4I32RegsRegClassID)
245 if (RC->getID() == NVPTX::V4I8RegsRegClassID)
247 llvm_unreachable("Not a vector register class");
251 NVPTXRegisterInfo::NVPTXRegisterInfo(const TargetInstrInfo &tii,
252 const NVPTXSubtarget &st)
253 : NVPTXGenRegisterInfo(0),
254 Is64Bit(st.is64Bit()) {}
256 #define GET_REGINFO_TARGET_DESC
257 #include "NVPTXGenRegisterInfo.inc"
259 /// NVPTX Callee Saved Registers
260 const uint16_t* NVPTXRegisterInfo::
261 getCalleeSavedRegs(const MachineFunction *MF) const {
262 static const uint16_t CalleeSavedRegs[] = { 0 };
263 return CalleeSavedRegs;
266 // NVPTX Callee Saved Reg Classes
267 const TargetRegisterClass* const*
268 NVPTXRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
269 static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
270 return CalleeSavedRegClasses;
273 BitVector NVPTXRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
274 BitVector Reserved(getNumRegs());
278 void NVPTXRegisterInfo::
279 eliminateFrameIndex(MachineBasicBlock::iterator II,
280 int SPAdj, unsigned FIOperandNum,
281 RegScavenger *RS) const {
282 assert(SPAdj == 0 && "Unexpected");
284 MachineInstr &MI = *II;
285 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
287 MachineFunction &MF = *MI.getParent()->getParent();
288 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
289 MI.getOperand(FIOperandNum+1).getImm();
291 // Using I0 as the frame pointer
292 MI.getOperand(FIOperandNum).ChangeToRegister(NVPTX::VRFrame, false);
293 MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
296 int NVPTXRegisterInfo::
297 getDwarfRegNum(unsigned RegNum, bool isEH) const {
301 unsigned NVPTXRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
302 return NVPTX::VRFrame;
305 unsigned NVPTXRegisterInfo::getRARegister() const {
309 // This function eliminates ADJCALLSTACKDOWN,
310 // ADJCALLSTACKUP pseudo instructions
311 void NVPTXRegisterInfo::
312 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
313 MachineBasicBlock::iterator I) const {
314 // Simply discard ADJCALLSTACKDOWN,
315 // ADJCALLSTACKUP instructions.