1 //===- NVPTXRegisterInfo.cpp - NVPTX Register Information -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the NVPTX implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "nvptx-reg-info"
16 #include "NVPTXRegisterInfo.h"
18 #include "NVPTXSubtarget.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/MC/MachineLocation.h"
24 #include "llvm/Target/TargetInstrInfo.h"
29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) {
30 if (RC == &NVPTX::Float32RegsRegClass) {
33 if (RC == &NVPTX::Float64RegsRegClass) {
35 } else if (RC == &NVPTX::Int64RegsRegClass) {
37 } else if (RC == &NVPTX::Int32RegsRegClass) {
39 } else if (RC == &NVPTX::Int16RegsRegClass) {
42 // Int8Regs become 16-bit registers in PTX
43 else if (RC == &NVPTX::Int8RegsRegClass) {
45 } else if (RC == &NVPTX::Int1RegsRegClass) {
47 } else if (RC == &NVPTX::SpecialRegsRegClass) {
55 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) {
56 if (RC == &NVPTX::Float32RegsRegClass) {
59 if (RC == &NVPTX::Float64RegsRegClass) {
61 } else if (RC == &NVPTX::Int64RegsRegClass) {
63 } else if (RC == &NVPTX::Int32RegsRegClass) {
65 } else if (RC == &NVPTX::Int16RegsRegClass) {
67 } else if (RC == &NVPTX::Int8RegsRegClass) {
69 } else if (RC == &NVPTX::Int1RegsRegClass) {
71 } else if (RC == &NVPTX::SpecialRegsRegClass) {
80 NVPTXRegisterInfo::NVPTXRegisterInfo(const NVPTXSubtarget &st)
81 : NVPTXGenRegisterInfo(0), Is64Bit(st.is64Bit()) {}
83 #define GET_REGINFO_TARGET_DESC
84 #include "NVPTXGenRegisterInfo.inc"
86 /// NVPTX Callee Saved Registers
88 NVPTXRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
89 static const uint16_t CalleeSavedRegs[] = { 0 };
90 return CalleeSavedRegs;
93 // NVPTX Callee Saved Reg Classes
94 const TargetRegisterClass *const *
95 NVPTXRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
96 static const TargetRegisterClass *const CalleeSavedRegClasses[] = { 0 };
97 return CalleeSavedRegClasses;
100 BitVector NVPTXRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
101 BitVector Reserved(getNumRegs());
105 void NVPTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
106 int SPAdj, unsigned FIOperandNum,
107 RegScavenger *RS) const {
108 assert(SPAdj == 0 && "Unexpected");
110 MachineInstr &MI = *II;
111 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
113 MachineFunction &MF = *MI.getParent()->getParent();
114 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
115 MI.getOperand(FIOperandNum + 1).getImm();
117 // Using I0 as the frame pointer
118 MI.getOperand(FIOperandNum).ChangeToRegister(NVPTX::VRFrame, false);
119 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
122 int NVPTXRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
126 unsigned NVPTXRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
127 return NVPTX::VRFrame;
130 unsigned NVPTXRegisterInfo::getRARegister() const { return 0; }