1 //===- NVPTXInstrInfo.cpp - NVPTX Instruction Information -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the NVPTX implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "NVPTXInstrInfo.h"
16 #include "NVPTXTargetMachine.h"
17 #define GET_INSTRINFO_CTOR
18 #include "NVPTXGenInstrInfo.inc"
19 #include "llvm/IR/Function.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 // FIXME: Add the subtarget support on this constructor.
28 NVPTXInstrInfo::NVPTXInstrInfo(NVPTXTargetMachine &tm)
29 : NVPTXGenInstrInfo(), TM(tm), RegInfo(*TM.getSubtargetImpl()) {}
31 void NVPTXInstrInfo::copyPhysReg(
32 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL,
33 unsigned DestReg, unsigned SrcReg, bool KillSrc) const {
34 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
35 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
36 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
39 report_fatal_error("Attempted to created cross-class register copy");
41 if (DestRC == &NVPTX::Int32RegsRegClass)
42 BuildMI(MBB, I, DL, get(NVPTX::IMOV32rr), DestReg)
43 .addReg(SrcReg, getKillRegState(KillSrc));
44 else if (DestRC == &NVPTX::Int1RegsRegClass)
45 BuildMI(MBB, I, DL, get(NVPTX::IMOV1rr), DestReg)
46 .addReg(SrcReg, getKillRegState(KillSrc));
47 else if (DestRC == &NVPTX::Float32RegsRegClass)
48 BuildMI(MBB, I, DL, get(NVPTX::FMOV32rr), DestReg)
49 .addReg(SrcReg, getKillRegState(KillSrc));
50 else if (DestRC == &NVPTX::Int16RegsRegClass)
51 BuildMI(MBB, I, DL, get(NVPTX::IMOV16rr), DestReg)
52 .addReg(SrcReg, getKillRegState(KillSrc));
53 else if (DestRC == &NVPTX::Int64RegsRegClass)
54 BuildMI(MBB, I, DL, get(NVPTX::IMOV64rr), DestReg)
55 .addReg(SrcReg, getKillRegState(KillSrc));
56 else if (DestRC == &NVPTX::Float64RegsRegClass)
57 BuildMI(MBB, I, DL, get(NVPTX::FMOV64rr), DestReg)
58 .addReg(SrcReg, getKillRegState(KillSrc));
60 llvm_unreachable("Bad register copy");
64 bool NVPTXInstrInfo::isMoveInstr(const MachineInstr &MI, unsigned &SrcReg,
65 unsigned &DestReg) const {
66 // Look for the appropriate part of TSFlags
70 (MI.getDesc().TSFlags & NVPTX::SimpleMoveMask) >> NVPTX::SimpleMoveShift;
71 isMove = (TSFlags == 1);
74 MachineOperand dest = MI.getOperand(0);
75 MachineOperand src = MI.getOperand(1);
76 assert(dest.isReg() && "dest of a movrr is not a reg");
77 assert(src.isReg() && "src of a movrr is not a reg");
79 SrcReg = src.getReg();
80 DestReg = dest.getReg();
87 bool NVPTXInstrInfo::isReadSpecialReg(MachineInstr &MI) const {
88 switch (MI.getOpcode()) {
91 case NVPTX::INT_PTX_SREG_NTID_X:
92 case NVPTX::INT_PTX_SREG_NTID_Y:
93 case NVPTX::INT_PTX_SREG_NTID_Z:
94 case NVPTX::INT_PTX_SREG_TID_X:
95 case NVPTX::INT_PTX_SREG_TID_Y:
96 case NVPTX::INT_PTX_SREG_TID_Z:
97 case NVPTX::INT_PTX_SREG_CTAID_X:
98 case NVPTX::INT_PTX_SREG_CTAID_Y:
99 case NVPTX::INT_PTX_SREG_CTAID_Z:
100 case NVPTX::INT_PTX_SREG_NCTAID_X:
101 case NVPTX::INT_PTX_SREG_NCTAID_Y:
102 case NVPTX::INT_PTX_SREG_NCTAID_Z:
103 case NVPTX::INT_PTX_SREG_WARPSIZE:
108 bool NVPTXInstrInfo::isLoadInstr(const MachineInstr &MI,
109 unsigned &AddrSpace) const {
112 (MI.getDesc().TSFlags & NVPTX::isLoadMask) >> NVPTX::isLoadShift;
113 isLoad = (TSFlags == 1);
115 AddrSpace = getLdStCodeAddrSpace(MI);
119 bool NVPTXInstrInfo::isStoreInstr(const MachineInstr &MI,
120 unsigned &AddrSpace) const {
121 bool isStore = false;
123 (MI.getDesc().TSFlags & NVPTX::isStoreMask) >> NVPTX::isStoreShift;
124 isStore = (TSFlags == 1);
126 AddrSpace = getLdStCodeAddrSpace(MI);
130 bool NVPTXInstrInfo::CanTailMerge(const MachineInstr *MI) const {
131 unsigned addrspace = 0;
132 if (MI->getOpcode() == NVPTX::INT_CUDA_SYNCTHREADS)
134 if (isLoadInstr(*MI, addrspace))
135 if (addrspace == NVPTX::PTXLdStInstCode::SHARED)
137 if (isStoreInstr(*MI, addrspace))
138 if (addrspace == NVPTX::PTXLdStInstCode::SHARED)
143 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
144 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
145 /// implemented for a target). Upon success, this returns false and returns
146 /// with the following information in various cases:
148 /// 1. If this block ends with no branches (it just falls through to its succ)
149 /// just return false, leaving TBB/FBB null.
150 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
151 /// the destination block.
152 /// 3. If this block ends with an conditional branch and it falls through to
153 /// an successor block, it sets TBB to be the branch destination block and a
154 /// list of operands that evaluate the condition. These
155 /// operands can be passed to other TargetInstrInfo methods to create new
157 /// 4. If this block ends with an conditional branch and an unconditional
158 /// block, it returns the 'true' destination in TBB, the 'false' destination
159 /// in FBB, and a list of operands that evaluate the condition. These
160 /// operands can be passed to other TargetInstrInfo methods to create new
163 /// Note that RemoveBranch and InsertBranch must be implemented to support
164 /// cases where this method returns success.
166 bool NVPTXInstrInfo::AnalyzeBranch(
167 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
168 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const {
169 // If the block has no terminators, it just falls into the block after it.
170 MachineBasicBlock::iterator I = MBB.end();
171 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
174 // Get the last instruction in the block.
175 MachineInstr *LastInst = I;
177 // If there is only one terminator instruction, process it.
178 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
179 if (LastInst->getOpcode() == NVPTX::GOTO) {
180 TBB = LastInst->getOperand(0).getMBB();
182 } else if (LastInst->getOpcode() == NVPTX::CBranch) {
183 // Block ends with fall-through condbranch.
184 TBB = LastInst->getOperand(1).getMBB();
185 Cond.push_back(LastInst->getOperand(0));
188 // Otherwise, don't know what this is.
192 // Get the instruction before it if it's a terminator.
193 MachineInstr *SecondLastInst = I;
195 // If there are three terminators, we don't know what sort of block this is.
196 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
199 // If the block ends with NVPTX::GOTO and NVPTX:CBranch, handle it.
200 if (SecondLastInst->getOpcode() == NVPTX::CBranch &&
201 LastInst->getOpcode() == NVPTX::GOTO) {
202 TBB = SecondLastInst->getOperand(1).getMBB();
203 Cond.push_back(SecondLastInst->getOperand(0));
204 FBB = LastInst->getOperand(0).getMBB();
208 // If the block ends with two NVPTX:GOTOs, handle it. The second one is not
209 // executed, so remove it.
210 if (SecondLastInst->getOpcode() == NVPTX::GOTO &&
211 LastInst->getOpcode() == NVPTX::GOTO) {
212 TBB = SecondLastInst->getOperand(0).getMBB();
215 I->eraseFromParent();
219 // Otherwise, can't handle this.
223 unsigned NVPTXInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
224 MachineBasicBlock::iterator I = MBB.end();
225 if (I == MBB.begin())
228 if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() != NVPTX::CBranch)
231 // Remove the branch.
232 I->eraseFromParent();
236 if (I == MBB.begin())
239 if (I->getOpcode() != NVPTX::CBranch)
242 // Remove the branch.
243 I->eraseFromParent();
247 unsigned NVPTXInstrInfo::InsertBranch(
248 MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
249 const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const {
250 // Shouldn't be a fall through.
251 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
252 assert((Cond.size() == 1 || Cond.size() == 0) &&
253 "NVPTX branch conditions have two components!");
257 if (Cond.empty()) // Unconditional branch
258 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB);
259 else // Conditional branch
260 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg())
265 // Two-way Conditional Branch.
266 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
267 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB);