1 //===-- NVPTXISelDAGToDAG.cpp - A dag to dag inst selector for NVPTX ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the NVPTX target.
12 //===----------------------------------------------------------------------===//
14 #include "NVPTXISelDAGToDAG.h"
15 #include "llvm/IR/GlobalValue.h"
16 #include "llvm/IR/Instructions.h"
17 #include "llvm/Support/CommandLine.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Support/raw_ostream.h"
21 #include "llvm/Target/TargetIntrinsicInfo.h"
25 #define DEBUG_TYPE "nvptx-isel"
27 static cl::opt<int> UsePrecDivF32(
28 "nvptx-prec-divf32", cl::ZeroOrMore, cl::Hidden,
29 cl::desc("NVPTX Specifies: 0 use div.approx, 1 use div.full, 2 use"
30 " IEEE Compliant F32 div.rnd if available."),
34 UsePrecSqrtF32("nvptx-prec-sqrtf32", cl::Hidden,
35 cl::desc("NVPTX Specific: 0 use sqrt.approx, 1 use sqrt.rn."),
39 FtzEnabled("nvptx-f32ftz", cl::ZeroOrMore, cl::Hidden,
40 cl::desc("NVPTX Specific: Flush f32 subnormals to sign-preserving zero."),
44 /// createNVPTXISelDag - This pass converts a legalized DAG into a
45 /// NVPTX-specific DAG, ready for instruction scheduling.
46 FunctionPass *llvm::createNVPTXISelDag(NVPTXTargetMachine &TM,
47 llvm::CodeGenOpt::Level OptLevel) {
48 return new NVPTXDAGToDAGISel(TM, OptLevel);
51 NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
52 CodeGenOpt::Level OptLevel)
53 : SelectionDAGISel(tm, OptLevel), TM(tm) {
54 doMulWide = (OptLevel > 0);
57 bool NVPTXDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
58 Subtarget = &static_cast<const NVPTXSubtarget &>(MF.getSubtarget());
59 return SelectionDAGISel::runOnMachineFunction(MF);
62 int NVPTXDAGToDAGISel::getDivF32Level() const {
63 if (UsePrecDivF32.getNumOccurrences() > 0) {
64 // If nvptx-prec-div32=N is used on the command-line, always honor it
67 // Otherwise, use div.approx if fast math is enabled
68 if (TM.Options.UnsafeFPMath)
75 bool NVPTXDAGToDAGISel::usePrecSqrtF32() const {
76 if (UsePrecSqrtF32.getNumOccurrences() > 0) {
77 // If nvptx-prec-sqrtf32 is used on the command-line, always honor it
78 return UsePrecSqrtF32;
80 // Otherwise, use sqrt.approx if fast math is enabled
81 if (TM.Options.UnsafeFPMath)
88 bool NVPTXDAGToDAGISel::useF32FTZ() const {
89 if (FtzEnabled.getNumOccurrences() > 0) {
90 // If nvptx-f32ftz is used on the command-line, always honor it
93 const Function *F = MF->getFunction();
94 // Otherwise, check for an nvptx-f32ftz attribute on the function
95 if (F->hasFnAttribute("nvptx-f32ftz"))
96 return F->getFnAttribute("nvptx-f32ftz").getValueAsString() == "true";
102 bool NVPTXDAGToDAGISel::allowFMA() const {
103 const NVPTXTargetLowering *TL = Subtarget->getTargetLowering();
104 return TL->allowFMA(*MF, OptLevel);
107 /// Select - Select instructions not customized! Used for
108 /// expanded, promoted and normal instructions.
109 SDNode *NVPTXDAGToDAGISel::Select(SDNode *N) {
111 if (N->isMachineOpcode()) {
113 return nullptr; // Already selected.
116 SDNode *ResNode = nullptr;
117 switch (N->getOpcode()) {
119 ResNode = SelectLoad(N);
122 ResNode = SelectStore(N);
124 case NVPTXISD::LoadV2:
125 case NVPTXISD::LoadV4:
126 ResNode = SelectLoadVector(N);
128 case NVPTXISD::LDGV2:
129 case NVPTXISD::LDGV4:
130 case NVPTXISD::LDUV2:
131 case NVPTXISD::LDUV4:
132 ResNode = SelectLDGLDU(N);
134 case NVPTXISD::StoreV2:
135 case NVPTXISD::StoreV4:
136 ResNode = SelectStoreVector(N);
138 case NVPTXISD::LoadParam:
139 case NVPTXISD::LoadParamV2:
140 case NVPTXISD::LoadParamV4:
141 ResNode = SelectLoadParam(N);
143 case NVPTXISD::StoreRetval:
144 case NVPTXISD::StoreRetvalV2:
145 case NVPTXISD::StoreRetvalV4:
146 ResNode = SelectStoreRetval(N);
148 case NVPTXISD::StoreParam:
149 case NVPTXISD::StoreParamV2:
150 case NVPTXISD::StoreParamV4:
151 case NVPTXISD::StoreParamS32:
152 case NVPTXISD::StoreParamU32:
153 ResNode = SelectStoreParam(N);
155 case ISD::INTRINSIC_WO_CHAIN:
156 ResNode = SelectIntrinsicNoChain(N);
158 case ISD::INTRINSIC_W_CHAIN:
159 ResNode = SelectIntrinsicChain(N);
161 case NVPTXISD::Tex1DFloatS32:
162 case NVPTXISD::Tex1DFloatFloat:
163 case NVPTXISD::Tex1DFloatFloatLevel:
164 case NVPTXISD::Tex1DFloatFloatGrad:
165 case NVPTXISD::Tex1DS32S32:
166 case NVPTXISD::Tex1DS32Float:
167 case NVPTXISD::Tex1DS32FloatLevel:
168 case NVPTXISD::Tex1DS32FloatGrad:
169 case NVPTXISD::Tex1DU32S32:
170 case NVPTXISD::Tex1DU32Float:
171 case NVPTXISD::Tex1DU32FloatLevel:
172 case NVPTXISD::Tex1DU32FloatGrad:
173 case NVPTXISD::Tex1DArrayFloatS32:
174 case NVPTXISD::Tex1DArrayFloatFloat:
175 case NVPTXISD::Tex1DArrayFloatFloatLevel:
176 case NVPTXISD::Tex1DArrayFloatFloatGrad:
177 case NVPTXISD::Tex1DArrayS32S32:
178 case NVPTXISD::Tex1DArrayS32Float:
179 case NVPTXISD::Tex1DArrayS32FloatLevel:
180 case NVPTXISD::Tex1DArrayS32FloatGrad:
181 case NVPTXISD::Tex1DArrayU32S32:
182 case NVPTXISD::Tex1DArrayU32Float:
183 case NVPTXISD::Tex1DArrayU32FloatLevel:
184 case NVPTXISD::Tex1DArrayU32FloatGrad:
185 case NVPTXISD::Tex2DFloatS32:
186 case NVPTXISD::Tex2DFloatFloat:
187 case NVPTXISD::Tex2DFloatFloatLevel:
188 case NVPTXISD::Tex2DFloatFloatGrad:
189 case NVPTXISD::Tex2DS32S32:
190 case NVPTXISD::Tex2DS32Float:
191 case NVPTXISD::Tex2DS32FloatLevel:
192 case NVPTXISD::Tex2DS32FloatGrad:
193 case NVPTXISD::Tex2DU32S32:
194 case NVPTXISD::Tex2DU32Float:
195 case NVPTXISD::Tex2DU32FloatLevel:
196 case NVPTXISD::Tex2DU32FloatGrad:
197 case NVPTXISD::Tex2DArrayFloatS32:
198 case NVPTXISD::Tex2DArrayFloatFloat:
199 case NVPTXISD::Tex2DArrayFloatFloatLevel:
200 case NVPTXISD::Tex2DArrayFloatFloatGrad:
201 case NVPTXISD::Tex2DArrayS32S32:
202 case NVPTXISD::Tex2DArrayS32Float:
203 case NVPTXISD::Tex2DArrayS32FloatLevel:
204 case NVPTXISD::Tex2DArrayS32FloatGrad:
205 case NVPTXISD::Tex2DArrayU32S32:
206 case NVPTXISD::Tex2DArrayU32Float:
207 case NVPTXISD::Tex2DArrayU32FloatLevel:
208 case NVPTXISD::Tex2DArrayU32FloatGrad:
209 case NVPTXISD::Tex3DFloatS32:
210 case NVPTXISD::Tex3DFloatFloat:
211 case NVPTXISD::Tex3DFloatFloatLevel:
212 case NVPTXISD::Tex3DFloatFloatGrad:
213 case NVPTXISD::Tex3DS32S32:
214 case NVPTXISD::Tex3DS32Float:
215 case NVPTXISD::Tex3DS32FloatLevel:
216 case NVPTXISD::Tex3DS32FloatGrad:
217 case NVPTXISD::Tex3DU32S32:
218 case NVPTXISD::Tex3DU32Float:
219 case NVPTXISD::Tex3DU32FloatLevel:
220 case NVPTXISD::Tex3DU32FloatGrad:
221 case NVPTXISD::TexCubeFloatFloat:
222 case NVPTXISD::TexCubeFloatFloatLevel:
223 case NVPTXISD::TexCubeS32Float:
224 case NVPTXISD::TexCubeS32FloatLevel:
225 case NVPTXISD::TexCubeU32Float:
226 case NVPTXISD::TexCubeU32FloatLevel:
227 case NVPTXISD::TexCubeArrayFloatFloat:
228 case NVPTXISD::TexCubeArrayFloatFloatLevel:
229 case NVPTXISD::TexCubeArrayS32Float:
230 case NVPTXISD::TexCubeArrayS32FloatLevel:
231 case NVPTXISD::TexCubeArrayU32Float:
232 case NVPTXISD::TexCubeArrayU32FloatLevel:
233 case NVPTXISD::Tld4R2DFloatFloat:
234 case NVPTXISD::Tld4G2DFloatFloat:
235 case NVPTXISD::Tld4B2DFloatFloat:
236 case NVPTXISD::Tld4A2DFloatFloat:
237 case NVPTXISD::Tld4R2DS64Float:
238 case NVPTXISD::Tld4G2DS64Float:
239 case NVPTXISD::Tld4B2DS64Float:
240 case NVPTXISD::Tld4A2DS64Float:
241 case NVPTXISD::Tld4R2DU64Float:
242 case NVPTXISD::Tld4G2DU64Float:
243 case NVPTXISD::Tld4B2DU64Float:
244 case NVPTXISD::Tld4A2DU64Float:
245 case NVPTXISD::TexUnified1DFloatS32:
246 case NVPTXISD::TexUnified1DFloatFloat:
247 case NVPTXISD::TexUnified1DFloatFloatLevel:
248 case NVPTXISD::TexUnified1DFloatFloatGrad:
249 case NVPTXISD::TexUnified1DS32S32:
250 case NVPTXISD::TexUnified1DS32Float:
251 case NVPTXISD::TexUnified1DS32FloatLevel:
252 case NVPTXISD::TexUnified1DS32FloatGrad:
253 case NVPTXISD::TexUnified1DU32S32:
254 case NVPTXISD::TexUnified1DU32Float:
255 case NVPTXISD::TexUnified1DU32FloatLevel:
256 case NVPTXISD::TexUnified1DU32FloatGrad:
257 case NVPTXISD::TexUnified1DArrayFloatS32:
258 case NVPTXISD::TexUnified1DArrayFloatFloat:
259 case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
260 case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
261 case NVPTXISD::TexUnified1DArrayS32S32:
262 case NVPTXISD::TexUnified1DArrayS32Float:
263 case NVPTXISD::TexUnified1DArrayS32FloatLevel:
264 case NVPTXISD::TexUnified1DArrayS32FloatGrad:
265 case NVPTXISD::TexUnified1DArrayU32S32:
266 case NVPTXISD::TexUnified1DArrayU32Float:
267 case NVPTXISD::TexUnified1DArrayU32FloatLevel:
268 case NVPTXISD::TexUnified1DArrayU32FloatGrad:
269 case NVPTXISD::TexUnified2DFloatS32:
270 case NVPTXISD::TexUnified2DFloatFloat:
271 case NVPTXISD::TexUnified2DFloatFloatLevel:
272 case NVPTXISD::TexUnified2DFloatFloatGrad:
273 case NVPTXISD::TexUnified2DS32S32:
274 case NVPTXISD::TexUnified2DS32Float:
275 case NVPTXISD::TexUnified2DS32FloatLevel:
276 case NVPTXISD::TexUnified2DS32FloatGrad:
277 case NVPTXISD::TexUnified2DU32S32:
278 case NVPTXISD::TexUnified2DU32Float:
279 case NVPTXISD::TexUnified2DU32FloatLevel:
280 case NVPTXISD::TexUnified2DU32FloatGrad:
281 case NVPTXISD::TexUnified2DArrayFloatS32:
282 case NVPTXISD::TexUnified2DArrayFloatFloat:
283 case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
284 case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
285 case NVPTXISD::TexUnified2DArrayS32S32:
286 case NVPTXISD::TexUnified2DArrayS32Float:
287 case NVPTXISD::TexUnified2DArrayS32FloatLevel:
288 case NVPTXISD::TexUnified2DArrayS32FloatGrad:
289 case NVPTXISD::TexUnified2DArrayU32S32:
290 case NVPTXISD::TexUnified2DArrayU32Float:
291 case NVPTXISD::TexUnified2DArrayU32FloatLevel:
292 case NVPTXISD::TexUnified2DArrayU32FloatGrad:
293 case NVPTXISD::TexUnified3DFloatS32:
294 case NVPTXISD::TexUnified3DFloatFloat:
295 case NVPTXISD::TexUnified3DFloatFloatLevel:
296 case NVPTXISD::TexUnified3DFloatFloatGrad:
297 case NVPTXISD::TexUnified3DS32S32:
298 case NVPTXISD::TexUnified3DS32Float:
299 case NVPTXISD::TexUnified3DS32FloatLevel:
300 case NVPTXISD::TexUnified3DS32FloatGrad:
301 case NVPTXISD::TexUnified3DU32S32:
302 case NVPTXISD::TexUnified3DU32Float:
303 case NVPTXISD::TexUnified3DU32FloatLevel:
304 case NVPTXISD::TexUnified3DU32FloatGrad:
305 case NVPTXISD::TexUnifiedCubeFloatFloat:
306 case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
307 case NVPTXISD::TexUnifiedCubeS32Float:
308 case NVPTXISD::TexUnifiedCubeS32FloatLevel:
309 case NVPTXISD::TexUnifiedCubeU32Float:
310 case NVPTXISD::TexUnifiedCubeU32FloatLevel:
311 case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
312 case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
313 case NVPTXISD::TexUnifiedCubeArrayS32Float:
314 case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
315 case NVPTXISD::TexUnifiedCubeArrayU32Float:
316 case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
317 case NVPTXISD::Tld4UnifiedR2DFloatFloat:
318 case NVPTXISD::Tld4UnifiedG2DFloatFloat:
319 case NVPTXISD::Tld4UnifiedB2DFloatFloat:
320 case NVPTXISD::Tld4UnifiedA2DFloatFloat:
321 case NVPTXISD::Tld4UnifiedR2DS64Float:
322 case NVPTXISD::Tld4UnifiedG2DS64Float:
323 case NVPTXISD::Tld4UnifiedB2DS64Float:
324 case NVPTXISD::Tld4UnifiedA2DS64Float:
325 case NVPTXISD::Tld4UnifiedR2DU64Float:
326 case NVPTXISD::Tld4UnifiedG2DU64Float:
327 case NVPTXISD::Tld4UnifiedB2DU64Float:
328 case NVPTXISD::Tld4UnifiedA2DU64Float:
329 ResNode = SelectTextureIntrinsic(N);
331 case NVPTXISD::Suld1DI8Clamp:
332 case NVPTXISD::Suld1DI16Clamp:
333 case NVPTXISD::Suld1DI32Clamp:
334 case NVPTXISD::Suld1DI64Clamp:
335 case NVPTXISD::Suld1DV2I8Clamp:
336 case NVPTXISD::Suld1DV2I16Clamp:
337 case NVPTXISD::Suld1DV2I32Clamp:
338 case NVPTXISD::Suld1DV2I64Clamp:
339 case NVPTXISD::Suld1DV4I8Clamp:
340 case NVPTXISD::Suld1DV4I16Clamp:
341 case NVPTXISD::Suld1DV4I32Clamp:
342 case NVPTXISD::Suld1DArrayI8Clamp:
343 case NVPTXISD::Suld1DArrayI16Clamp:
344 case NVPTXISD::Suld1DArrayI32Clamp:
345 case NVPTXISD::Suld1DArrayI64Clamp:
346 case NVPTXISD::Suld1DArrayV2I8Clamp:
347 case NVPTXISD::Suld1DArrayV2I16Clamp:
348 case NVPTXISD::Suld1DArrayV2I32Clamp:
349 case NVPTXISD::Suld1DArrayV2I64Clamp:
350 case NVPTXISD::Suld1DArrayV4I8Clamp:
351 case NVPTXISD::Suld1DArrayV4I16Clamp:
352 case NVPTXISD::Suld1DArrayV4I32Clamp:
353 case NVPTXISD::Suld2DI8Clamp:
354 case NVPTXISD::Suld2DI16Clamp:
355 case NVPTXISD::Suld2DI32Clamp:
356 case NVPTXISD::Suld2DI64Clamp:
357 case NVPTXISD::Suld2DV2I8Clamp:
358 case NVPTXISD::Suld2DV2I16Clamp:
359 case NVPTXISD::Suld2DV2I32Clamp:
360 case NVPTXISD::Suld2DV2I64Clamp:
361 case NVPTXISD::Suld2DV4I8Clamp:
362 case NVPTXISD::Suld2DV4I16Clamp:
363 case NVPTXISD::Suld2DV4I32Clamp:
364 case NVPTXISD::Suld2DArrayI8Clamp:
365 case NVPTXISD::Suld2DArrayI16Clamp:
366 case NVPTXISD::Suld2DArrayI32Clamp:
367 case NVPTXISD::Suld2DArrayI64Clamp:
368 case NVPTXISD::Suld2DArrayV2I8Clamp:
369 case NVPTXISD::Suld2DArrayV2I16Clamp:
370 case NVPTXISD::Suld2DArrayV2I32Clamp:
371 case NVPTXISD::Suld2DArrayV2I64Clamp:
372 case NVPTXISD::Suld2DArrayV4I8Clamp:
373 case NVPTXISD::Suld2DArrayV4I16Clamp:
374 case NVPTXISD::Suld2DArrayV4I32Clamp:
375 case NVPTXISD::Suld3DI8Clamp:
376 case NVPTXISD::Suld3DI16Clamp:
377 case NVPTXISD::Suld3DI32Clamp:
378 case NVPTXISD::Suld3DI64Clamp:
379 case NVPTXISD::Suld3DV2I8Clamp:
380 case NVPTXISD::Suld3DV2I16Clamp:
381 case NVPTXISD::Suld3DV2I32Clamp:
382 case NVPTXISD::Suld3DV2I64Clamp:
383 case NVPTXISD::Suld3DV4I8Clamp:
384 case NVPTXISD::Suld3DV4I16Clamp:
385 case NVPTXISD::Suld3DV4I32Clamp:
386 case NVPTXISD::Suld1DI8Trap:
387 case NVPTXISD::Suld1DI16Trap:
388 case NVPTXISD::Suld1DI32Trap:
389 case NVPTXISD::Suld1DI64Trap:
390 case NVPTXISD::Suld1DV2I8Trap:
391 case NVPTXISD::Suld1DV2I16Trap:
392 case NVPTXISD::Suld1DV2I32Trap:
393 case NVPTXISD::Suld1DV2I64Trap:
394 case NVPTXISD::Suld1DV4I8Trap:
395 case NVPTXISD::Suld1DV4I16Trap:
396 case NVPTXISD::Suld1DV4I32Trap:
397 case NVPTXISD::Suld1DArrayI8Trap:
398 case NVPTXISD::Suld1DArrayI16Trap:
399 case NVPTXISD::Suld1DArrayI32Trap:
400 case NVPTXISD::Suld1DArrayI64Trap:
401 case NVPTXISD::Suld1DArrayV2I8Trap:
402 case NVPTXISD::Suld1DArrayV2I16Trap:
403 case NVPTXISD::Suld1DArrayV2I32Trap:
404 case NVPTXISD::Suld1DArrayV2I64Trap:
405 case NVPTXISD::Suld1DArrayV4I8Trap:
406 case NVPTXISD::Suld1DArrayV4I16Trap:
407 case NVPTXISD::Suld1DArrayV4I32Trap:
408 case NVPTXISD::Suld2DI8Trap:
409 case NVPTXISD::Suld2DI16Trap:
410 case NVPTXISD::Suld2DI32Trap:
411 case NVPTXISD::Suld2DI64Trap:
412 case NVPTXISD::Suld2DV2I8Trap:
413 case NVPTXISD::Suld2DV2I16Trap:
414 case NVPTXISD::Suld2DV2I32Trap:
415 case NVPTXISD::Suld2DV2I64Trap:
416 case NVPTXISD::Suld2DV4I8Trap:
417 case NVPTXISD::Suld2DV4I16Trap:
418 case NVPTXISD::Suld2DV4I32Trap:
419 case NVPTXISD::Suld2DArrayI8Trap:
420 case NVPTXISD::Suld2DArrayI16Trap:
421 case NVPTXISD::Suld2DArrayI32Trap:
422 case NVPTXISD::Suld2DArrayI64Trap:
423 case NVPTXISD::Suld2DArrayV2I8Trap:
424 case NVPTXISD::Suld2DArrayV2I16Trap:
425 case NVPTXISD::Suld2DArrayV2I32Trap:
426 case NVPTXISD::Suld2DArrayV2I64Trap:
427 case NVPTXISD::Suld2DArrayV4I8Trap:
428 case NVPTXISD::Suld2DArrayV4I16Trap:
429 case NVPTXISD::Suld2DArrayV4I32Trap:
430 case NVPTXISD::Suld3DI8Trap:
431 case NVPTXISD::Suld3DI16Trap:
432 case NVPTXISD::Suld3DI32Trap:
433 case NVPTXISD::Suld3DI64Trap:
434 case NVPTXISD::Suld3DV2I8Trap:
435 case NVPTXISD::Suld3DV2I16Trap:
436 case NVPTXISD::Suld3DV2I32Trap:
437 case NVPTXISD::Suld3DV2I64Trap:
438 case NVPTXISD::Suld3DV4I8Trap:
439 case NVPTXISD::Suld3DV4I16Trap:
440 case NVPTXISD::Suld3DV4I32Trap:
441 case NVPTXISD::Suld1DI8Zero:
442 case NVPTXISD::Suld1DI16Zero:
443 case NVPTXISD::Suld1DI32Zero:
444 case NVPTXISD::Suld1DI64Zero:
445 case NVPTXISD::Suld1DV2I8Zero:
446 case NVPTXISD::Suld1DV2I16Zero:
447 case NVPTXISD::Suld1DV2I32Zero:
448 case NVPTXISD::Suld1DV2I64Zero:
449 case NVPTXISD::Suld1DV4I8Zero:
450 case NVPTXISD::Suld1DV4I16Zero:
451 case NVPTXISD::Suld1DV4I32Zero:
452 case NVPTXISD::Suld1DArrayI8Zero:
453 case NVPTXISD::Suld1DArrayI16Zero:
454 case NVPTXISD::Suld1DArrayI32Zero:
455 case NVPTXISD::Suld1DArrayI64Zero:
456 case NVPTXISD::Suld1DArrayV2I8Zero:
457 case NVPTXISD::Suld1DArrayV2I16Zero:
458 case NVPTXISD::Suld1DArrayV2I32Zero:
459 case NVPTXISD::Suld1DArrayV2I64Zero:
460 case NVPTXISD::Suld1DArrayV4I8Zero:
461 case NVPTXISD::Suld1DArrayV4I16Zero:
462 case NVPTXISD::Suld1DArrayV4I32Zero:
463 case NVPTXISD::Suld2DI8Zero:
464 case NVPTXISD::Suld2DI16Zero:
465 case NVPTXISD::Suld2DI32Zero:
466 case NVPTXISD::Suld2DI64Zero:
467 case NVPTXISD::Suld2DV2I8Zero:
468 case NVPTXISD::Suld2DV2I16Zero:
469 case NVPTXISD::Suld2DV2I32Zero:
470 case NVPTXISD::Suld2DV2I64Zero:
471 case NVPTXISD::Suld2DV4I8Zero:
472 case NVPTXISD::Suld2DV4I16Zero:
473 case NVPTXISD::Suld2DV4I32Zero:
474 case NVPTXISD::Suld2DArrayI8Zero:
475 case NVPTXISD::Suld2DArrayI16Zero:
476 case NVPTXISD::Suld2DArrayI32Zero:
477 case NVPTXISD::Suld2DArrayI64Zero:
478 case NVPTXISD::Suld2DArrayV2I8Zero:
479 case NVPTXISD::Suld2DArrayV2I16Zero:
480 case NVPTXISD::Suld2DArrayV2I32Zero:
481 case NVPTXISD::Suld2DArrayV2I64Zero:
482 case NVPTXISD::Suld2DArrayV4I8Zero:
483 case NVPTXISD::Suld2DArrayV4I16Zero:
484 case NVPTXISD::Suld2DArrayV4I32Zero:
485 case NVPTXISD::Suld3DI8Zero:
486 case NVPTXISD::Suld3DI16Zero:
487 case NVPTXISD::Suld3DI32Zero:
488 case NVPTXISD::Suld3DI64Zero:
489 case NVPTXISD::Suld3DV2I8Zero:
490 case NVPTXISD::Suld3DV2I16Zero:
491 case NVPTXISD::Suld3DV2I32Zero:
492 case NVPTXISD::Suld3DV2I64Zero:
493 case NVPTXISD::Suld3DV4I8Zero:
494 case NVPTXISD::Suld3DV4I16Zero:
495 case NVPTXISD::Suld3DV4I32Zero:
496 ResNode = SelectSurfaceIntrinsic(N);
502 ResNode = SelectBFE(N);
504 case ISD::ADDRSPACECAST:
505 ResNode = SelectAddrSpaceCast(N);
512 return SelectCode(N);
515 SDNode *NVPTXDAGToDAGISel::SelectIntrinsicChain(SDNode *N) {
516 unsigned IID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
520 case Intrinsic::nvvm_ldg_global_f:
521 case Intrinsic::nvvm_ldg_global_i:
522 case Intrinsic::nvvm_ldg_global_p:
523 case Intrinsic::nvvm_ldu_global_f:
524 case Intrinsic::nvvm_ldu_global_i:
525 case Intrinsic::nvvm_ldu_global_p:
526 return SelectLDGLDU(N);
530 static unsigned int getCodeAddrSpace(MemSDNode *N) {
531 const Value *Src = N->getMemOperand()->getValue();
534 return NVPTX::PTXLdStInstCode::GENERIC;
536 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) {
537 switch (PT->getAddressSpace()) {
538 case llvm::ADDRESS_SPACE_LOCAL: return NVPTX::PTXLdStInstCode::LOCAL;
539 case llvm::ADDRESS_SPACE_GLOBAL: return NVPTX::PTXLdStInstCode::GLOBAL;
540 case llvm::ADDRESS_SPACE_SHARED: return NVPTX::PTXLdStInstCode::SHARED;
541 case llvm::ADDRESS_SPACE_GENERIC: return NVPTX::PTXLdStInstCode::GENERIC;
542 case llvm::ADDRESS_SPACE_PARAM: return NVPTX::PTXLdStInstCode::PARAM;
543 case llvm::ADDRESS_SPACE_CONST: return NVPTX::PTXLdStInstCode::CONSTANT;
547 return NVPTX::PTXLdStInstCode::GENERIC;
550 SDNode *NVPTXDAGToDAGISel::SelectIntrinsicNoChain(SDNode *N) {
551 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
555 case Intrinsic::nvvm_texsurf_handle_internal:
556 return SelectTexSurfHandle(N);
560 SDNode *NVPTXDAGToDAGISel::SelectTexSurfHandle(SDNode *N) {
561 // Op 0 is the intrinsic ID
562 SDValue Wrapper = N->getOperand(1);
563 SDValue GlobalVal = Wrapper.getOperand(0);
564 return CurDAG->getMachineNode(NVPTX::texsurf_handles, SDLoc(N), MVT::i64,
568 SDNode *NVPTXDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
569 SDValue Src = N->getOperand(0);
570 AddrSpaceCastSDNode *CastN = cast<AddrSpaceCastSDNode>(N);
571 unsigned SrcAddrSpace = CastN->getSrcAddressSpace();
572 unsigned DstAddrSpace = CastN->getDestAddressSpace();
574 assert(SrcAddrSpace != DstAddrSpace &&
575 "addrspacecast must be between different address spaces");
577 if (DstAddrSpace == ADDRESS_SPACE_GENERIC) {
578 // Specific to generic
580 switch (SrcAddrSpace) {
581 default: report_fatal_error("Bad address space in addrspacecast");
582 case ADDRESS_SPACE_GLOBAL:
583 Opc = TM.is64Bit() ? NVPTX::cvta_global_yes_64 : NVPTX::cvta_global_yes;
585 case ADDRESS_SPACE_SHARED:
586 Opc = TM.is64Bit() ? NVPTX::cvta_shared_yes_64 : NVPTX::cvta_shared_yes;
588 case ADDRESS_SPACE_CONST:
589 Opc = TM.is64Bit() ? NVPTX::cvta_const_yes_64 : NVPTX::cvta_const_yes;
591 case ADDRESS_SPACE_LOCAL:
592 Opc = TM.is64Bit() ? NVPTX::cvta_local_yes_64 : NVPTX::cvta_local_yes;
595 return CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), Src);
597 // Generic to specific
598 if (SrcAddrSpace != 0)
599 report_fatal_error("Cannot cast between two non-generic address spaces");
601 switch (DstAddrSpace) {
602 default: report_fatal_error("Bad address space in addrspacecast");
603 case ADDRESS_SPACE_GLOBAL:
604 Opc = TM.is64Bit() ? NVPTX::cvta_to_global_yes_64
605 : NVPTX::cvta_to_global_yes;
607 case ADDRESS_SPACE_SHARED:
608 Opc = TM.is64Bit() ? NVPTX::cvta_to_shared_yes_64
609 : NVPTX::cvta_to_shared_yes;
611 case ADDRESS_SPACE_CONST:
613 TM.is64Bit() ? NVPTX::cvta_to_const_yes_64 : NVPTX::cvta_to_const_yes;
615 case ADDRESS_SPACE_LOCAL:
617 TM.is64Bit() ? NVPTX::cvta_to_local_yes_64 : NVPTX::cvta_to_local_yes;
620 return CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), Src);
624 SDNode *NVPTXDAGToDAGISel::SelectLoad(SDNode *N) {
626 LoadSDNode *LD = cast<LoadSDNode>(N);
627 EVT LoadedVT = LD->getMemoryVT();
628 SDNode *NVPTXLD = nullptr;
630 // do not support pre/post inc/dec
634 if (!LoadedVT.isSimple())
637 // Address Space Setting
638 unsigned int codeAddrSpace = getCodeAddrSpace(LD);
641 // - .volatile is only availalble for .global and .shared
642 bool isVolatile = LD->isVolatile();
643 if (codeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
644 codeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
645 codeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
649 MVT SimpleVT = LoadedVT.getSimpleVT();
650 unsigned vecType = NVPTX::PTXLdStInstCode::Scalar;
651 if (SimpleVT.isVector()) {
652 unsigned num = SimpleVT.getVectorNumElements();
654 vecType = NVPTX::PTXLdStInstCode::V2;
656 vecType = NVPTX::PTXLdStInstCode::V4;
661 // Type Setting: fromType + fromTypeWidth
663 // Sign : ISD::SEXTLOAD
664 // Unsign : ISD::ZEXTLOAD, ISD::NON_EXTLOAD or ISD::EXTLOAD and the
666 // Float : ISD::NON_EXTLOAD or ISD::EXTLOAD and the type is float
667 MVT ScalarVT = SimpleVT.getScalarType();
668 // Read at least 8 bits (predicates are stored as 8-bit values)
669 unsigned fromTypeWidth = std::max(8U, ScalarVT.getSizeInBits());
670 unsigned int fromType;
671 if ((LD->getExtensionType() == ISD::SEXTLOAD))
672 fromType = NVPTX::PTXLdStInstCode::Signed;
673 else if (ScalarVT.isFloatingPoint())
674 fromType = NVPTX::PTXLdStInstCode::Float;
676 fromType = NVPTX::PTXLdStInstCode::Unsigned;
678 // Create the machine instruction DAG
679 SDValue Chain = N->getOperand(0);
680 SDValue N1 = N->getOperand(1);
682 SDValue Offset, Base;
684 MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy;
686 if (SelectDirectAddr(N1, Addr)) {
689 Opcode = NVPTX::LD_i8_avar;
692 Opcode = NVPTX::LD_i16_avar;
695 Opcode = NVPTX::LD_i32_avar;
698 Opcode = NVPTX::LD_i64_avar;
701 Opcode = NVPTX::LD_f32_avar;
704 Opcode = NVPTX::LD_f64_avar;
709 SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
710 getI32Imm(vecType), getI32Imm(fromType),
711 getI32Imm(fromTypeWidth), Addr, Chain };
712 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
713 } else if (TM.is64Bit() ? SelectADDRsi64(N1.getNode(), N1, Base, Offset)
714 : SelectADDRsi(N1.getNode(), N1, Base, Offset)) {
717 Opcode = NVPTX::LD_i8_asi;
720 Opcode = NVPTX::LD_i16_asi;
723 Opcode = NVPTX::LD_i32_asi;
726 Opcode = NVPTX::LD_i64_asi;
729 Opcode = NVPTX::LD_f32_asi;
732 Opcode = NVPTX::LD_f64_asi;
737 SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
738 getI32Imm(vecType), getI32Imm(fromType),
739 getI32Imm(fromTypeWidth), Base, Offset, Chain };
740 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
741 } else if (TM.is64Bit() ? SelectADDRri64(N1.getNode(), N1, Base, Offset)
742 : SelectADDRri(N1.getNode(), N1, Base, Offset)) {
746 Opcode = NVPTX::LD_i8_ari_64;
749 Opcode = NVPTX::LD_i16_ari_64;
752 Opcode = NVPTX::LD_i32_ari_64;
755 Opcode = NVPTX::LD_i64_ari_64;
758 Opcode = NVPTX::LD_f32_ari_64;
761 Opcode = NVPTX::LD_f64_ari_64;
769 Opcode = NVPTX::LD_i8_ari;
772 Opcode = NVPTX::LD_i16_ari;
775 Opcode = NVPTX::LD_i32_ari;
778 Opcode = NVPTX::LD_i64_ari;
781 Opcode = NVPTX::LD_f32_ari;
784 Opcode = NVPTX::LD_f64_ari;
790 SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
791 getI32Imm(vecType), getI32Imm(fromType),
792 getI32Imm(fromTypeWidth), Base, Offset, Chain };
793 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
798 Opcode = NVPTX::LD_i8_areg_64;
801 Opcode = NVPTX::LD_i16_areg_64;
804 Opcode = NVPTX::LD_i32_areg_64;
807 Opcode = NVPTX::LD_i64_areg_64;
810 Opcode = NVPTX::LD_f32_areg_64;
813 Opcode = NVPTX::LD_f64_areg_64;
821 Opcode = NVPTX::LD_i8_areg;
824 Opcode = NVPTX::LD_i16_areg;
827 Opcode = NVPTX::LD_i32_areg;
830 Opcode = NVPTX::LD_i64_areg;
833 Opcode = NVPTX::LD_f32_areg;
836 Opcode = NVPTX::LD_f64_areg;
842 SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
843 getI32Imm(vecType), getI32Imm(fromType),
844 getI32Imm(fromTypeWidth), N1, Chain };
845 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
849 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
850 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
851 cast<MachineSDNode>(NVPTXLD)->setMemRefs(MemRefs0, MemRefs0 + 1);
857 SDNode *NVPTXDAGToDAGISel::SelectLoadVector(SDNode *N) {
859 SDValue Chain = N->getOperand(0);
860 SDValue Op1 = N->getOperand(1);
861 SDValue Addr, Offset, Base;
865 MemSDNode *MemSD = cast<MemSDNode>(N);
866 EVT LoadedVT = MemSD->getMemoryVT();
868 if (!LoadedVT.isSimple())
871 // Address Space Setting
872 unsigned int CodeAddrSpace = getCodeAddrSpace(MemSD);
875 // - .volatile is only availalble for .global and .shared
876 bool IsVolatile = MemSD->isVolatile();
877 if (CodeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
878 CodeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
879 CodeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
883 MVT SimpleVT = LoadedVT.getSimpleVT();
885 // Type Setting: fromType + fromTypeWidth
887 // Sign : ISD::SEXTLOAD
888 // Unsign : ISD::ZEXTLOAD, ISD::NON_EXTLOAD or ISD::EXTLOAD and the
890 // Float : ISD::NON_EXTLOAD or ISD::EXTLOAD and the type is float
891 MVT ScalarVT = SimpleVT.getScalarType();
892 // Read at least 8 bits (predicates are stored as 8-bit values)
893 unsigned FromTypeWidth = std::max(8U, ScalarVT.getSizeInBits());
894 unsigned int FromType;
895 // The last operand holds the original LoadSDNode::getExtensionType() value
896 unsigned ExtensionType = cast<ConstantSDNode>(
897 N->getOperand(N->getNumOperands() - 1))->getZExtValue();
898 if (ExtensionType == ISD::SEXTLOAD)
899 FromType = NVPTX::PTXLdStInstCode::Signed;
900 else if (ScalarVT.isFloatingPoint())
901 FromType = NVPTX::PTXLdStInstCode::Float;
903 FromType = NVPTX::PTXLdStInstCode::Unsigned;
907 switch (N->getOpcode()) {
908 case NVPTXISD::LoadV2:
909 VecType = NVPTX::PTXLdStInstCode::V2;
911 case NVPTXISD::LoadV4:
912 VecType = NVPTX::PTXLdStInstCode::V4;
918 EVT EltVT = N->getValueType(0);
920 if (SelectDirectAddr(Op1, Addr)) {
921 switch (N->getOpcode()) {
924 case NVPTXISD::LoadV2:
925 switch (EltVT.getSimpleVT().SimpleTy) {
929 Opcode = NVPTX::LDV_i8_v2_avar;
932 Opcode = NVPTX::LDV_i16_v2_avar;
935 Opcode = NVPTX::LDV_i32_v2_avar;
938 Opcode = NVPTX::LDV_i64_v2_avar;
941 Opcode = NVPTX::LDV_f32_v2_avar;
944 Opcode = NVPTX::LDV_f64_v2_avar;
948 case NVPTXISD::LoadV4:
949 switch (EltVT.getSimpleVT().SimpleTy) {
953 Opcode = NVPTX::LDV_i8_v4_avar;
956 Opcode = NVPTX::LDV_i16_v4_avar;
959 Opcode = NVPTX::LDV_i32_v4_avar;
962 Opcode = NVPTX::LDV_f32_v4_avar;
968 SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
969 getI32Imm(VecType), getI32Imm(FromType),
970 getI32Imm(FromTypeWidth), Addr, Chain };
971 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
972 } else if (TM.is64Bit() ? SelectADDRsi64(Op1.getNode(), Op1, Base, Offset)
973 : SelectADDRsi(Op1.getNode(), Op1, Base, Offset)) {
974 switch (N->getOpcode()) {
977 case NVPTXISD::LoadV2:
978 switch (EltVT.getSimpleVT().SimpleTy) {
982 Opcode = NVPTX::LDV_i8_v2_asi;
985 Opcode = NVPTX::LDV_i16_v2_asi;
988 Opcode = NVPTX::LDV_i32_v2_asi;
991 Opcode = NVPTX::LDV_i64_v2_asi;
994 Opcode = NVPTX::LDV_f32_v2_asi;
997 Opcode = NVPTX::LDV_f64_v2_asi;
1001 case NVPTXISD::LoadV4:
1002 switch (EltVT.getSimpleVT().SimpleTy) {
1006 Opcode = NVPTX::LDV_i8_v4_asi;
1009 Opcode = NVPTX::LDV_i16_v4_asi;
1012 Opcode = NVPTX::LDV_i32_v4_asi;
1015 Opcode = NVPTX::LDV_f32_v4_asi;
1021 SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
1022 getI32Imm(VecType), getI32Imm(FromType),
1023 getI32Imm(FromTypeWidth), Base, Offset, Chain };
1024 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1025 } else if (TM.is64Bit() ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
1026 : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
1028 switch (N->getOpcode()) {
1031 case NVPTXISD::LoadV2:
1032 switch (EltVT.getSimpleVT().SimpleTy) {
1036 Opcode = NVPTX::LDV_i8_v2_ari_64;
1039 Opcode = NVPTX::LDV_i16_v2_ari_64;
1042 Opcode = NVPTX::LDV_i32_v2_ari_64;
1045 Opcode = NVPTX::LDV_i64_v2_ari_64;
1048 Opcode = NVPTX::LDV_f32_v2_ari_64;
1051 Opcode = NVPTX::LDV_f64_v2_ari_64;
1055 case NVPTXISD::LoadV4:
1056 switch (EltVT.getSimpleVT().SimpleTy) {
1060 Opcode = NVPTX::LDV_i8_v4_ari_64;
1063 Opcode = NVPTX::LDV_i16_v4_ari_64;
1066 Opcode = NVPTX::LDV_i32_v4_ari_64;
1069 Opcode = NVPTX::LDV_f32_v4_ari_64;
1075 switch (N->getOpcode()) {
1078 case NVPTXISD::LoadV2:
1079 switch (EltVT.getSimpleVT().SimpleTy) {
1083 Opcode = NVPTX::LDV_i8_v2_ari;
1086 Opcode = NVPTX::LDV_i16_v2_ari;
1089 Opcode = NVPTX::LDV_i32_v2_ari;
1092 Opcode = NVPTX::LDV_i64_v2_ari;
1095 Opcode = NVPTX::LDV_f32_v2_ari;
1098 Opcode = NVPTX::LDV_f64_v2_ari;
1102 case NVPTXISD::LoadV4:
1103 switch (EltVT.getSimpleVT().SimpleTy) {
1107 Opcode = NVPTX::LDV_i8_v4_ari;
1110 Opcode = NVPTX::LDV_i16_v4_ari;
1113 Opcode = NVPTX::LDV_i32_v4_ari;
1116 Opcode = NVPTX::LDV_f32_v4_ari;
1123 SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
1124 getI32Imm(VecType), getI32Imm(FromType),
1125 getI32Imm(FromTypeWidth), Base, Offset, Chain };
1127 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1130 switch (N->getOpcode()) {
1133 case NVPTXISD::LoadV2:
1134 switch (EltVT.getSimpleVT().SimpleTy) {
1138 Opcode = NVPTX::LDV_i8_v2_areg_64;
1141 Opcode = NVPTX::LDV_i16_v2_areg_64;
1144 Opcode = NVPTX::LDV_i32_v2_areg_64;
1147 Opcode = NVPTX::LDV_i64_v2_areg_64;
1150 Opcode = NVPTX::LDV_f32_v2_areg_64;
1153 Opcode = NVPTX::LDV_f64_v2_areg_64;
1157 case NVPTXISD::LoadV4:
1158 switch (EltVT.getSimpleVT().SimpleTy) {
1162 Opcode = NVPTX::LDV_i8_v4_areg_64;
1165 Opcode = NVPTX::LDV_i16_v4_areg_64;
1168 Opcode = NVPTX::LDV_i32_v4_areg_64;
1171 Opcode = NVPTX::LDV_f32_v4_areg_64;
1177 switch (N->getOpcode()) {
1180 case NVPTXISD::LoadV2:
1181 switch (EltVT.getSimpleVT().SimpleTy) {
1185 Opcode = NVPTX::LDV_i8_v2_areg;
1188 Opcode = NVPTX::LDV_i16_v2_areg;
1191 Opcode = NVPTX::LDV_i32_v2_areg;
1194 Opcode = NVPTX::LDV_i64_v2_areg;
1197 Opcode = NVPTX::LDV_f32_v2_areg;
1200 Opcode = NVPTX::LDV_f64_v2_areg;
1204 case NVPTXISD::LoadV4:
1205 switch (EltVT.getSimpleVT().SimpleTy) {
1209 Opcode = NVPTX::LDV_i8_v4_areg;
1212 Opcode = NVPTX::LDV_i16_v4_areg;
1215 Opcode = NVPTX::LDV_i32_v4_areg;
1218 Opcode = NVPTX::LDV_f32_v4_areg;
1225 SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
1226 getI32Imm(VecType), getI32Imm(FromType),
1227 getI32Imm(FromTypeWidth), Op1, Chain };
1228 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1231 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
1232 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
1233 cast<MachineSDNode>(LD)->setMemRefs(MemRefs0, MemRefs0 + 1);
1238 SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(SDNode *N) {
1240 SDValue Chain = N->getOperand(0);
1245 // If this is an LDG intrinsic, the address is the third operand. Its its an
1246 // LDG/LDU SD node (from custom vector handling), then its the second operand
1247 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
1248 Op1 = N->getOperand(2);
1249 Mem = cast<MemIntrinsicSDNode>(N);
1250 unsigned IID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
1254 case Intrinsic::nvvm_ldg_global_f:
1255 case Intrinsic::nvvm_ldg_global_i:
1256 case Intrinsic::nvvm_ldg_global_p:
1259 case Intrinsic::nvvm_ldu_global_f:
1260 case Intrinsic::nvvm_ldu_global_i:
1261 case Intrinsic::nvvm_ldu_global_p:
1266 Op1 = N->getOperand(1);
1267 Mem = cast<MemSDNode>(N);
1273 SDValue Base, Offset, Addr;
1275 EVT EltVT = Mem->getMemoryVT();
1276 if (EltVT.isVector()) {
1277 EltVT = EltVT.getVectorElementType();
1280 if (SelectDirectAddr(Op1, Addr)) {
1281 switch (N->getOpcode()) {
1284 case ISD::INTRINSIC_W_CHAIN:
1286 switch (EltVT.getSimpleVT().SimpleTy) {
1290 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8avar;
1293 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16avar;
1296 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32avar;
1299 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64avar;
1302 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32avar;
1305 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64avar;
1309 switch (EltVT.getSimpleVT().SimpleTy) {
1313 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8avar;
1316 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16avar;
1319 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32avar;
1322 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64avar;
1325 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32avar;
1328 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64avar;
1333 case NVPTXISD::LDGV2:
1334 switch (EltVT.getSimpleVT().SimpleTy) {
1338 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_avar;
1341 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_avar;
1344 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_avar;
1347 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_avar;
1350 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_avar;
1353 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_avar;
1357 case NVPTXISD::LDUV2:
1358 switch (EltVT.getSimpleVT().SimpleTy) {
1362 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_avar;
1365 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_avar;
1368 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_avar;
1371 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_avar;
1374 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_avar;
1377 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_avar;
1381 case NVPTXISD::LDGV4:
1382 switch (EltVT.getSimpleVT().SimpleTy) {
1386 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_avar;
1389 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_avar;
1392 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_avar;
1395 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_avar;
1399 case NVPTXISD::LDUV4:
1400 switch (EltVT.getSimpleVT().SimpleTy) {
1404 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_avar;
1407 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_avar;
1410 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_avar;
1413 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_avar;
1419 SDValue Ops[] = { Addr, Chain };
1420 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1421 } else if (TM.is64Bit() ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
1422 : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
1424 switch (N->getOpcode()) {
1427 case ISD::INTRINSIC_W_CHAIN:
1429 switch (EltVT.getSimpleVT().SimpleTy) {
1433 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8ari64;
1436 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16ari64;
1439 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32ari64;
1442 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64ari64;
1445 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32ari64;
1448 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64ari64;
1452 switch (EltVT.getSimpleVT().SimpleTy) {
1456 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8ari64;
1459 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16ari64;
1462 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32ari64;
1465 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64ari64;
1468 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32ari64;
1471 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64ari64;
1476 case NVPTXISD::LDGV2:
1477 switch (EltVT.getSimpleVT().SimpleTy) {
1481 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_ari64;
1484 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_ari64;
1487 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_ari64;
1490 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_ari64;
1493 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_ari64;
1496 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_ari64;
1500 case NVPTXISD::LDUV2:
1501 switch (EltVT.getSimpleVT().SimpleTy) {
1505 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_ari64;
1508 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_ari64;
1511 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_ari64;
1514 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_ari64;
1517 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_ari64;
1520 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_ari64;
1524 case NVPTXISD::LDGV4:
1525 switch (EltVT.getSimpleVT().SimpleTy) {
1529 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari64;
1532 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_ari64;
1535 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_ari64;
1538 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_ari64;
1542 case NVPTXISD::LDUV4:
1543 switch (EltVT.getSimpleVT().SimpleTy) {
1547 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari64;
1550 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_ari64;
1553 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_ari64;
1556 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_ari64;
1562 switch (N->getOpcode()) {
1565 case ISD::INTRINSIC_W_CHAIN:
1567 switch (EltVT.getSimpleVT().SimpleTy) {
1571 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8ari;
1574 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16ari;
1577 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32ari;
1580 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64ari;
1583 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32ari;
1586 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64ari;
1590 switch (EltVT.getSimpleVT().SimpleTy) {
1594 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8ari;
1597 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16ari;
1600 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32ari;
1603 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64ari;
1606 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32ari;
1609 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64ari;
1614 case NVPTXISD::LDGV2:
1615 switch (EltVT.getSimpleVT().SimpleTy) {
1619 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_ari32;
1622 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_ari32;
1625 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_ari32;
1628 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_ari32;
1631 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_ari32;
1634 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_ari32;
1638 case NVPTXISD::LDUV2:
1639 switch (EltVT.getSimpleVT().SimpleTy) {
1643 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_ari32;
1646 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_ari32;
1649 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_ari32;
1652 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_ari32;
1655 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_ari32;
1658 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_ari32;
1662 case NVPTXISD::LDGV4:
1663 switch (EltVT.getSimpleVT().SimpleTy) {
1667 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari32;
1670 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_ari32;
1673 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_ari32;
1676 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_ari32;
1680 case NVPTXISD::LDUV4:
1681 switch (EltVT.getSimpleVT().SimpleTy) {
1685 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari32;
1688 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_ari32;
1691 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_ari32;
1694 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_ari32;
1701 SDValue Ops[] = { Base, Offset, Chain };
1703 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1706 switch (N->getOpcode()) {
1709 case ISD::INTRINSIC_W_CHAIN:
1711 switch (EltVT.getSimpleVT().SimpleTy) {
1715 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8areg64;
1718 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16areg64;
1721 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32areg64;
1724 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64areg64;
1727 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32areg64;
1730 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64areg64;
1734 switch (EltVT.getSimpleVT().SimpleTy) {
1738 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8areg64;
1741 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16areg64;
1744 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32areg64;
1747 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64areg64;
1750 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32areg64;
1753 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64areg64;
1758 case NVPTXISD::LDGV2:
1759 switch (EltVT.getSimpleVT().SimpleTy) {
1763 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_areg64;
1766 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_areg64;
1769 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_areg64;
1772 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_areg64;
1775 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_areg64;
1778 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_areg64;
1782 case NVPTXISD::LDUV2:
1783 switch (EltVT.getSimpleVT().SimpleTy) {
1787 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_areg64;
1790 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_areg64;
1793 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_areg64;
1796 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_areg64;
1799 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_areg64;
1802 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_areg64;
1806 case NVPTXISD::LDGV4:
1807 switch (EltVT.getSimpleVT().SimpleTy) {
1811 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg64;
1814 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg64;
1817 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg64;
1820 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg64;
1824 case NVPTXISD::LDUV4:
1825 switch (EltVT.getSimpleVT().SimpleTy) {
1829 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg64;
1832 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg64;
1835 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg64;
1838 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg64;
1844 switch (N->getOpcode()) {
1847 case ISD::INTRINSIC_W_CHAIN:
1849 switch (EltVT.getSimpleVT().SimpleTy) {
1853 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8areg;
1856 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16areg;
1859 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32areg;
1862 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64areg;
1865 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32areg;
1868 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64areg;
1872 switch (EltVT.getSimpleVT().SimpleTy) {
1876 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8areg;
1879 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16areg;
1882 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32areg;
1885 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64areg;
1888 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32areg;
1891 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64areg;
1896 case NVPTXISD::LDGV2:
1897 switch (EltVT.getSimpleVT().SimpleTy) {
1901 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_areg32;
1904 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_areg32;
1907 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_areg32;
1910 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_areg32;
1913 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_areg32;
1916 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_areg32;
1920 case NVPTXISD::LDUV2:
1921 switch (EltVT.getSimpleVT().SimpleTy) {
1925 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_areg32;
1928 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_areg32;
1931 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_areg32;
1934 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_areg32;
1937 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_areg32;
1940 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_areg32;
1944 case NVPTXISD::LDGV4:
1945 switch (EltVT.getSimpleVT().SimpleTy) {
1949 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg32;
1952 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg32;
1955 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg32;
1958 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg32;
1962 case NVPTXISD::LDUV4:
1963 switch (EltVT.getSimpleVT().SimpleTy) {
1967 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg32;
1970 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg32;
1973 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg32;
1976 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg32;
1983 SDValue Ops[] = { Op1, Chain };
1984 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1987 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
1988 MemRefs0[0] = Mem->getMemOperand();
1989 cast<MachineSDNode>(LD)->setMemRefs(MemRefs0, MemRefs0 + 1);
1994 SDNode *NVPTXDAGToDAGISel::SelectStore(SDNode *N) {
1996 StoreSDNode *ST = cast<StoreSDNode>(N);
1997 EVT StoreVT = ST->getMemoryVT();
1998 SDNode *NVPTXST = nullptr;
2000 // do not support pre/post inc/dec
2001 if (ST->isIndexed())
2004 if (!StoreVT.isSimple())
2007 // Address Space Setting
2008 unsigned int codeAddrSpace = getCodeAddrSpace(ST);
2011 // - .volatile is only availalble for .global and .shared
2012 bool isVolatile = ST->isVolatile();
2013 if (codeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
2014 codeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
2015 codeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
2019 MVT SimpleVT = StoreVT.getSimpleVT();
2020 unsigned vecType = NVPTX::PTXLdStInstCode::Scalar;
2021 if (SimpleVT.isVector()) {
2022 unsigned num = SimpleVT.getVectorNumElements();
2024 vecType = NVPTX::PTXLdStInstCode::V2;
2026 vecType = NVPTX::PTXLdStInstCode::V4;
2031 // Type Setting: toType + toTypeWidth
2032 // - for integer type, always use 'u'
2034 MVT ScalarVT = SimpleVT.getScalarType();
2035 unsigned toTypeWidth = ScalarVT.getSizeInBits();
2036 unsigned int toType;
2037 if (ScalarVT.isFloatingPoint())
2038 toType = NVPTX::PTXLdStInstCode::Float;
2040 toType = NVPTX::PTXLdStInstCode::Unsigned;
2042 // Create the machine instruction DAG
2043 SDValue Chain = N->getOperand(0);
2044 SDValue N1 = N->getOperand(1);
2045 SDValue N2 = N->getOperand(2);
2047 SDValue Offset, Base;
2049 MVT::SimpleValueType SourceVT = N1.getNode()->getSimpleValueType(0).SimpleTy;
2051 if (SelectDirectAddr(N2, Addr)) {
2054 Opcode = NVPTX::ST_i8_avar;
2057 Opcode = NVPTX::ST_i16_avar;
2060 Opcode = NVPTX::ST_i32_avar;
2063 Opcode = NVPTX::ST_i64_avar;
2066 Opcode = NVPTX::ST_f32_avar;
2069 Opcode = NVPTX::ST_f64_avar;
2074 SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
2075 getI32Imm(vecType), getI32Imm(toType),
2076 getI32Imm(toTypeWidth), Addr, Chain };
2077 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
2078 } else if (TM.is64Bit() ? SelectADDRsi64(N2.getNode(), N2, Base, Offset)
2079 : SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
2082 Opcode = NVPTX::ST_i8_asi;
2085 Opcode = NVPTX::ST_i16_asi;
2088 Opcode = NVPTX::ST_i32_asi;
2091 Opcode = NVPTX::ST_i64_asi;
2094 Opcode = NVPTX::ST_f32_asi;
2097 Opcode = NVPTX::ST_f64_asi;
2102 SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
2103 getI32Imm(vecType), getI32Imm(toType),
2104 getI32Imm(toTypeWidth), Base, Offset, Chain };
2105 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
2106 } else if (TM.is64Bit() ? SelectADDRri64(N2.getNode(), N2, Base, Offset)
2107 : SelectADDRri(N2.getNode(), N2, Base, Offset)) {
2111 Opcode = NVPTX::ST_i8_ari_64;
2114 Opcode = NVPTX::ST_i16_ari_64;
2117 Opcode = NVPTX::ST_i32_ari_64;
2120 Opcode = NVPTX::ST_i64_ari_64;
2123 Opcode = NVPTX::ST_f32_ari_64;
2126 Opcode = NVPTX::ST_f64_ari_64;
2134 Opcode = NVPTX::ST_i8_ari;
2137 Opcode = NVPTX::ST_i16_ari;
2140 Opcode = NVPTX::ST_i32_ari;
2143 Opcode = NVPTX::ST_i64_ari;
2146 Opcode = NVPTX::ST_f32_ari;
2149 Opcode = NVPTX::ST_f64_ari;
2155 SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
2156 getI32Imm(vecType), getI32Imm(toType),
2157 getI32Imm(toTypeWidth), Base, Offset, Chain };
2158 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
2163 Opcode = NVPTX::ST_i8_areg_64;
2166 Opcode = NVPTX::ST_i16_areg_64;
2169 Opcode = NVPTX::ST_i32_areg_64;
2172 Opcode = NVPTX::ST_i64_areg_64;
2175 Opcode = NVPTX::ST_f32_areg_64;
2178 Opcode = NVPTX::ST_f64_areg_64;
2186 Opcode = NVPTX::ST_i8_areg;
2189 Opcode = NVPTX::ST_i16_areg;
2192 Opcode = NVPTX::ST_i32_areg;
2195 Opcode = NVPTX::ST_i64_areg;
2198 Opcode = NVPTX::ST_f32_areg;
2201 Opcode = NVPTX::ST_f64_areg;
2207 SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
2208 getI32Imm(vecType), getI32Imm(toType),
2209 getI32Imm(toTypeWidth), N2, Chain };
2210 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
2214 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2215 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2216 cast<MachineSDNode>(NVPTXST)->setMemRefs(MemRefs0, MemRefs0 + 1);
2222 SDNode *NVPTXDAGToDAGISel::SelectStoreVector(SDNode *N) {
2223 SDValue Chain = N->getOperand(0);
2224 SDValue Op1 = N->getOperand(1);
2225 SDValue Addr, Offset, Base;
2229 EVT EltVT = Op1.getValueType();
2230 MemSDNode *MemSD = cast<MemSDNode>(N);
2231 EVT StoreVT = MemSD->getMemoryVT();
2233 // Address Space Setting
2234 unsigned CodeAddrSpace = getCodeAddrSpace(MemSD);
2236 if (CodeAddrSpace == NVPTX::PTXLdStInstCode::CONSTANT) {
2237 report_fatal_error("Cannot store to pointer that points to constant "
2242 // - .volatile is only availalble for .global and .shared
2243 bool IsVolatile = MemSD->isVolatile();
2244 if (CodeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
2245 CodeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
2246 CodeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
2249 // Type Setting: toType + toTypeWidth
2250 // - for integer type, always use 'u'
2251 assert(StoreVT.isSimple() && "Store value is not simple");
2252 MVT ScalarVT = StoreVT.getSimpleVT().getScalarType();
2253 unsigned ToTypeWidth = ScalarVT.getSizeInBits();
2255 if (ScalarVT.isFloatingPoint())
2256 ToType = NVPTX::PTXLdStInstCode::Float;
2258 ToType = NVPTX::PTXLdStInstCode::Unsigned;
2260 SmallVector<SDValue, 12> StOps;
2264 switch (N->getOpcode()) {
2265 case NVPTXISD::StoreV2:
2266 VecType = NVPTX::PTXLdStInstCode::V2;
2267 StOps.push_back(N->getOperand(1));
2268 StOps.push_back(N->getOperand(2));
2269 N2 = N->getOperand(3);
2271 case NVPTXISD::StoreV4:
2272 VecType = NVPTX::PTXLdStInstCode::V4;
2273 StOps.push_back(N->getOperand(1));
2274 StOps.push_back(N->getOperand(2));
2275 StOps.push_back(N->getOperand(3));
2276 StOps.push_back(N->getOperand(4));
2277 N2 = N->getOperand(5);
2283 StOps.push_back(getI32Imm(IsVolatile));
2284 StOps.push_back(getI32Imm(CodeAddrSpace));
2285 StOps.push_back(getI32Imm(VecType));
2286 StOps.push_back(getI32Imm(ToType));
2287 StOps.push_back(getI32Imm(ToTypeWidth));
2289 if (SelectDirectAddr(N2, Addr)) {
2290 switch (N->getOpcode()) {
2293 case NVPTXISD::StoreV2:
2294 switch (EltVT.getSimpleVT().SimpleTy) {
2298 Opcode = NVPTX::STV_i8_v2_avar;
2301 Opcode = NVPTX::STV_i16_v2_avar;
2304 Opcode = NVPTX::STV_i32_v2_avar;
2307 Opcode = NVPTX::STV_i64_v2_avar;
2310 Opcode = NVPTX::STV_f32_v2_avar;
2313 Opcode = NVPTX::STV_f64_v2_avar;
2317 case NVPTXISD::StoreV4:
2318 switch (EltVT.getSimpleVT().SimpleTy) {
2322 Opcode = NVPTX::STV_i8_v4_avar;
2325 Opcode = NVPTX::STV_i16_v4_avar;
2328 Opcode = NVPTX::STV_i32_v4_avar;
2331 Opcode = NVPTX::STV_f32_v4_avar;
2336 StOps.push_back(Addr);
2337 } else if (TM.is64Bit() ? SelectADDRsi64(N2.getNode(), N2, Base, Offset)
2338 : SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
2339 switch (N->getOpcode()) {
2342 case NVPTXISD::StoreV2:
2343 switch (EltVT.getSimpleVT().SimpleTy) {
2347 Opcode = NVPTX::STV_i8_v2_asi;
2350 Opcode = NVPTX::STV_i16_v2_asi;
2353 Opcode = NVPTX::STV_i32_v2_asi;
2356 Opcode = NVPTX::STV_i64_v2_asi;
2359 Opcode = NVPTX::STV_f32_v2_asi;
2362 Opcode = NVPTX::STV_f64_v2_asi;
2366 case NVPTXISD::StoreV4:
2367 switch (EltVT.getSimpleVT().SimpleTy) {
2371 Opcode = NVPTX::STV_i8_v4_asi;
2374 Opcode = NVPTX::STV_i16_v4_asi;
2377 Opcode = NVPTX::STV_i32_v4_asi;
2380 Opcode = NVPTX::STV_f32_v4_asi;
2385 StOps.push_back(Base);
2386 StOps.push_back(Offset);
2387 } else if (TM.is64Bit() ? SelectADDRri64(N2.getNode(), N2, Base, Offset)
2388 : SelectADDRri(N2.getNode(), N2, Base, Offset)) {
2390 switch (N->getOpcode()) {
2393 case NVPTXISD::StoreV2:
2394 switch (EltVT.getSimpleVT().SimpleTy) {
2398 Opcode = NVPTX::STV_i8_v2_ari_64;
2401 Opcode = NVPTX::STV_i16_v2_ari_64;
2404 Opcode = NVPTX::STV_i32_v2_ari_64;
2407 Opcode = NVPTX::STV_i64_v2_ari_64;
2410 Opcode = NVPTX::STV_f32_v2_ari_64;
2413 Opcode = NVPTX::STV_f64_v2_ari_64;
2417 case NVPTXISD::StoreV4:
2418 switch (EltVT.getSimpleVT().SimpleTy) {
2422 Opcode = NVPTX::STV_i8_v4_ari_64;
2425 Opcode = NVPTX::STV_i16_v4_ari_64;
2428 Opcode = NVPTX::STV_i32_v4_ari_64;
2431 Opcode = NVPTX::STV_f32_v4_ari_64;
2437 switch (N->getOpcode()) {
2440 case NVPTXISD::StoreV2:
2441 switch (EltVT.getSimpleVT().SimpleTy) {
2445 Opcode = NVPTX::STV_i8_v2_ari;
2448 Opcode = NVPTX::STV_i16_v2_ari;
2451 Opcode = NVPTX::STV_i32_v2_ari;
2454 Opcode = NVPTX::STV_i64_v2_ari;
2457 Opcode = NVPTX::STV_f32_v2_ari;
2460 Opcode = NVPTX::STV_f64_v2_ari;
2464 case NVPTXISD::StoreV4:
2465 switch (EltVT.getSimpleVT().SimpleTy) {
2469 Opcode = NVPTX::STV_i8_v4_ari;
2472 Opcode = NVPTX::STV_i16_v4_ari;
2475 Opcode = NVPTX::STV_i32_v4_ari;
2478 Opcode = NVPTX::STV_f32_v4_ari;
2484 StOps.push_back(Base);
2485 StOps.push_back(Offset);
2488 switch (N->getOpcode()) {
2491 case NVPTXISD::StoreV2:
2492 switch (EltVT.getSimpleVT().SimpleTy) {
2496 Opcode = NVPTX::STV_i8_v2_areg_64;
2499 Opcode = NVPTX::STV_i16_v2_areg_64;
2502 Opcode = NVPTX::STV_i32_v2_areg_64;
2505 Opcode = NVPTX::STV_i64_v2_areg_64;
2508 Opcode = NVPTX::STV_f32_v2_areg_64;
2511 Opcode = NVPTX::STV_f64_v2_areg_64;
2515 case NVPTXISD::StoreV4:
2516 switch (EltVT.getSimpleVT().SimpleTy) {
2520 Opcode = NVPTX::STV_i8_v4_areg_64;
2523 Opcode = NVPTX::STV_i16_v4_areg_64;
2526 Opcode = NVPTX::STV_i32_v4_areg_64;
2529 Opcode = NVPTX::STV_f32_v4_areg_64;
2535 switch (N->getOpcode()) {
2538 case NVPTXISD::StoreV2:
2539 switch (EltVT.getSimpleVT().SimpleTy) {
2543 Opcode = NVPTX::STV_i8_v2_areg;
2546 Opcode = NVPTX::STV_i16_v2_areg;
2549 Opcode = NVPTX::STV_i32_v2_areg;
2552 Opcode = NVPTX::STV_i64_v2_areg;
2555 Opcode = NVPTX::STV_f32_v2_areg;
2558 Opcode = NVPTX::STV_f64_v2_areg;
2562 case NVPTXISD::StoreV4:
2563 switch (EltVT.getSimpleVT().SimpleTy) {
2567 Opcode = NVPTX::STV_i8_v4_areg;
2570 Opcode = NVPTX::STV_i16_v4_areg;
2573 Opcode = NVPTX::STV_i32_v4_areg;
2576 Opcode = NVPTX::STV_f32_v4_areg;
2582 StOps.push_back(N2);
2585 StOps.push_back(Chain);
2587 ST = CurDAG->getMachineNode(Opcode, DL, MVT::Other, StOps);
2589 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2590 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2591 cast<MachineSDNode>(ST)->setMemRefs(MemRefs0, MemRefs0 + 1);
2596 SDNode *NVPTXDAGToDAGISel::SelectLoadParam(SDNode *Node) {
2597 SDValue Chain = Node->getOperand(0);
2598 SDValue Offset = Node->getOperand(2);
2599 SDValue Flag = Node->getOperand(3);
2601 MemSDNode *Mem = cast<MemSDNode>(Node);
2604 switch (Node->getOpcode()) {
2607 case NVPTXISD::LoadParam:
2610 case NVPTXISD::LoadParamV2:
2613 case NVPTXISD::LoadParamV4:
2618 EVT EltVT = Node->getValueType(0);
2619 EVT MemVT = Mem->getMemoryVT();
2627 switch (MemVT.getSimpleVT().SimpleTy) {
2631 Opc = NVPTX::LoadParamMemI8;
2634 Opc = NVPTX::LoadParamMemI8;
2637 Opc = NVPTX::LoadParamMemI16;
2640 Opc = NVPTX::LoadParamMemI32;
2643 Opc = NVPTX::LoadParamMemI64;
2646 Opc = NVPTX::LoadParamMemF32;
2649 Opc = NVPTX::LoadParamMemF64;
2654 switch (MemVT.getSimpleVT().SimpleTy) {
2658 Opc = NVPTX::LoadParamMemV2I8;
2661 Opc = NVPTX::LoadParamMemV2I8;
2664 Opc = NVPTX::LoadParamMemV2I16;
2667 Opc = NVPTX::LoadParamMemV2I32;
2670 Opc = NVPTX::LoadParamMemV2I64;
2673 Opc = NVPTX::LoadParamMemV2F32;
2676 Opc = NVPTX::LoadParamMemV2F64;
2681 switch (MemVT.getSimpleVT().SimpleTy) {
2685 Opc = NVPTX::LoadParamMemV4I8;
2688 Opc = NVPTX::LoadParamMemV4I8;
2691 Opc = NVPTX::LoadParamMemV4I16;
2694 Opc = NVPTX::LoadParamMemV4I32;
2697 Opc = NVPTX::LoadParamMemV4F32;
2705 VTs = CurDAG->getVTList(EltVT, MVT::Other, MVT::Glue);
2706 } else if (VecSize == 2) {
2707 VTs = CurDAG->getVTList(EltVT, EltVT, MVT::Other, MVT::Glue);
2709 EVT EVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other, MVT::Glue };
2710 VTs = CurDAG->getVTList(EVTs);
2713 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2715 SmallVector<SDValue, 2> Ops;
2716 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, MVT::i32));
2717 Ops.push_back(Chain);
2718 Ops.push_back(Flag);
2721 CurDAG->getMachineNode(Opc, DL, VTs, Ops);
2725 SDNode *NVPTXDAGToDAGISel::SelectStoreRetval(SDNode *N) {
2727 SDValue Chain = N->getOperand(0);
2728 SDValue Offset = N->getOperand(1);
2729 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2730 MemSDNode *Mem = cast<MemSDNode>(N);
2732 // How many elements do we have?
2733 unsigned NumElts = 1;
2734 switch (N->getOpcode()) {
2737 case NVPTXISD::StoreRetval:
2740 case NVPTXISD::StoreRetvalV2:
2743 case NVPTXISD::StoreRetvalV4:
2748 // Build vector of operands
2749 SmallVector<SDValue, 6> Ops;
2750 for (unsigned i = 0; i < NumElts; ++i)
2751 Ops.push_back(N->getOperand(i + 2));
2752 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, MVT::i32));
2753 Ops.push_back(Chain);
2755 // Determine target opcode
2756 // If we have an i1, use an 8-bit store. The lowering code in
2757 // NVPTXISelLowering will have already emitted an upcast.
2758 unsigned Opcode = 0;
2763 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2767 Opcode = NVPTX::StoreRetvalI8;
2770 Opcode = NVPTX::StoreRetvalI8;
2773 Opcode = NVPTX::StoreRetvalI16;
2776 Opcode = NVPTX::StoreRetvalI32;
2779 Opcode = NVPTX::StoreRetvalI64;
2782 Opcode = NVPTX::StoreRetvalF32;
2785 Opcode = NVPTX::StoreRetvalF64;
2790 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2794 Opcode = NVPTX::StoreRetvalV2I8;
2797 Opcode = NVPTX::StoreRetvalV2I8;
2800 Opcode = NVPTX::StoreRetvalV2I16;
2803 Opcode = NVPTX::StoreRetvalV2I32;
2806 Opcode = NVPTX::StoreRetvalV2I64;
2809 Opcode = NVPTX::StoreRetvalV2F32;
2812 Opcode = NVPTX::StoreRetvalV2F64;
2817 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2821 Opcode = NVPTX::StoreRetvalV4I8;
2824 Opcode = NVPTX::StoreRetvalV4I8;
2827 Opcode = NVPTX::StoreRetvalV4I16;
2830 Opcode = NVPTX::StoreRetvalV4I32;
2833 Opcode = NVPTX::StoreRetvalV4F32;
2840 CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops);
2841 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2842 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2843 cast<MachineSDNode>(Ret)->setMemRefs(MemRefs0, MemRefs0 + 1);
2848 SDNode *NVPTXDAGToDAGISel::SelectStoreParam(SDNode *N) {
2850 SDValue Chain = N->getOperand(0);
2851 SDValue Param = N->getOperand(1);
2852 unsigned ParamVal = cast<ConstantSDNode>(Param)->getZExtValue();
2853 SDValue Offset = N->getOperand(2);
2854 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2855 MemSDNode *Mem = cast<MemSDNode>(N);
2856 SDValue Flag = N->getOperand(N->getNumOperands() - 1);
2858 // How many elements do we have?
2859 unsigned NumElts = 1;
2860 switch (N->getOpcode()) {
2863 case NVPTXISD::StoreParamU32:
2864 case NVPTXISD::StoreParamS32:
2865 case NVPTXISD::StoreParam:
2868 case NVPTXISD::StoreParamV2:
2871 case NVPTXISD::StoreParamV4:
2876 // Build vector of operands
2877 SmallVector<SDValue, 8> Ops;
2878 for (unsigned i = 0; i < NumElts; ++i)
2879 Ops.push_back(N->getOperand(i + 3));
2880 Ops.push_back(CurDAG->getTargetConstant(ParamVal, MVT::i32));
2881 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, MVT::i32));
2882 Ops.push_back(Chain);
2883 Ops.push_back(Flag);
2885 // Determine target opcode
2886 // If we have an i1, use an 8-bit store. The lowering code in
2887 // NVPTXISelLowering will have already emitted an upcast.
2888 unsigned Opcode = 0;
2889 switch (N->getOpcode()) {
2895 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2899 Opcode = NVPTX::StoreParamI8;
2902 Opcode = NVPTX::StoreParamI8;
2905 Opcode = NVPTX::StoreParamI16;
2908 Opcode = NVPTX::StoreParamI32;
2911 Opcode = NVPTX::StoreParamI64;
2914 Opcode = NVPTX::StoreParamF32;
2917 Opcode = NVPTX::StoreParamF64;
2922 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2926 Opcode = NVPTX::StoreParamV2I8;
2929 Opcode = NVPTX::StoreParamV2I8;
2932 Opcode = NVPTX::StoreParamV2I16;
2935 Opcode = NVPTX::StoreParamV2I32;
2938 Opcode = NVPTX::StoreParamV2I64;
2941 Opcode = NVPTX::StoreParamV2F32;
2944 Opcode = NVPTX::StoreParamV2F64;
2949 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2953 Opcode = NVPTX::StoreParamV4I8;
2956 Opcode = NVPTX::StoreParamV4I8;
2959 Opcode = NVPTX::StoreParamV4I16;
2962 Opcode = NVPTX::StoreParamV4I32;
2965 Opcode = NVPTX::StoreParamV4F32;
2971 // Special case: if we have a sign-extend/zero-extend node, insert the
2972 // conversion instruction first, and use that as the value operand to
2973 // the selected StoreParam node.
2974 case NVPTXISD::StoreParamU32: {
2975 Opcode = NVPTX::StoreParamI32;
2976 SDValue CvtNone = CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE,
2978 SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_u32_u16, DL,
2979 MVT::i32, Ops[0], CvtNone);
2980 Ops[0] = SDValue(Cvt, 0);
2983 case NVPTXISD::StoreParamS32: {
2984 Opcode = NVPTX::StoreParamI32;
2985 SDValue CvtNone = CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE,
2987 SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_s32_s16, DL,
2988 MVT::i32, Ops[0], CvtNone);
2989 Ops[0] = SDValue(Cvt, 0);
2994 SDVTList RetVTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
2996 CurDAG->getMachineNode(Opcode, DL, RetVTs, Ops);
2997 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2998 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2999 cast<MachineSDNode>(Ret)->setMemRefs(MemRefs0, MemRefs0 + 1);
3004 SDNode *NVPTXDAGToDAGISel::SelectTextureIntrinsic(SDNode *N) {
3005 SDValue Chain = N->getOperand(0);
3006 SDNode *Ret = nullptr;
3008 SmallVector<SDValue, 8> Ops;
3010 switch (N->getOpcode()) {
3011 default: return nullptr;
3012 case NVPTXISD::Tex1DFloatS32:
3013 Opc = NVPTX::TEX_1D_F32_S32;
3015 case NVPTXISD::Tex1DFloatFloat:
3016 Opc = NVPTX::TEX_1D_F32_F32;
3018 case NVPTXISD::Tex1DFloatFloatLevel:
3019 Opc = NVPTX::TEX_1D_F32_F32_LEVEL;
3021 case NVPTXISD::Tex1DFloatFloatGrad:
3022 Opc = NVPTX::TEX_1D_F32_F32_GRAD;
3024 case NVPTXISD::Tex1DS32S32:
3025 Opc = NVPTX::TEX_1D_S32_S32;
3027 case NVPTXISD::Tex1DS32Float:
3028 Opc = NVPTX::TEX_1D_S32_F32;
3030 case NVPTXISD::Tex1DS32FloatLevel:
3031 Opc = NVPTX::TEX_1D_S32_F32_LEVEL;
3033 case NVPTXISD::Tex1DS32FloatGrad:
3034 Opc = NVPTX::TEX_1D_S32_F32_GRAD;
3036 case NVPTXISD::Tex1DU32S32:
3037 Opc = NVPTX::TEX_1D_U32_S32;
3039 case NVPTXISD::Tex1DU32Float:
3040 Opc = NVPTX::TEX_1D_U32_F32;
3042 case NVPTXISD::Tex1DU32FloatLevel:
3043 Opc = NVPTX::TEX_1D_U32_F32_LEVEL;
3045 case NVPTXISD::Tex1DU32FloatGrad:
3046 Opc = NVPTX::TEX_1D_U32_F32_GRAD;
3048 case NVPTXISD::Tex1DArrayFloatS32:
3049 Opc = NVPTX::TEX_1D_ARRAY_F32_S32;
3051 case NVPTXISD::Tex1DArrayFloatFloat:
3052 Opc = NVPTX::TEX_1D_ARRAY_F32_F32;
3054 case NVPTXISD::Tex1DArrayFloatFloatLevel:
3055 Opc = NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL;
3057 case NVPTXISD::Tex1DArrayFloatFloatGrad:
3058 Opc = NVPTX::TEX_1D_ARRAY_F32_F32_GRAD;
3060 case NVPTXISD::Tex1DArrayS32S32:
3061 Opc = NVPTX::TEX_1D_ARRAY_S32_S32;
3063 case NVPTXISD::Tex1DArrayS32Float:
3064 Opc = NVPTX::TEX_1D_ARRAY_S32_F32;
3066 case NVPTXISD::Tex1DArrayS32FloatLevel:
3067 Opc = NVPTX::TEX_1D_ARRAY_S32_F32_LEVEL;
3069 case NVPTXISD::Tex1DArrayS32FloatGrad:
3070 Opc = NVPTX::TEX_1D_ARRAY_S32_F32_GRAD;
3072 case NVPTXISD::Tex1DArrayU32S32:
3073 Opc = NVPTX::TEX_1D_ARRAY_U32_S32;
3075 case NVPTXISD::Tex1DArrayU32Float:
3076 Opc = NVPTX::TEX_1D_ARRAY_U32_F32;
3078 case NVPTXISD::Tex1DArrayU32FloatLevel:
3079 Opc = NVPTX::TEX_1D_ARRAY_U32_F32_LEVEL;
3081 case NVPTXISD::Tex1DArrayU32FloatGrad:
3082 Opc = NVPTX::TEX_1D_ARRAY_U32_F32_GRAD;
3084 case NVPTXISD::Tex2DFloatS32:
3085 Opc = NVPTX::TEX_2D_F32_S32;
3087 case NVPTXISD::Tex2DFloatFloat:
3088 Opc = NVPTX::TEX_2D_F32_F32;
3090 case NVPTXISD::Tex2DFloatFloatLevel:
3091 Opc = NVPTX::TEX_2D_F32_F32_LEVEL;
3093 case NVPTXISD::Tex2DFloatFloatGrad:
3094 Opc = NVPTX::TEX_2D_F32_F32_GRAD;
3096 case NVPTXISD::Tex2DS32S32:
3097 Opc = NVPTX::TEX_2D_S32_S32;
3099 case NVPTXISD::Tex2DS32Float:
3100 Opc = NVPTX::TEX_2D_S32_F32;
3102 case NVPTXISD::Tex2DS32FloatLevel:
3103 Opc = NVPTX::TEX_2D_S32_F32_LEVEL;
3105 case NVPTXISD::Tex2DS32FloatGrad:
3106 Opc = NVPTX::TEX_2D_S32_F32_GRAD;
3108 case NVPTXISD::Tex2DU32S32:
3109 Opc = NVPTX::TEX_2D_U32_S32;
3111 case NVPTXISD::Tex2DU32Float:
3112 Opc = NVPTX::TEX_2D_U32_F32;
3114 case NVPTXISD::Tex2DU32FloatLevel:
3115 Opc = NVPTX::TEX_2D_U32_F32_LEVEL;
3117 case NVPTXISD::Tex2DU32FloatGrad:
3118 Opc = NVPTX::TEX_2D_U32_F32_GRAD;
3120 case NVPTXISD::Tex2DArrayFloatS32:
3121 Opc = NVPTX::TEX_2D_ARRAY_F32_S32;
3123 case NVPTXISD::Tex2DArrayFloatFloat:
3124 Opc = NVPTX::TEX_2D_ARRAY_F32_F32;
3126 case NVPTXISD::Tex2DArrayFloatFloatLevel:
3127 Opc = NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL;
3129 case NVPTXISD::Tex2DArrayFloatFloatGrad:
3130 Opc = NVPTX::TEX_2D_ARRAY_F32_F32_GRAD;
3132 case NVPTXISD::Tex2DArrayS32S32:
3133 Opc = NVPTX::TEX_2D_ARRAY_S32_S32;
3135 case NVPTXISD::Tex2DArrayS32Float:
3136 Opc = NVPTX::TEX_2D_ARRAY_S32_F32;
3138 case NVPTXISD::Tex2DArrayS32FloatLevel:
3139 Opc = NVPTX::TEX_2D_ARRAY_S32_F32_LEVEL;
3141 case NVPTXISD::Tex2DArrayS32FloatGrad:
3142 Opc = NVPTX::TEX_2D_ARRAY_S32_F32_GRAD;
3144 case NVPTXISD::Tex2DArrayU32S32:
3145 Opc = NVPTX::TEX_2D_ARRAY_U32_S32;
3147 case NVPTXISD::Tex2DArrayU32Float:
3148 Opc = NVPTX::TEX_2D_ARRAY_U32_F32;
3150 case NVPTXISD::Tex2DArrayU32FloatLevel:
3151 Opc = NVPTX::TEX_2D_ARRAY_U32_F32_LEVEL;
3153 case NVPTXISD::Tex2DArrayU32FloatGrad:
3154 Opc = NVPTX::TEX_2D_ARRAY_U32_F32_GRAD;
3156 case NVPTXISD::Tex3DFloatS32:
3157 Opc = NVPTX::TEX_3D_F32_S32;
3159 case NVPTXISD::Tex3DFloatFloat:
3160 Opc = NVPTX::TEX_3D_F32_F32;
3162 case NVPTXISD::Tex3DFloatFloatLevel:
3163 Opc = NVPTX::TEX_3D_F32_F32_LEVEL;
3165 case NVPTXISD::Tex3DFloatFloatGrad:
3166 Opc = NVPTX::TEX_3D_F32_F32_GRAD;
3168 case NVPTXISD::Tex3DS32S32:
3169 Opc = NVPTX::TEX_3D_S32_S32;
3171 case NVPTXISD::Tex3DS32Float:
3172 Opc = NVPTX::TEX_3D_S32_F32;
3174 case NVPTXISD::Tex3DS32FloatLevel:
3175 Opc = NVPTX::TEX_3D_S32_F32_LEVEL;
3177 case NVPTXISD::Tex3DS32FloatGrad:
3178 Opc = NVPTX::TEX_3D_S32_F32_GRAD;
3180 case NVPTXISD::Tex3DU32S32:
3181 Opc = NVPTX::TEX_3D_U32_S32;
3183 case NVPTXISD::Tex3DU32Float:
3184 Opc = NVPTX::TEX_3D_U32_F32;
3186 case NVPTXISD::Tex3DU32FloatLevel:
3187 Opc = NVPTX::TEX_3D_U32_F32_LEVEL;
3189 case NVPTXISD::Tex3DU32FloatGrad:
3190 Opc = NVPTX::TEX_3D_U32_F32_GRAD;
3192 case NVPTXISD::TexCubeFloatFloat:
3193 Opc = NVPTX::TEX_CUBE_F32_F32;
3195 case NVPTXISD::TexCubeFloatFloatLevel:
3196 Opc = NVPTX::TEX_CUBE_F32_F32_LEVEL;
3198 case NVPTXISD::TexCubeS32Float:
3199 Opc = NVPTX::TEX_CUBE_S32_F32;
3201 case NVPTXISD::TexCubeS32FloatLevel:
3202 Opc = NVPTX::TEX_CUBE_S32_F32_LEVEL;
3204 case NVPTXISD::TexCubeU32Float:
3205 Opc = NVPTX::TEX_CUBE_U32_F32;
3207 case NVPTXISD::TexCubeU32FloatLevel:
3208 Opc = NVPTX::TEX_CUBE_U32_F32_LEVEL;
3210 case NVPTXISD::TexCubeArrayFloatFloat:
3211 Opc = NVPTX::TEX_CUBE_ARRAY_F32_F32;
3213 case NVPTXISD::TexCubeArrayFloatFloatLevel:
3214 Opc = NVPTX::TEX_CUBE_ARRAY_F32_F32_LEVEL;
3216 case NVPTXISD::TexCubeArrayS32Float:
3217 Opc = NVPTX::TEX_CUBE_ARRAY_S32_F32;
3219 case NVPTXISD::TexCubeArrayS32FloatLevel:
3220 Opc = NVPTX::TEX_CUBE_ARRAY_S32_F32_LEVEL;
3222 case NVPTXISD::TexCubeArrayU32Float:
3223 Opc = NVPTX::TEX_CUBE_ARRAY_U32_F32;
3225 case NVPTXISD::TexCubeArrayU32FloatLevel:
3226 Opc = NVPTX::TEX_CUBE_ARRAY_U32_F32_LEVEL;
3228 case NVPTXISD::Tld4R2DFloatFloat:
3229 Opc = NVPTX::TLD4_R_2D_F32_F32;
3231 case NVPTXISD::Tld4G2DFloatFloat:
3232 Opc = NVPTX::TLD4_G_2D_F32_F32;
3234 case NVPTXISD::Tld4B2DFloatFloat:
3235 Opc = NVPTX::TLD4_B_2D_F32_F32;
3237 case NVPTXISD::Tld4A2DFloatFloat:
3238 Opc = NVPTX::TLD4_A_2D_F32_F32;
3240 case NVPTXISD::Tld4R2DS64Float:
3241 Opc = NVPTX::TLD4_R_2D_S32_F32;
3243 case NVPTXISD::Tld4G2DS64Float:
3244 Opc = NVPTX::TLD4_G_2D_S32_F32;
3246 case NVPTXISD::Tld4B2DS64Float:
3247 Opc = NVPTX::TLD4_B_2D_S32_F32;
3249 case NVPTXISD::Tld4A2DS64Float:
3250 Opc = NVPTX::TLD4_A_2D_S32_F32;
3252 case NVPTXISD::Tld4R2DU64Float:
3253 Opc = NVPTX::TLD4_R_2D_U32_F32;
3255 case NVPTXISD::Tld4G2DU64Float:
3256 Opc = NVPTX::TLD4_G_2D_U32_F32;
3258 case NVPTXISD::Tld4B2DU64Float:
3259 Opc = NVPTX::TLD4_B_2D_U32_F32;
3261 case NVPTXISD::Tld4A2DU64Float:
3262 Opc = NVPTX::TLD4_A_2D_U32_F32;
3264 case NVPTXISD::TexUnified1DFloatS32:
3265 Opc = NVPTX::TEX_UNIFIED_1D_F32_S32;
3267 case NVPTXISD::TexUnified1DFloatFloat:
3268 Opc = NVPTX::TEX_UNIFIED_1D_F32_F32;
3270 case NVPTXISD::TexUnified1DFloatFloatLevel:
3271 Opc = NVPTX::TEX_UNIFIED_1D_F32_F32_LEVEL;
3273 case NVPTXISD::TexUnified1DFloatFloatGrad:
3274 Opc = NVPTX::TEX_UNIFIED_1D_F32_F32_GRAD;
3276 case NVPTXISD::TexUnified1DS32S32:
3277 Opc = NVPTX::TEX_UNIFIED_1D_S32_S32;
3279 case NVPTXISD::TexUnified1DS32Float:
3280 Opc = NVPTX::TEX_UNIFIED_1D_S32_F32;
3282 case NVPTXISD::TexUnified1DS32FloatLevel:
3283 Opc = NVPTX::TEX_UNIFIED_1D_S32_F32_LEVEL;
3285 case NVPTXISD::TexUnified1DS32FloatGrad:
3286 Opc = NVPTX::TEX_UNIFIED_1D_S32_F32_GRAD;
3288 case NVPTXISD::TexUnified1DU32S32:
3289 Opc = NVPTX::TEX_UNIFIED_1D_U32_S32;
3291 case NVPTXISD::TexUnified1DU32Float:
3292 Opc = NVPTX::TEX_UNIFIED_1D_U32_F32;
3294 case NVPTXISD::TexUnified1DU32FloatLevel:
3295 Opc = NVPTX::TEX_UNIFIED_1D_U32_F32_LEVEL;
3297 case NVPTXISD::TexUnified1DU32FloatGrad:
3298 Opc = NVPTX::TEX_UNIFIED_1D_U32_F32_GRAD;
3300 case NVPTXISD::TexUnified1DArrayFloatS32:
3301 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_S32;
3303 case NVPTXISD::TexUnified1DArrayFloatFloat:
3304 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32;
3306 case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
3307 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_LEVEL;
3309 case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
3310 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_GRAD;
3312 case NVPTXISD::TexUnified1DArrayS32S32:
3313 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_S32;
3315 case NVPTXISD::TexUnified1DArrayS32Float:
3316 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32;
3318 case NVPTXISD::TexUnified1DArrayS32FloatLevel:
3319 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_LEVEL;
3321 case NVPTXISD::TexUnified1DArrayS32FloatGrad:
3322 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_GRAD;
3324 case NVPTXISD::TexUnified1DArrayU32S32:
3325 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_S32;
3327 case NVPTXISD::TexUnified1DArrayU32Float:
3328 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32;
3330 case NVPTXISD::TexUnified1DArrayU32FloatLevel:
3331 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_LEVEL;
3333 case NVPTXISD::TexUnified1DArrayU32FloatGrad:
3334 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_GRAD;
3336 case NVPTXISD::TexUnified2DFloatS32:
3337 Opc = NVPTX::TEX_UNIFIED_2D_F32_S32;
3339 case NVPTXISD::TexUnified2DFloatFloat:
3340 Opc = NVPTX::TEX_UNIFIED_2D_F32_F32;
3342 case NVPTXISD::TexUnified2DFloatFloatLevel:
3343 Opc = NVPTX::TEX_UNIFIED_2D_F32_F32_LEVEL;
3345 case NVPTXISD::TexUnified2DFloatFloatGrad:
3346 Opc = NVPTX::TEX_UNIFIED_2D_F32_F32_GRAD;
3348 case NVPTXISD::TexUnified2DS32S32:
3349 Opc = NVPTX::TEX_UNIFIED_2D_S32_S32;
3351 case NVPTXISD::TexUnified2DS32Float:
3352 Opc = NVPTX::TEX_UNIFIED_2D_S32_F32;
3354 case NVPTXISD::TexUnified2DS32FloatLevel:
3355 Opc = NVPTX::TEX_UNIFIED_2D_S32_F32_LEVEL;
3357 case NVPTXISD::TexUnified2DS32FloatGrad:
3358 Opc = NVPTX::TEX_UNIFIED_2D_S32_F32_GRAD;
3360 case NVPTXISD::TexUnified2DU32S32:
3361 Opc = NVPTX::TEX_UNIFIED_2D_U32_S32;
3363 case NVPTXISD::TexUnified2DU32Float:
3364 Opc = NVPTX::TEX_UNIFIED_2D_U32_F32;
3366 case NVPTXISD::TexUnified2DU32FloatLevel:
3367 Opc = NVPTX::TEX_UNIFIED_2D_U32_F32_LEVEL;
3369 case NVPTXISD::TexUnified2DU32FloatGrad:
3370 Opc = NVPTX::TEX_UNIFIED_2D_U32_F32_GRAD;
3372 case NVPTXISD::TexUnified2DArrayFloatS32:
3373 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_S32;
3375 case NVPTXISD::TexUnified2DArrayFloatFloat:
3376 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32;
3378 case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
3379 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_LEVEL;
3381 case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
3382 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_GRAD;
3384 case NVPTXISD::TexUnified2DArrayS32S32:
3385 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_S32;
3387 case NVPTXISD::TexUnified2DArrayS32Float:
3388 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32;
3390 case NVPTXISD::TexUnified2DArrayS32FloatLevel:
3391 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_LEVEL;
3393 case NVPTXISD::TexUnified2DArrayS32FloatGrad:
3394 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_GRAD;
3396 case NVPTXISD::TexUnified2DArrayU32S32:
3397 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_S32;
3399 case NVPTXISD::TexUnified2DArrayU32Float:
3400 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32;
3402 case NVPTXISD::TexUnified2DArrayU32FloatLevel:
3403 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_LEVEL;
3405 case NVPTXISD::TexUnified2DArrayU32FloatGrad:
3406 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_GRAD;
3408 case NVPTXISD::TexUnified3DFloatS32:
3409 Opc = NVPTX::TEX_UNIFIED_3D_F32_S32;
3411 case NVPTXISD::TexUnified3DFloatFloat:
3412 Opc = NVPTX::TEX_UNIFIED_3D_F32_F32;
3414 case NVPTXISD::TexUnified3DFloatFloatLevel:
3415 Opc = NVPTX::TEX_UNIFIED_3D_F32_F32_LEVEL;
3417 case NVPTXISD::TexUnified3DFloatFloatGrad:
3418 Opc = NVPTX::TEX_UNIFIED_3D_F32_F32_GRAD;
3420 case NVPTXISD::TexUnified3DS32S32:
3421 Opc = NVPTX::TEX_UNIFIED_3D_S32_S32;
3423 case NVPTXISD::TexUnified3DS32Float:
3424 Opc = NVPTX::TEX_UNIFIED_3D_S32_F32;
3426 case NVPTXISD::TexUnified3DS32FloatLevel:
3427 Opc = NVPTX::TEX_UNIFIED_3D_S32_F32_LEVEL;
3429 case NVPTXISD::TexUnified3DS32FloatGrad:
3430 Opc = NVPTX::TEX_UNIFIED_3D_S32_F32_GRAD;
3432 case NVPTXISD::TexUnified3DU32S32:
3433 Opc = NVPTX::TEX_UNIFIED_3D_U32_S32;
3435 case NVPTXISD::TexUnified3DU32Float:
3436 Opc = NVPTX::TEX_UNIFIED_3D_U32_F32;
3438 case NVPTXISD::TexUnified3DU32FloatLevel:
3439 Opc = NVPTX::TEX_UNIFIED_3D_U32_F32_LEVEL;
3441 case NVPTXISD::TexUnified3DU32FloatGrad:
3442 Opc = NVPTX::TEX_UNIFIED_3D_U32_F32_GRAD;
3444 case NVPTXISD::TexUnifiedCubeFloatFloat:
3445 Opc = NVPTX::TEX_UNIFIED_CUBE_F32_F32;
3447 case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
3448 Opc = NVPTX::TEX_UNIFIED_CUBE_F32_F32_LEVEL;
3450 case NVPTXISD::TexUnifiedCubeS32Float:
3451 Opc = NVPTX::TEX_UNIFIED_CUBE_S32_F32;
3453 case NVPTXISD::TexUnifiedCubeS32FloatLevel:
3454 Opc = NVPTX::TEX_UNIFIED_CUBE_S32_F32_LEVEL;
3456 case NVPTXISD::TexUnifiedCubeU32Float:
3457 Opc = NVPTX::TEX_UNIFIED_CUBE_U32_F32;
3459 case NVPTXISD::TexUnifiedCubeU32FloatLevel:
3460 Opc = NVPTX::TEX_UNIFIED_CUBE_U32_F32_LEVEL;
3462 case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
3463 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32;
3465 case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
3466 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32_LEVEL;
3468 case NVPTXISD::TexUnifiedCubeArrayS32Float:
3469 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32;
3471 case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
3472 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32_LEVEL;
3474 case NVPTXISD::TexUnifiedCubeArrayU32Float:
3475 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32;
3477 case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
3478 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32_LEVEL;
3480 case NVPTXISD::Tld4UnifiedR2DFloatFloat:
3481 Opc = NVPTX::TLD4_UNIFIED_R_2D_F32_F32;
3483 case NVPTXISD::Tld4UnifiedG2DFloatFloat:
3484 Opc = NVPTX::TLD4_UNIFIED_G_2D_F32_F32;
3486 case NVPTXISD::Tld4UnifiedB2DFloatFloat:
3487 Opc = NVPTX::TLD4_UNIFIED_B_2D_F32_F32;
3489 case NVPTXISD::Tld4UnifiedA2DFloatFloat:
3490 Opc = NVPTX::TLD4_UNIFIED_A_2D_F32_F32;
3492 case NVPTXISD::Tld4UnifiedR2DS64Float:
3493 Opc = NVPTX::TLD4_UNIFIED_R_2D_S32_F32;
3495 case NVPTXISD::Tld4UnifiedG2DS64Float:
3496 Opc = NVPTX::TLD4_UNIFIED_G_2D_S32_F32;
3498 case NVPTXISD::Tld4UnifiedB2DS64Float:
3499 Opc = NVPTX::TLD4_UNIFIED_B_2D_S32_F32;
3501 case NVPTXISD::Tld4UnifiedA2DS64Float:
3502 Opc = NVPTX::TLD4_UNIFIED_A_2D_S32_F32;
3504 case NVPTXISD::Tld4UnifiedR2DU64Float:
3505 Opc = NVPTX::TLD4_UNIFIED_R_2D_U32_F32;
3507 case NVPTXISD::Tld4UnifiedG2DU64Float:
3508 Opc = NVPTX::TLD4_UNIFIED_G_2D_U32_F32;
3510 case NVPTXISD::Tld4UnifiedB2DU64Float:
3511 Opc = NVPTX::TLD4_UNIFIED_B_2D_U32_F32;
3513 case NVPTXISD::Tld4UnifiedA2DU64Float:
3514 Opc = NVPTX::TLD4_UNIFIED_A_2D_U32_F32;
3518 // Copy over operands
3519 for (unsigned i = 1; i < N->getNumOperands(); ++i) {
3520 Ops.push_back(N->getOperand(i));
3523 Ops.push_back(Chain);
3524 Ret = CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);
3528 SDNode *NVPTXDAGToDAGISel::SelectSurfaceIntrinsic(SDNode *N) {
3529 SDValue Chain = N->getOperand(0);
3530 SDValue TexHandle = N->getOperand(1);
3531 SDNode *Ret = nullptr;
3533 SmallVector<SDValue, 8> Ops;
3534 switch (N->getOpcode()) {
3535 default: return nullptr;
3536 case NVPTXISD::Suld1DI8Clamp:
3537 Opc = NVPTX::SULD_1D_I8_CLAMP;
3538 Ops.push_back(TexHandle);
3539 Ops.push_back(N->getOperand(2));
3540 Ops.push_back(Chain);
3542 case NVPTXISD::Suld1DI16Clamp:
3543 Opc = NVPTX::SULD_1D_I16_CLAMP;
3544 Ops.push_back(TexHandle);
3545 Ops.push_back(N->getOperand(2));
3546 Ops.push_back(Chain);
3548 case NVPTXISD::Suld1DI32Clamp:
3549 Opc = NVPTX::SULD_1D_I32_CLAMP;
3550 Ops.push_back(TexHandle);
3551 Ops.push_back(N->getOperand(2));
3552 Ops.push_back(Chain);
3554 case NVPTXISD::Suld1DI64Clamp:
3555 Opc = NVPTX::SULD_1D_I64_CLAMP;
3556 Ops.push_back(TexHandle);
3557 Ops.push_back(N->getOperand(2));
3558 Ops.push_back(Chain);
3560 case NVPTXISD::Suld1DV2I8Clamp:
3561 Opc = NVPTX::SULD_1D_V2I8_CLAMP;
3562 Ops.push_back(TexHandle);
3563 Ops.push_back(N->getOperand(2));
3564 Ops.push_back(Chain);
3566 case NVPTXISD::Suld1DV2I16Clamp:
3567 Opc = NVPTX::SULD_1D_V2I16_CLAMP;
3568 Ops.push_back(TexHandle);
3569 Ops.push_back(N->getOperand(2));
3570 Ops.push_back(Chain);
3572 case NVPTXISD::Suld1DV2I32Clamp:
3573 Opc = NVPTX::SULD_1D_V2I32_CLAMP;
3574 Ops.push_back(TexHandle);
3575 Ops.push_back(N->getOperand(2));
3576 Ops.push_back(Chain);
3578 case NVPTXISD::Suld1DV2I64Clamp:
3579 Opc = NVPTX::SULD_1D_V2I64_CLAMP;
3580 Ops.push_back(TexHandle);
3581 Ops.push_back(N->getOperand(2));
3582 Ops.push_back(Chain);
3584 case NVPTXISD::Suld1DV4I8Clamp:
3585 Opc = NVPTX::SULD_1D_V4I8_CLAMP;
3586 Ops.push_back(TexHandle);
3587 Ops.push_back(N->getOperand(2));
3588 Ops.push_back(Chain);
3590 case NVPTXISD::Suld1DV4I16Clamp:
3591 Opc = NVPTX::SULD_1D_V4I16_CLAMP;
3592 Ops.push_back(TexHandle);
3593 Ops.push_back(N->getOperand(2));
3594 Ops.push_back(Chain);
3596 case NVPTXISD::Suld1DV4I32Clamp:
3597 Opc = NVPTX::SULD_1D_V4I32_CLAMP;
3598 Ops.push_back(TexHandle);
3599 Ops.push_back(N->getOperand(2));
3600 Ops.push_back(Chain);
3602 case NVPTXISD::Suld1DArrayI8Clamp:
3603 Opc = NVPTX::SULD_1D_ARRAY_I8_CLAMP;
3604 Ops.push_back(TexHandle);
3605 Ops.push_back(N->getOperand(2));
3606 Ops.push_back(N->getOperand(3));
3607 Ops.push_back(Chain);
3609 case NVPTXISD::Suld1DArrayI16Clamp:
3610 Opc = NVPTX::SULD_1D_ARRAY_I16_CLAMP;
3611 Ops.push_back(TexHandle);
3612 Ops.push_back(N->getOperand(2));
3613 Ops.push_back(N->getOperand(3));
3614 Ops.push_back(Chain);
3616 case NVPTXISD::Suld1DArrayI32Clamp:
3617 Opc = NVPTX::SULD_1D_ARRAY_I32_CLAMP;
3618 Ops.push_back(TexHandle);
3619 Ops.push_back(N->getOperand(2));
3620 Ops.push_back(N->getOperand(3));
3621 Ops.push_back(Chain);
3623 case NVPTXISD::Suld1DArrayI64Clamp:
3624 Opc = NVPTX::SULD_1D_ARRAY_I64_CLAMP;
3625 Ops.push_back(TexHandle);
3626 Ops.push_back(N->getOperand(2));
3627 Ops.push_back(N->getOperand(3));
3628 Ops.push_back(Chain);
3630 case NVPTXISD::Suld1DArrayV2I8Clamp:
3631 Opc = NVPTX::SULD_1D_ARRAY_V2I8_CLAMP;
3632 Ops.push_back(TexHandle);
3633 Ops.push_back(N->getOperand(2));
3634 Ops.push_back(N->getOperand(3));
3635 Ops.push_back(Chain);
3637 case NVPTXISD::Suld1DArrayV2I16Clamp:
3638 Opc = NVPTX::SULD_1D_ARRAY_V2I16_CLAMP;
3639 Ops.push_back(TexHandle);
3640 Ops.push_back(N->getOperand(2));
3641 Ops.push_back(N->getOperand(3));
3642 Ops.push_back(Chain);
3644 case NVPTXISD::Suld1DArrayV2I32Clamp:
3645 Opc = NVPTX::SULD_1D_ARRAY_V2I32_CLAMP;
3646 Ops.push_back(TexHandle);
3647 Ops.push_back(N->getOperand(2));
3648 Ops.push_back(N->getOperand(3));
3649 Ops.push_back(Chain);
3651 case NVPTXISD::Suld1DArrayV2I64Clamp:
3652 Opc = NVPTX::SULD_1D_ARRAY_V2I64_CLAMP;
3653 Ops.push_back(TexHandle);
3654 Ops.push_back(N->getOperand(2));
3655 Ops.push_back(N->getOperand(3));
3656 Ops.push_back(Chain);
3658 case NVPTXISD::Suld1DArrayV4I8Clamp:
3659 Opc = NVPTX::SULD_1D_ARRAY_V4I8_CLAMP;
3660 Ops.push_back(TexHandle);
3661 Ops.push_back(N->getOperand(2));
3662 Ops.push_back(N->getOperand(3));
3663 Ops.push_back(Chain);
3665 case NVPTXISD::Suld1DArrayV4I16Clamp:
3666 Opc = NVPTX::SULD_1D_ARRAY_V4I16_CLAMP;
3667 Ops.push_back(TexHandle);
3668 Ops.push_back(N->getOperand(2));
3669 Ops.push_back(N->getOperand(3));
3670 Ops.push_back(Chain);
3672 case NVPTXISD::Suld1DArrayV4I32Clamp:
3673 Opc = NVPTX::SULD_1D_ARRAY_V4I32_CLAMP;
3674 Ops.push_back(TexHandle);
3675 Ops.push_back(N->getOperand(2));
3676 Ops.push_back(N->getOperand(3));
3677 Ops.push_back(Chain);
3679 case NVPTXISD::Suld2DI8Clamp:
3680 Opc = NVPTX::SULD_2D_I8_CLAMP;
3681 Ops.push_back(TexHandle);
3682 Ops.push_back(N->getOperand(2));
3683 Ops.push_back(N->getOperand(3));
3684 Ops.push_back(Chain);
3686 case NVPTXISD::Suld2DI16Clamp:
3687 Opc = NVPTX::SULD_2D_I16_CLAMP;
3688 Ops.push_back(TexHandle);
3689 Ops.push_back(N->getOperand(2));
3690 Ops.push_back(N->getOperand(3));
3691 Ops.push_back(Chain);
3693 case NVPTXISD::Suld2DI32Clamp:
3694 Opc = NVPTX::SULD_2D_I32_CLAMP;
3695 Ops.push_back(TexHandle);
3696 Ops.push_back(N->getOperand(2));
3697 Ops.push_back(N->getOperand(3));
3698 Ops.push_back(Chain);
3700 case NVPTXISD::Suld2DI64Clamp:
3701 Opc = NVPTX::SULD_2D_I64_CLAMP;
3702 Ops.push_back(TexHandle);
3703 Ops.push_back(N->getOperand(2));
3704 Ops.push_back(N->getOperand(3));
3705 Ops.push_back(Chain);
3707 case NVPTXISD::Suld2DV2I8Clamp:
3708 Opc = NVPTX::SULD_2D_V2I8_CLAMP;
3709 Ops.push_back(TexHandle);
3710 Ops.push_back(N->getOperand(2));
3711 Ops.push_back(N->getOperand(3));
3712 Ops.push_back(Chain);
3714 case NVPTXISD::Suld2DV2I16Clamp:
3715 Opc = NVPTX::SULD_2D_V2I16_CLAMP;
3716 Ops.push_back(TexHandle);
3717 Ops.push_back(N->getOperand(2));
3718 Ops.push_back(N->getOperand(3));
3719 Ops.push_back(Chain);
3721 case NVPTXISD::Suld2DV2I32Clamp:
3722 Opc = NVPTX::SULD_2D_V2I32_CLAMP;
3723 Ops.push_back(TexHandle);
3724 Ops.push_back(N->getOperand(2));
3725 Ops.push_back(N->getOperand(3));
3726 Ops.push_back(Chain);
3728 case NVPTXISD::Suld2DV2I64Clamp:
3729 Opc = NVPTX::SULD_2D_V2I64_CLAMP;
3730 Ops.push_back(TexHandle);
3731 Ops.push_back(N->getOperand(2));
3732 Ops.push_back(N->getOperand(3));
3733 Ops.push_back(Chain);
3735 case NVPTXISD::Suld2DV4I8Clamp:
3736 Opc = NVPTX::SULD_2D_V4I8_CLAMP;
3737 Ops.push_back(TexHandle);
3738 Ops.push_back(N->getOperand(2));
3739 Ops.push_back(N->getOperand(3));
3740 Ops.push_back(Chain);
3742 case NVPTXISD::Suld2DV4I16Clamp:
3743 Opc = NVPTX::SULD_2D_V4I16_CLAMP;
3744 Ops.push_back(TexHandle);
3745 Ops.push_back(N->getOperand(2));
3746 Ops.push_back(N->getOperand(3));
3747 Ops.push_back(Chain);
3749 case NVPTXISD::Suld2DV4I32Clamp:
3750 Opc = NVPTX::SULD_2D_V4I32_CLAMP;
3751 Ops.push_back(TexHandle);
3752 Ops.push_back(N->getOperand(2));
3753 Ops.push_back(N->getOperand(3));
3754 Ops.push_back(Chain);
3756 case NVPTXISD::Suld2DArrayI8Clamp:
3757 Opc = NVPTX::SULD_2D_ARRAY_I8_CLAMP;
3758 Ops.push_back(TexHandle);
3759 Ops.push_back(N->getOperand(2));
3760 Ops.push_back(N->getOperand(3));
3761 Ops.push_back(N->getOperand(4));
3762 Ops.push_back(Chain);
3764 case NVPTXISD::Suld2DArrayI16Clamp:
3765 Opc = NVPTX::SULD_2D_ARRAY_I16_CLAMP;
3766 Ops.push_back(TexHandle);
3767 Ops.push_back(N->getOperand(2));
3768 Ops.push_back(N->getOperand(3));
3769 Ops.push_back(N->getOperand(4));
3770 Ops.push_back(Chain);
3772 case NVPTXISD::Suld2DArrayI32Clamp:
3773 Opc = NVPTX::SULD_2D_ARRAY_I32_CLAMP;
3774 Ops.push_back(TexHandle);
3775 Ops.push_back(N->getOperand(2));
3776 Ops.push_back(N->getOperand(3));
3777 Ops.push_back(N->getOperand(4));
3778 Ops.push_back(Chain);
3780 case NVPTXISD::Suld2DArrayI64Clamp:
3781 Opc = NVPTX::SULD_2D_ARRAY_I64_CLAMP;
3782 Ops.push_back(TexHandle);
3783 Ops.push_back(N->getOperand(2));
3784 Ops.push_back(N->getOperand(3));
3785 Ops.push_back(N->getOperand(4));
3786 Ops.push_back(Chain);
3788 case NVPTXISD::Suld2DArrayV2I8Clamp:
3789 Opc = NVPTX::SULD_2D_ARRAY_V2I8_CLAMP;
3790 Ops.push_back(TexHandle);
3791 Ops.push_back(N->getOperand(2));
3792 Ops.push_back(N->getOperand(3));
3793 Ops.push_back(N->getOperand(4));
3794 Ops.push_back(Chain);
3796 case NVPTXISD::Suld2DArrayV2I16Clamp:
3797 Opc = NVPTX::SULD_2D_ARRAY_V2I16_CLAMP;
3798 Ops.push_back(TexHandle);
3799 Ops.push_back(N->getOperand(2));
3800 Ops.push_back(N->getOperand(3));
3801 Ops.push_back(N->getOperand(4));
3802 Ops.push_back(Chain);
3804 case NVPTXISD::Suld2DArrayV2I32Clamp:
3805 Opc = NVPTX::SULD_2D_ARRAY_V2I32_CLAMP;
3806 Ops.push_back(TexHandle);
3807 Ops.push_back(N->getOperand(2));
3808 Ops.push_back(N->getOperand(3));
3809 Ops.push_back(N->getOperand(4));
3810 Ops.push_back(Chain);
3812 case NVPTXISD::Suld2DArrayV2I64Clamp:
3813 Opc = NVPTX::SULD_2D_ARRAY_V2I64_CLAMP;
3814 Ops.push_back(TexHandle);
3815 Ops.push_back(N->getOperand(2));
3816 Ops.push_back(N->getOperand(3));
3817 Ops.push_back(N->getOperand(4));
3818 Ops.push_back(Chain);
3820 case NVPTXISD::Suld2DArrayV4I8Clamp:
3821 Opc = NVPTX::SULD_2D_ARRAY_V4I8_CLAMP;
3822 Ops.push_back(TexHandle);
3823 Ops.push_back(N->getOperand(2));
3824 Ops.push_back(N->getOperand(3));
3825 Ops.push_back(N->getOperand(4));
3826 Ops.push_back(Chain);
3828 case NVPTXISD::Suld2DArrayV4I16Clamp:
3829 Opc = NVPTX::SULD_2D_ARRAY_V4I16_CLAMP;
3830 Ops.push_back(TexHandle);
3831 Ops.push_back(N->getOperand(2));
3832 Ops.push_back(N->getOperand(3));
3833 Ops.push_back(N->getOperand(4));
3834 Ops.push_back(Chain);
3836 case NVPTXISD::Suld2DArrayV4I32Clamp:
3837 Opc = NVPTX::SULD_2D_ARRAY_V4I32_CLAMP;
3838 Ops.push_back(TexHandle);
3839 Ops.push_back(N->getOperand(2));
3840 Ops.push_back(N->getOperand(3));
3841 Ops.push_back(N->getOperand(4));
3842 Ops.push_back(Chain);
3844 case NVPTXISD::Suld3DI8Clamp:
3845 Opc = NVPTX::SULD_3D_I8_CLAMP;
3846 Ops.push_back(TexHandle);
3847 Ops.push_back(N->getOperand(2));
3848 Ops.push_back(N->getOperand(3));
3849 Ops.push_back(N->getOperand(4));
3850 Ops.push_back(Chain);
3852 case NVPTXISD::Suld3DI16Clamp:
3853 Opc = NVPTX::SULD_3D_I16_CLAMP;
3854 Ops.push_back(TexHandle);
3855 Ops.push_back(N->getOperand(2));
3856 Ops.push_back(N->getOperand(3));
3857 Ops.push_back(N->getOperand(4));
3858 Ops.push_back(Chain);
3860 case NVPTXISD::Suld3DI32Clamp:
3861 Opc = NVPTX::SULD_3D_I32_CLAMP;
3862 Ops.push_back(TexHandle);
3863 Ops.push_back(N->getOperand(2));
3864 Ops.push_back(N->getOperand(3));
3865 Ops.push_back(N->getOperand(4));
3866 Ops.push_back(Chain);
3868 case NVPTXISD::Suld3DI64Clamp:
3869 Opc = NVPTX::SULD_3D_I64_CLAMP;
3870 Ops.push_back(TexHandle);
3871 Ops.push_back(N->getOperand(2));
3872 Ops.push_back(N->getOperand(3));
3873 Ops.push_back(N->getOperand(4));
3874 Ops.push_back(Chain);
3876 case NVPTXISD::Suld3DV2I8Clamp:
3877 Opc = NVPTX::SULD_3D_V2I8_CLAMP;
3878 Ops.push_back(TexHandle);
3879 Ops.push_back(N->getOperand(2));
3880 Ops.push_back(N->getOperand(3));
3881 Ops.push_back(N->getOperand(4));
3882 Ops.push_back(Chain);
3884 case NVPTXISD::Suld3DV2I16Clamp:
3885 Opc = NVPTX::SULD_3D_V2I16_CLAMP;
3886 Ops.push_back(TexHandle);
3887 Ops.push_back(N->getOperand(2));
3888 Ops.push_back(N->getOperand(3));
3889 Ops.push_back(N->getOperand(4));
3890 Ops.push_back(Chain);
3892 case NVPTXISD::Suld3DV2I32Clamp:
3893 Opc = NVPTX::SULD_3D_V2I32_CLAMP;
3894 Ops.push_back(TexHandle);
3895 Ops.push_back(N->getOperand(2));
3896 Ops.push_back(N->getOperand(3));
3897 Ops.push_back(N->getOperand(4));
3898 Ops.push_back(Chain);
3900 case NVPTXISD::Suld3DV2I64Clamp:
3901 Opc = NVPTX::SULD_3D_V2I64_CLAMP;
3902 Ops.push_back(TexHandle);
3903 Ops.push_back(N->getOperand(2));
3904 Ops.push_back(N->getOperand(3));
3905 Ops.push_back(N->getOperand(4));
3906 Ops.push_back(Chain);
3908 case NVPTXISD::Suld3DV4I8Clamp:
3909 Opc = NVPTX::SULD_3D_V4I8_CLAMP;
3910 Ops.push_back(TexHandle);
3911 Ops.push_back(N->getOperand(2));
3912 Ops.push_back(N->getOperand(3));
3913 Ops.push_back(N->getOperand(4));
3914 Ops.push_back(Chain);
3916 case NVPTXISD::Suld3DV4I16Clamp:
3917 Opc = NVPTX::SULD_3D_V4I16_CLAMP;
3918 Ops.push_back(TexHandle);
3919 Ops.push_back(N->getOperand(2));
3920 Ops.push_back(N->getOperand(3));
3921 Ops.push_back(N->getOperand(4));
3922 Ops.push_back(Chain);
3924 case NVPTXISD::Suld3DV4I32Clamp:
3925 Opc = NVPTX::SULD_3D_V4I32_CLAMP;
3926 Ops.push_back(TexHandle);
3927 Ops.push_back(N->getOperand(2));
3928 Ops.push_back(N->getOperand(3));
3929 Ops.push_back(N->getOperand(4));
3930 Ops.push_back(Chain);
3932 case NVPTXISD::Suld1DI8Trap:
3933 Opc = NVPTX::SULD_1D_I8_TRAP;
3934 Ops.push_back(TexHandle);
3935 Ops.push_back(N->getOperand(2));
3936 Ops.push_back(Chain);
3938 case NVPTXISD::Suld1DI16Trap:
3939 Opc = NVPTX::SULD_1D_I16_TRAP;
3940 Ops.push_back(TexHandle);
3941 Ops.push_back(N->getOperand(2));
3942 Ops.push_back(Chain);
3944 case NVPTXISD::Suld1DI32Trap:
3945 Opc = NVPTX::SULD_1D_I32_TRAP;
3946 Ops.push_back(TexHandle);
3947 Ops.push_back(N->getOperand(2));
3948 Ops.push_back(Chain);
3950 case NVPTXISD::Suld1DI64Trap:
3951 Opc = NVPTX::SULD_1D_I64_TRAP;
3952 Ops.push_back(TexHandle);
3953 Ops.push_back(N->getOperand(2));
3954 Ops.push_back(Chain);
3956 case NVPTXISD::Suld1DV2I8Trap:
3957 Opc = NVPTX::SULD_1D_V2I8_TRAP;
3958 Ops.push_back(TexHandle);
3959 Ops.push_back(N->getOperand(2));
3960 Ops.push_back(Chain);
3962 case NVPTXISD::Suld1DV2I16Trap:
3963 Opc = NVPTX::SULD_1D_V2I16_TRAP;
3964 Ops.push_back(TexHandle);
3965 Ops.push_back(N->getOperand(2));
3966 Ops.push_back(Chain);
3968 case NVPTXISD::Suld1DV2I32Trap:
3969 Opc = NVPTX::SULD_1D_V2I32_TRAP;
3970 Ops.push_back(TexHandle);
3971 Ops.push_back(N->getOperand(2));
3972 Ops.push_back(Chain);
3974 case NVPTXISD::Suld1DV2I64Trap:
3975 Opc = NVPTX::SULD_1D_V2I64_TRAP;
3976 Ops.push_back(TexHandle);
3977 Ops.push_back(N->getOperand(2));
3978 Ops.push_back(Chain);
3980 case NVPTXISD::Suld1DV4I8Trap:
3981 Opc = NVPTX::SULD_1D_V4I8_TRAP;
3982 Ops.push_back(TexHandle);
3983 Ops.push_back(N->getOperand(2));
3984 Ops.push_back(Chain);
3986 case NVPTXISD::Suld1DV4I16Trap:
3987 Opc = NVPTX::SULD_1D_V4I16_TRAP;
3988 Ops.push_back(TexHandle);
3989 Ops.push_back(N->getOperand(2));
3990 Ops.push_back(Chain);
3992 case NVPTXISD::Suld1DV4I32Trap:
3993 Opc = NVPTX::SULD_1D_V4I32_TRAP;
3994 Ops.push_back(TexHandle);
3995 Ops.push_back(N->getOperand(2));
3996 Ops.push_back(Chain);
3998 case NVPTXISD::Suld1DArrayI8Trap:
3999 Opc = NVPTX::SULD_1D_ARRAY_I8_TRAP;
4000 Ops.push_back(TexHandle);
4001 Ops.push_back(N->getOperand(2));
4002 Ops.push_back(N->getOperand(3));
4003 Ops.push_back(Chain);
4005 case NVPTXISD::Suld1DArrayI16Trap:
4006 Opc = NVPTX::SULD_1D_ARRAY_I16_TRAP;
4007 Ops.push_back(TexHandle);
4008 Ops.push_back(N->getOperand(2));
4009 Ops.push_back(N->getOperand(3));
4010 Ops.push_back(Chain);
4012 case NVPTXISD::Suld1DArrayI32Trap:
4013 Opc = NVPTX::SULD_1D_ARRAY_I32_TRAP;
4014 Ops.push_back(TexHandle);
4015 Ops.push_back(N->getOperand(2));
4016 Ops.push_back(N->getOperand(3));
4017 Ops.push_back(Chain);
4019 case NVPTXISD::Suld1DArrayI64Trap:
4020 Opc = NVPTX::SULD_1D_ARRAY_I64_TRAP;
4021 Ops.push_back(TexHandle);
4022 Ops.push_back(N->getOperand(2));
4023 Ops.push_back(N->getOperand(3));
4024 Ops.push_back(Chain);
4026 case NVPTXISD::Suld1DArrayV2I8Trap:
4027 Opc = NVPTX::SULD_1D_ARRAY_V2I8_TRAP;
4028 Ops.push_back(TexHandle);
4029 Ops.push_back(N->getOperand(2));
4030 Ops.push_back(N->getOperand(3));
4031 Ops.push_back(Chain);
4033 case NVPTXISD::Suld1DArrayV2I16Trap:
4034 Opc = NVPTX::SULD_1D_ARRAY_V2I16_TRAP;
4035 Ops.push_back(TexHandle);
4036 Ops.push_back(N->getOperand(2));
4037 Ops.push_back(N->getOperand(3));
4038 Ops.push_back(Chain);
4040 case NVPTXISD::Suld1DArrayV2I32Trap:
4041 Opc = NVPTX::SULD_1D_ARRAY_V2I32_TRAP;
4042 Ops.push_back(TexHandle);
4043 Ops.push_back(N->getOperand(2));
4044 Ops.push_back(N->getOperand(3));
4045 Ops.push_back(Chain);
4047 case NVPTXISD::Suld1DArrayV2I64Trap:
4048 Opc = NVPTX::SULD_1D_ARRAY_V2I64_TRAP;
4049 Ops.push_back(TexHandle);
4050 Ops.push_back(N->getOperand(2));
4051 Ops.push_back(N->getOperand(3));
4052 Ops.push_back(Chain);
4054 case NVPTXISD::Suld1DArrayV4I8Trap:
4055 Opc = NVPTX::SULD_1D_ARRAY_V4I8_TRAP;
4056 Ops.push_back(TexHandle);
4057 Ops.push_back(N->getOperand(2));
4058 Ops.push_back(N->getOperand(3));
4059 Ops.push_back(Chain);
4061 case NVPTXISD::Suld1DArrayV4I16Trap:
4062 Opc = NVPTX::SULD_1D_ARRAY_V4I16_TRAP;
4063 Ops.push_back(TexHandle);
4064 Ops.push_back(N->getOperand(2));
4065 Ops.push_back(N->getOperand(3));
4066 Ops.push_back(Chain);
4068 case NVPTXISD::Suld1DArrayV4I32Trap:
4069 Opc = NVPTX::SULD_1D_ARRAY_V4I32_TRAP;
4070 Ops.push_back(TexHandle);
4071 Ops.push_back(N->getOperand(2));
4072 Ops.push_back(N->getOperand(3));
4073 Ops.push_back(Chain);
4075 case NVPTXISD::Suld2DI8Trap:
4076 Opc = NVPTX::SULD_2D_I8_TRAP;
4077 Ops.push_back(TexHandle);
4078 Ops.push_back(N->getOperand(2));
4079 Ops.push_back(N->getOperand(3));
4080 Ops.push_back(Chain);
4082 case NVPTXISD::Suld2DI16Trap:
4083 Opc = NVPTX::SULD_2D_I16_TRAP;
4084 Ops.push_back(TexHandle);
4085 Ops.push_back(N->getOperand(2));
4086 Ops.push_back(N->getOperand(3));
4087 Ops.push_back(Chain);
4089 case NVPTXISD::Suld2DI32Trap:
4090 Opc = NVPTX::SULD_2D_I32_TRAP;
4091 Ops.push_back(TexHandle);
4092 Ops.push_back(N->getOperand(2));
4093 Ops.push_back(N->getOperand(3));
4094 Ops.push_back(Chain);
4096 case NVPTXISD::Suld2DI64Trap:
4097 Opc = NVPTX::SULD_2D_I64_TRAP;
4098 Ops.push_back(TexHandle);
4099 Ops.push_back(N->getOperand(2));
4100 Ops.push_back(N->getOperand(3));
4101 Ops.push_back(Chain);
4103 case NVPTXISD::Suld2DV2I8Trap:
4104 Opc = NVPTX::SULD_2D_V2I8_TRAP;
4105 Ops.push_back(TexHandle);
4106 Ops.push_back(N->getOperand(2));
4107 Ops.push_back(N->getOperand(3));
4108 Ops.push_back(Chain);
4110 case NVPTXISD::Suld2DV2I16Trap:
4111 Opc = NVPTX::SULD_2D_V2I16_TRAP;
4112 Ops.push_back(TexHandle);
4113 Ops.push_back(N->getOperand(2));
4114 Ops.push_back(N->getOperand(3));
4115 Ops.push_back(Chain);
4117 case NVPTXISD::Suld2DV2I32Trap:
4118 Opc = NVPTX::SULD_2D_V2I32_TRAP;
4119 Ops.push_back(TexHandle);
4120 Ops.push_back(N->getOperand(2));
4121 Ops.push_back(N->getOperand(3));
4122 Ops.push_back(Chain);
4124 case NVPTXISD::Suld2DV2I64Trap:
4125 Opc = NVPTX::SULD_2D_V2I64_TRAP;
4126 Ops.push_back(TexHandle);
4127 Ops.push_back(N->getOperand(2));
4128 Ops.push_back(N->getOperand(3));
4129 Ops.push_back(Chain);
4131 case NVPTXISD::Suld2DV4I8Trap:
4132 Opc = NVPTX::SULD_2D_V4I8_TRAP;
4133 Ops.push_back(TexHandle);
4134 Ops.push_back(N->getOperand(2));
4135 Ops.push_back(N->getOperand(3));
4136 Ops.push_back(Chain);
4138 case NVPTXISD::Suld2DV4I16Trap:
4139 Opc = NVPTX::SULD_2D_V4I16_TRAP;
4140 Ops.push_back(TexHandle);
4141 Ops.push_back(N->getOperand(2));
4142 Ops.push_back(N->getOperand(3));
4143 Ops.push_back(Chain);
4145 case NVPTXISD::Suld2DV4I32Trap:
4146 Opc = NVPTX::SULD_2D_V4I32_TRAP;
4147 Ops.push_back(TexHandle);
4148 Ops.push_back(N->getOperand(2));
4149 Ops.push_back(N->getOperand(3));
4150 Ops.push_back(Chain);
4152 case NVPTXISD::Suld2DArrayI8Trap:
4153 Opc = NVPTX::SULD_2D_ARRAY_I8_TRAP;
4154 Ops.push_back(TexHandle);
4155 Ops.push_back(N->getOperand(2));
4156 Ops.push_back(N->getOperand(3));
4157 Ops.push_back(N->getOperand(4));
4158 Ops.push_back(Chain);
4160 case NVPTXISD::Suld2DArrayI16Trap:
4161 Opc = NVPTX::SULD_2D_ARRAY_I16_TRAP;
4162 Ops.push_back(TexHandle);
4163 Ops.push_back(N->getOperand(2));
4164 Ops.push_back(N->getOperand(3));
4165 Ops.push_back(N->getOperand(4));
4166 Ops.push_back(Chain);
4168 case NVPTXISD::Suld2DArrayI32Trap:
4169 Opc = NVPTX::SULD_2D_ARRAY_I32_TRAP;
4170 Ops.push_back(TexHandle);
4171 Ops.push_back(N->getOperand(2));
4172 Ops.push_back(N->getOperand(3));
4173 Ops.push_back(N->getOperand(4));
4174 Ops.push_back(Chain);
4176 case NVPTXISD::Suld2DArrayI64Trap:
4177 Opc = NVPTX::SULD_2D_ARRAY_I64_TRAP;
4178 Ops.push_back(TexHandle);
4179 Ops.push_back(N->getOperand(2));
4180 Ops.push_back(N->getOperand(3));
4181 Ops.push_back(N->getOperand(4));
4182 Ops.push_back(Chain);
4184 case NVPTXISD::Suld2DArrayV2I8Trap:
4185 Opc = NVPTX::SULD_2D_ARRAY_V2I8_TRAP;
4186 Ops.push_back(TexHandle);
4187 Ops.push_back(N->getOperand(2));
4188 Ops.push_back(N->getOperand(3));
4189 Ops.push_back(N->getOperand(4));
4190 Ops.push_back(Chain);
4192 case NVPTXISD::Suld2DArrayV2I16Trap:
4193 Opc = NVPTX::SULD_2D_ARRAY_V2I16_TRAP;
4194 Ops.push_back(TexHandle);
4195 Ops.push_back(N->getOperand(2));
4196 Ops.push_back(N->getOperand(3));
4197 Ops.push_back(N->getOperand(4));
4198 Ops.push_back(Chain);
4200 case NVPTXISD::Suld2DArrayV2I32Trap:
4201 Opc = NVPTX::SULD_2D_ARRAY_V2I32_TRAP;
4202 Ops.push_back(TexHandle);
4203 Ops.push_back(N->getOperand(2));
4204 Ops.push_back(N->getOperand(3));
4205 Ops.push_back(N->getOperand(4));
4206 Ops.push_back(Chain);
4208 case NVPTXISD::Suld2DArrayV2I64Trap:
4209 Opc = NVPTX::SULD_2D_ARRAY_V2I64_TRAP;
4210 Ops.push_back(TexHandle);
4211 Ops.push_back(N->getOperand(2));
4212 Ops.push_back(N->getOperand(3));
4213 Ops.push_back(N->getOperand(4));
4214 Ops.push_back(Chain);
4216 case NVPTXISD::Suld2DArrayV4I8Trap:
4217 Opc = NVPTX::SULD_2D_ARRAY_V4I8_TRAP;
4218 Ops.push_back(TexHandle);
4219 Ops.push_back(N->getOperand(2));
4220 Ops.push_back(N->getOperand(3));
4221 Ops.push_back(N->getOperand(4));
4222 Ops.push_back(Chain);
4224 case NVPTXISD::Suld2DArrayV4I16Trap:
4225 Opc = NVPTX::SULD_2D_ARRAY_V4I16_TRAP;
4226 Ops.push_back(TexHandle);
4227 Ops.push_back(N->getOperand(2));
4228 Ops.push_back(N->getOperand(3));
4229 Ops.push_back(N->getOperand(4));
4230 Ops.push_back(Chain);
4232 case NVPTXISD::Suld2DArrayV4I32Trap:
4233 Opc = NVPTX::SULD_2D_ARRAY_V4I32_TRAP;
4234 Ops.push_back(TexHandle);
4235 Ops.push_back(N->getOperand(2));
4236 Ops.push_back(N->getOperand(3));
4237 Ops.push_back(N->getOperand(4));
4238 Ops.push_back(Chain);
4240 case NVPTXISD::Suld3DI8Trap:
4241 Opc = NVPTX::SULD_3D_I8_TRAP;
4242 Ops.push_back(TexHandle);
4243 Ops.push_back(N->getOperand(2));
4244 Ops.push_back(N->getOperand(3));
4245 Ops.push_back(N->getOperand(4));
4246 Ops.push_back(Chain);
4248 case NVPTXISD::Suld3DI16Trap:
4249 Opc = NVPTX::SULD_3D_I16_TRAP;
4250 Ops.push_back(TexHandle);
4251 Ops.push_back(N->getOperand(2));
4252 Ops.push_back(N->getOperand(3));
4253 Ops.push_back(N->getOperand(4));
4254 Ops.push_back(Chain);
4256 case NVPTXISD::Suld3DI32Trap:
4257 Opc = NVPTX::SULD_3D_I32_TRAP;
4258 Ops.push_back(TexHandle);
4259 Ops.push_back(N->getOperand(2));
4260 Ops.push_back(N->getOperand(3));
4261 Ops.push_back(N->getOperand(4));
4262 Ops.push_back(Chain);
4264 case NVPTXISD::Suld3DI64Trap:
4265 Opc = NVPTX::SULD_3D_I64_TRAP;
4266 Ops.push_back(TexHandle);
4267 Ops.push_back(N->getOperand(2));
4268 Ops.push_back(N->getOperand(3));
4269 Ops.push_back(N->getOperand(4));
4270 Ops.push_back(Chain);
4272 case NVPTXISD::Suld3DV2I8Trap:
4273 Opc = NVPTX::SULD_3D_V2I8_TRAP;
4274 Ops.push_back(TexHandle);
4275 Ops.push_back(N->getOperand(2));
4276 Ops.push_back(N->getOperand(3));
4277 Ops.push_back(N->getOperand(4));
4278 Ops.push_back(Chain);
4280 case NVPTXISD::Suld3DV2I16Trap:
4281 Opc = NVPTX::SULD_3D_V2I16_TRAP;
4282 Ops.push_back(TexHandle);
4283 Ops.push_back(N->getOperand(2));
4284 Ops.push_back(N->getOperand(3));
4285 Ops.push_back(N->getOperand(4));
4286 Ops.push_back(Chain);
4288 case NVPTXISD::Suld3DV2I32Trap:
4289 Opc = NVPTX::SULD_3D_V2I32_TRAP;
4290 Ops.push_back(TexHandle);
4291 Ops.push_back(N->getOperand(2));
4292 Ops.push_back(N->getOperand(3));
4293 Ops.push_back(N->getOperand(4));
4294 Ops.push_back(Chain);
4296 case NVPTXISD::Suld3DV2I64Trap:
4297 Opc = NVPTX::SULD_3D_V2I64_TRAP;
4298 Ops.push_back(TexHandle);
4299 Ops.push_back(N->getOperand(2));
4300 Ops.push_back(N->getOperand(3));
4301 Ops.push_back(N->getOperand(4));
4302 Ops.push_back(Chain);
4304 case NVPTXISD::Suld3DV4I8Trap:
4305 Opc = NVPTX::SULD_3D_V4I8_TRAP;
4306 Ops.push_back(TexHandle);
4307 Ops.push_back(N->getOperand(2));
4308 Ops.push_back(N->getOperand(3));
4309 Ops.push_back(N->getOperand(4));
4310 Ops.push_back(Chain);
4312 case NVPTXISD::Suld3DV4I16Trap:
4313 Opc = NVPTX::SULD_3D_V4I16_TRAP;
4314 Ops.push_back(TexHandle);
4315 Ops.push_back(N->getOperand(2));
4316 Ops.push_back(N->getOperand(3));
4317 Ops.push_back(N->getOperand(4));
4318 Ops.push_back(Chain);
4320 case NVPTXISD::Suld3DV4I32Trap:
4321 Opc = NVPTX::SULD_3D_V4I32_TRAP;
4322 Ops.push_back(TexHandle);
4323 Ops.push_back(N->getOperand(2));
4324 Ops.push_back(N->getOperand(3));
4325 Ops.push_back(N->getOperand(4));
4326 Ops.push_back(Chain);
4328 case NVPTXISD::Suld1DI8Zero:
4329 Opc = NVPTX::SULD_1D_I8_ZERO;
4330 Ops.push_back(TexHandle);
4331 Ops.push_back(N->getOperand(2));
4332 Ops.push_back(Chain);
4334 case NVPTXISD::Suld1DI16Zero:
4335 Opc = NVPTX::SULD_1D_I16_ZERO;
4336 Ops.push_back(TexHandle);
4337 Ops.push_back(N->getOperand(2));
4338 Ops.push_back(Chain);
4340 case NVPTXISD::Suld1DI32Zero:
4341 Opc = NVPTX::SULD_1D_I32_ZERO;
4342 Ops.push_back(TexHandle);
4343 Ops.push_back(N->getOperand(2));
4344 Ops.push_back(Chain);
4346 case NVPTXISD::Suld1DI64Zero:
4347 Opc = NVPTX::SULD_1D_I64_ZERO;
4348 Ops.push_back(TexHandle);
4349 Ops.push_back(N->getOperand(2));
4350 Ops.push_back(Chain);
4352 case NVPTXISD::Suld1DV2I8Zero:
4353 Opc = NVPTX::SULD_1D_V2I8_ZERO;
4354 Ops.push_back(TexHandle);
4355 Ops.push_back(N->getOperand(2));
4356 Ops.push_back(Chain);
4358 case NVPTXISD::Suld1DV2I16Zero:
4359 Opc = NVPTX::SULD_1D_V2I16_ZERO;
4360 Ops.push_back(TexHandle);
4361 Ops.push_back(N->getOperand(2));
4362 Ops.push_back(Chain);
4364 case NVPTXISD::Suld1DV2I32Zero:
4365 Opc = NVPTX::SULD_1D_V2I32_ZERO;
4366 Ops.push_back(TexHandle);
4367 Ops.push_back(N->getOperand(2));
4368 Ops.push_back(Chain);
4370 case NVPTXISD::Suld1DV2I64Zero:
4371 Opc = NVPTX::SULD_1D_V2I64_ZERO;
4372 Ops.push_back(TexHandle);
4373 Ops.push_back(N->getOperand(2));
4374 Ops.push_back(Chain);
4376 case NVPTXISD::Suld1DV4I8Zero:
4377 Opc = NVPTX::SULD_1D_V4I8_ZERO;
4378 Ops.push_back(TexHandle);
4379 Ops.push_back(N->getOperand(2));
4380 Ops.push_back(Chain);
4382 case NVPTXISD::Suld1DV4I16Zero:
4383 Opc = NVPTX::SULD_1D_V4I16_ZERO;
4384 Ops.push_back(TexHandle);
4385 Ops.push_back(N->getOperand(2));
4386 Ops.push_back(Chain);
4388 case NVPTXISD::Suld1DV4I32Zero:
4389 Opc = NVPTX::SULD_1D_V4I32_ZERO;
4390 Ops.push_back(TexHandle);
4391 Ops.push_back(N->getOperand(2));
4392 Ops.push_back(Chain);
4394 case NVPTXISD::Suld1DArrayI8Zero:
4395 Opc = NVPTX::SULD_1D_ARRAY_I8_ZERO;
4396 Ops.push_back(TexHandle);
4397 Ops.push_back(N->getOperand(2));
4398 Ops.push_back(N->getOperand(3));
4399 Ops.push_back(Chain);
4401 case NVPTXISD::Suld1DArrayI16Zero:
4402 Opc = NVPTX::SULD_1D_ARRAY_I16_ZERO;
4403 Ops.push_back(TexHandle);
4404 Ops.push_back(N->getOperand(2));
4405 Ops.push_back(N->getOperand(3));
4406 Ops.push_back(Chain);
4408 case NVPTXISD::Suld1DArrayI32Zero:
4409 Opc = NVPTX::SULD_1D_ARRAY_I32_ZERO;
4410 Ops.push_back(TexHandle);
4411 Ops.push_back(N->getOperand(2));
4412 Ops.push_back(N->getOperand(3));
4413 Ops.push_back(Chain);
4415 case NVPTXISD::Suld1DArrayI64Zero:
4416 Opc = NVPTX::SULD_1D_ARRAY_I64_ZERO;
4417 Ops.push_back(TexHandle);
4418 Ops.push_back(N->getOperand(2));
4419 Ops.push_back(N->getOperand(3));
4420 Ops.push_back(Chain);
4422 case NVPTXISD::Suld1DArrayV2I8Zero:
4423 Opc = NVPTX::SULD_1D_ARRAY_V2I8_ZERO;
4424 Ops.push_back(TexHandle);
4425 Ops.push_back(N->getOperand(2));
4426 Ops.push_back(N->getOperand(3));
4427 Ops.push_back(Chain);
4429 case NVPTXISD::Suld1DArrayV2I16Zero:
4430 Opc = NVPTX::SULD_1D_ARRAY_V2I16_ZERO;
4431 Ops.push_back(TexHandle);
4432 Ops.push_back(N->getOperand(2));
4433 Ops.push_back(N->getOperand(3));
4434 Ops.push_back(Chain);
4436 case NVPTXISD::Suld1DArrayV2I32Zero:
4437 Opc = NVPTX::SULD_1D_ARRAY_V2I32_ZERO;
4438 Ops.push_back(TexHandle);
4439 Ops.push_back(N->getOperand(2));
4440 Ops.push_back(N->getOperand(3));
4441 Ops.push_back(Chain);
4443 case NVPTXISD::Suld1DArrayV2I64Zero:
4444 Opc = NVPTX::SULD_1D_ARRAY_V2I64_ZERO;
4445 Ops.push_back(TexHandle);
4446 Ops.push_back(N->getOperand(2));
4447 Ops.push_back(N->getOperand(3));
4448 Ops.push_back(Chain);
4450 case NVPTXISD::Suld1DArrayV4I8Zero:
4451 Opc = NVPTX::SULD_1D_ARRAY_V4I8_ZERO;
4452 Ops.push_back(TexHandle);
4453 Ops.push_back(N->getOperand(2));
4454 Ops.push_back(N->getOperand(3));
4455 Ops.push_back(Chain);
4457 case NVPTXISD::Suld1DArrayV4I16Zero:
4458 Opc = NVPTX::SULD_1D_ARRAY_V4I16_ZERO;
4459 Ops.push_back(TexHandle);
4460 Ops.push_back(N->getOperand(2));
4461 Ops.push_back(N->getOperand(3));
4462 Ops.push_back(Chain);
4464 case NVPTXISD::Suld1DArrayV4I32Zero:
4465 Opc = NVPTX::SULD_1D_ARRAY_V4I32_ZERO;
4466 Ops.push_back(TexHandle);
4467 Ops.push_back(N->getOperand(2));
4468 Ops.push_back(N->getOperand(3));
4469 Ops.push_back(Chain);
4471 case NVPTXISD::Suld2DI8Zero:
4472 Opc = NVPTX::SULD_2D_I8_ZERO;
4473 Ops.push_back(TexHandle);
4474 Ops.push_back(N->getOperand(2));
4475 Ops.push_back(N->getOperand(3));
4476 Ops.push_back(Chain);
4478 case NVPTXISD::Suld2DI16Zero:
4479 Opc = NVPTX::SULD_2D_I16_ZERO;
4480 Ops.push_back(TexHandle);
4481 Ops.push_back(N->getOperand(2));
4482 Ops.push_back(N->getOperand(3));
4483 Ops.push_back(Chain);
4485 case NVPTXISD::Suld2DI32Zero:
4486 Opc = NVPTX::SULD_2D_I32_ZERO;
4487 Ops.push_back(TexHandle);
4488 Ops.push_back(N->getOperand(2));
4489 Ops.push_back(N->getOperand(3));
4490 Ops.push_back(Chain);
4492 case NVPTXISD::Suld2DI64Zero:
4493 Opc = NVPTX::SULD_2D_I64_ZERO;
4494 Ops.push_back(TexHandle);
4495 Ops.push_back(N->getOperand(2));
4496 Ops.push_back(N->getOperand(3));
4497 Ops.push_back(Chain);
4499 case NVPTXISD::Suld2DV2I8Zero:
4500 Opc = NVPTX::SULD_2D_V2I8_ZERO;
4501 Ops.push_back(TexHandle);
4502 Ops.push_back(N->getOperand(2));
4503 Ops.push_back(N->getOperand(3));
4504 Ops.push_back(Chain);
4506 case NVPTXISD::Suld2DV2I16Zero:
4507 Opc = NVPTX::SULD_2D_V2I16_ZERO;
4508 Ops.push_back(TexHandle);
4509 Ops.push_back(N->getOperand(2));
4510 Ops.push_back(N->getOperand(3));
4511 Ops.push_back(Chain);
4513 case NVPTXISD::Suld2DV2I32Zero:
4514 Opc = NVPTX::SULD_2D_V2I32_ZERO;
4515 Ops.push_back(TexHandle);
4516 Ops.push_back(N->getOperand(2));
4517 Ops.push_back(N->getOperand(3));
4518 Ops.push_back(Chain);
4520 case NVPTXISD::Suld2DV2I64Zero:
4521 Opc = NVPTX::SULD_2D_V2I64_ZERO;
4522 Ops.push_back(TexHandle);
4523 Ops.push_back(N->getOperand(2));
4524 Ops.push_back(N->getOperand(3));
4525 Ops.push_back(Chain);
4527 case NVPTXISD::Suld2DV4I8Zero:
4528 Opc = NVPTX::SULD_2D_V4I8_ZERO;
4529 Ops.push_back(TexHandle);
4530 Ops.push_back(N->getOperand(2));
4531 Ops.push_back(N->getOperand(3));
4532 Ops.push_back(Chain);
4534 case NVPTXISD::Suld2DV4I16Zero:
4535 Opc = NVPTX::SULD_2D_V4I16_ZERO;
4536 Ops.push_back(TexHandle);
4537 Ops.push_back(N->getOperand(2));
4538 Ops.push_back(N->getOperand(3));
4539 Ops.push_back(Chain);
4541 case NVPTXISD::Suld2DV4I32Zero:
4542 Opc = NVPTX::SULD_2D_V4I32_ZERO;
4543 Ops.push_back(TexHandle);
4544 Ops.push_back(N->getOperand(2));
4545 Ops.push_back(N->getOperand(3));
4546 Ops.push_back(Chain);
4548 case NVPTXISD::Suld2DArrayI8Zero:
4549 Opc = NVPTX::SULD_2D_ARRAY_I8_ZERO;
4550 Ops.push_back(TexHandle);
4551 Ops.push_back(N->getOperand(2));
4552 Ops.push_back(N->getOperand(3));
4553 Ops.push_back(N->getOperand(4));
4554 Ops.push_back(Chain);
4556 case NVPTXISD::Suld2DArrayI16Zero:
4557 Opc = NVPTX::SULD_2D_ARRAY_I16_ZERO;
4558 Ops.push_back(TexHandle);
4559 Ops.push_back(N->getOperand(2));
4560 Ops.push_back(N->getOperand(3));
4561 Ops.push_back(N->getOperand(4));
4562 Ops.push_back(Chain);
4564 case NVPTXISD::Suld2DArrayI32Zero:
4565 Opc = NVPTX::SULD_2D_ARRAY_I32_ZERO;
4566 Ops.push_back(TexHandle);
4567 Ops.push_back(N->getOperand(2));
4568 Ops.push_back(N->getOperand(3));
4569 Ops.push_back(N->getOperand(4));
4570 Ops.push_back(Chain);
4572 case NVPTXISD::Suld2DArrayI64Zero:
4573 Opc = NVPTX::SULD_2D_ARRAY_I64_ZERO;
4574 Ops.push_back(TexHandle);
4575 Ops.push_back(N->getOperand(2));
4576 Ops.push_back(N->getOperand(3));
4577 Ops.push_back(N->getOperand(4));
4578 Ops.push_back(Chain);
4580 case NVPTXISD::Suld2DArrayV2I8Zero:
4581 Opc = NVPTX::SULD_2D_ARRAY_V2I8_ZERO;
4582 Ops.push_back(TexHandle);
4583 Ops.push_back(N->getOperand(2));
4584 Ops.push_back(N->getOperand(3));
4585 Ops.push_back(N->getOperand(4));
4586 Ops.push_back(Chain);
4588 case NVPTXISD::Suld2DArrayV2I16Zero:
4589 Opc = NVPTX::SULD_2D_ARRAY_V2I16_ZERO;
4590 Ops.push_back(TexHandle);
4591 Ops.push_back(N->getOperand(2));
4592 Ops.push_back(N->getOperand(3));
4593 Ops.push_back(N->getOperand(4));
4594 Ops.push_back(Chain);
4596 case NVPTXISD::Suld2DArrayV2I32Zero:
4597 Opc = NVPTX::SULD_2D_ARRAY_V2I32_ZERO;
4598 Ops.push_back(TexHandle);
4599 Ops.push_back(N->getOperand(2));
4600 Ops.push_back(N->getOperand(3));
4601 Ops.push_back(N->getOperand(4));
4602 Ops.push_back(Chain);
4604 case NVPTXISD::Suld2DArrayV2I64Zero:
4605 Opc = NVPTX::SULD_2D_ARRAY_V2I64_ZERO;
4606 Ops.push_back(TexHandle);
4607 Ops.push_back(N->getOperand(2));
4608 Ops.push_back(N->getOperand(3));
4609 Ops.push_back(N->getOperand(4));
4610 Ops.push_back(Chain);
4612 case NVPTXISD::Suld2DArrayV4I8Zero:
4613 Opc = NVPTX::SULD_2D_ARRAY_V4I8_ZERO;
4614 Ops.push_back(TexHandle);
4615 Ops.push_back(N->getOperand(2));
4616 Ops.push_back(N->getOperand(3));
4617 Ops.push_back(N->getOperand(4));
4618 Ops.push_back(Chain);
4620 case NVPTXISD::Suld2DArrayV4I16Zero:
4621 Opc = NVPTX::SULD_2D_ARRAY_V4I16_ZERO;
4622 Ops.push_back(TexHandle);
4623 Ops.push_back(N->getOperand(2));
4624 Ops.push_back(N->getOperand(3));
4625 Ops.push_back(N->getOperand(4));
4626 Ops.push_back(Chain);
4628 case NVPTXISD::Suld2DArrayV4I32Zero:
4629 Opc = NVPTX::SULD_2D_ARRAY_V4I32_ZERO;
4630 Ops.push_back(TexHandle);
4631 Ops.push_back(N->getOperand(2));
4632 Ops.push_back(N->getOperand(3));
4633 Ops.push_back(N->getOperand(4));
4634 Ops.push_back(Chain);
4636 case NVPTXISD::Suld3DI8Zero:
4637 Opc = NVPTX::SULD_3D_I8_ZERO;
4638 Ops.push_back(TexHandle);
4639 Ops.push_back(N->getOperand(2));
4640 Ops.push_back(N->getOperand(3));
4641 Ops.push_back(N->getOperand(4));
4642 Ops.push_back(Chain);
4644 case NVPTXISD::Suld3DI16Zero:
4645 Opc = NVPTX::SULD_3D_I16_ZERO;
4646 Ops.push_back(TexHandle);
4647 Ops.push_back(N->getOperand(2));
4648 Ops.push_back(N->getOperand(3));
4649 Ops.push_back(N->getOperand(4));
4650 Ops.push_back(Chain);
4652 case NVPTXISD::Suld3DI32Zero:
4653 Opc = NVPTX::SULD_3D_I32_ZERO;
4654 Ops.push_back(TexHandle);
4655 Ops.push_back(N->getOperand(2));
4656 Ops.push_back(N->getOperand(3));
4657 Ops.push_back(N->getOperand(4));
4658 Ops.push_back(Chain);
4660 case NVPTXISD::Suld3DI64Zero:
4661 Opc = NVPTX::SULD_3D_I64_ZERO;
4662 Ops.push_back(TexHandle);
4663 Ops.push_back(N->getOperand(2));
4664 Ops.push_back(N->getOperand(3));
4665 Ops.push_back(N->getOperand(4));
4666 Ops.push_back(Chain);
4668 case NVPTXISD::Suld3DV2I8Zero:
4669 Opc = NVPTX::SULD_3D_V2I8_ZERO;
4670 Ops.push_back(TexHandle);
4671 Ops.push_back(N->getOperand(2));
4672 Ops.push_back(N->getOperand(3));
4673 Ops.push_back(N->getOperand(4));
4674 Ops.push_back(Chain);
4676 case NVPTXISD::Suld3DV2I16Zero:
4677 Opc = NVPTX::SULD_3D_V2I16_ZERO;
4678 Ops.push_back(TexHandle);
4679 Ops.push_back(N->getOperand(2));
4680 Ops.push_back(N->getOperand(3));
4681 Ops.push_back(N->getOperand(4));
4682 Ops.push_back(Chain);
4684 case NVPTXISD::Suld3DV2I32Zero:
4685 Opc = NVPTX::SULD_3D_V2I32_ZERO;
4686 Ops.push_back(TexHandle);
4687 Ops.push_back(N->getOperand(2));
4688 Ops.push_back(N->getOperand(3));
4689 Ops.push_back(N->getOperand(4));
4690 Ops.push_back(Chain);
4692 case NVPTXISD::Suld3DV2I64Zero:
4693 Opc = NVPTX::SULD_3D_V2I64_ZERO;
4694 Ops.push_back(TexHandle);
4695 Ops.push_back(N->getOperand(2));
4696 Ops.push_back(N->getOperand(3));
4697 Ops.push_back(N->getOperand(4));
4698 Ops.push_back(Chain);
4700 case NVPTXISD::Suld3DV4I8Zero:
4701 Opc = NVPTX::SULD_3D_V4I8_ZERO;
4702 Ops.push_back(TexHandle);
4703 Ops.push_back(N->getOperand(2));
4704 Ops.push_back(N->getOperand(3));
4705 Ops.push_back(N->getOperand(4));
4706 Ops.push_back(Chain);
4708 case NVPTXISD::Suld3DV4I16Zero:
4709 Opc = NVPTX::SULD_3D_V4I16_ZERO;
4710 Ops.push_back(TexHandle);
4711 Ops.push_back(N->getOperand(2));
4712 Ops.push_back(N->getOperand(3));
4713 Ops.push_back(N->getOperand(4));
4714 Ops.push_back(Chain);
4716 case NVPTXISD::Suld3DV4I32Zero:
4717 Opc = NVPTX::SULD_3D_V4I32_ZERO;
4718 Ops.push_back(TexHandle);
4719 Ops.push_back(N->getOperand(2));
4720 Ops.push_back(N->getOperand(3));
4721 Ops.push_back(N->getOperand(4));
4722 Ops.push_back(Chain);
4725 Ret = CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);
4730 /// SelectBFE - Look for instruction sequences that can be made more efficient
4731 /// by using the 'bfe' (bit-field extract) PTX instruction
4732 SDNode *NVPTXDAGToDAGISel::SelectBFE(SDNode *N) {
4733 SDValue LHS = N->getOperand(0);
4734 SDValue RHS = N->getOperand(1);
4738 bool IsSigned = false;
4740 if (N->getOpcode() == ISD::AND) {
4741 // Canonicalize the operands
4742 // We want 'and %val, %mask'
4743 if (isa<ConstantSDNode>(LHS) && !isa<ConstantSDNode>(RHS)) {
4744 std::swap(LHS, RHS);
4747 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(RHS);
4749 // We need a constant mask on the RHS of the AND
4753 // Extract the mask bits
4754 uint64_t MaskVal = Mask->getZExtValue();
4755 if (!isMask_64(MaskVal)) {
4756 // We *could* handle shifted masks here, but doing so would require an
4757 // 'and' operation to fix up the low-order bits so we would trade
4758 // shr+and for bfe+and, which has the same throughput
4762 // How many bits are in our mask?
4763 uint64_t NumBits = countTrailingOnes(MaskVal);
4764 Len = CurDAG->getTargetConstant(NumBits, MVT::i32);
4766 if (LHS.getOpcode() == ISD::SRL || LHS.getOpcode() == ISD::SRA) {
4767 // We have a 'srl/and' pair, extract the effective start bit and length
4768 Val = LHS.getNode()->getOperand(0);
4769 Start = LHS.getNode()->getOperand(1);
4770 ConstantSDNode *StartConst = dyn_cast<ConstantSDNode>(Start);
4772 uint64_t StartVal = StartConst->getZExtValue();
4773 // How many "good" bits do we have left? "good" is defined here as bits
4774 // that exist in the original value, not shifted in.
4775 uint64_t GoodBits = Start.getValueType().getSizeInBits() - StartVal;
4776 if (NumBits > GoodBits) {
4777 // Do not handle the case where bits have been shifted in. In theory
4778 // we could handle this, but the cost is likely higher than just
4779 // emitting the srl/and pair.
4782 Start = CurDAG->getTargetConstant(StartVal, MVT::i32);
4784 // Do not handle the case where the shift amount (can be zero if no srl
4785 // was found) is not constant. We could handle this case, but it would
4786 // require run-time logic that would be more expensive than just
4787 // emitting the srl/and pair.
4791 // Do not handle the case where the LHS of the and is not a shift. While
4792 // it would be trivial to handle this case, it would just transform
4793 // 'and' -> 'bfe', but 'and' has higher-throughput.
4796 } else if (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) {
4797 if (LHS->getOpcode() == ISD::AND) {
4798 ConstantSDNode *ShiftCnst = dyn_cast<ConstantSDNode>(RHS);
4800 // Shift amount must be constant
4804 uint64_t ShiftAmt = ShiftCnst->getZExtValue();
4806 SDValue AndLHS = LHS->getOperand(0);
4807 SDValue AndRHS = LHS->getOperand(1);
4809 // Canonicalize the AND to have the mask on the RHS
4810 if (isa<ConstantSDNode>(AndLHS)) {
4811 std::swap(AndLHS, AndRHS);
4814 ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(AndRHS);
4816 // Mask must be constant
4820 uint64_t MaskVal = MaskCnst->getZExtValue();
4823 if (isMask_64(MaskVal)) {
4825 // The number of bits in the result bitfield will be the number of
4826 // trailing ones (the AND) minus the number of bits we shift off
4827 NumBits = countTrailingOnes(MaskVal) - ShiftAmt;
4828 } else if (isShiftedMask_64(MaskVal)) {
4829 NumZeros = countTrailingZeros(MaskVal);
4830 unsigned NumOnes = countTrailingOnes(MaskVal >> NumZeros);
4831 // The number of bits in the result bitfield will be the number of
4832 // trailing zeros plus the number of set bits in the mask minus the
4833 // number of bits we shift off
4834 NumBits = NumZeros + NumOnes - ShiftAmt;
4836 // This is not a mask we can handle
4840 if (ShiftAmt < NumZeros) {
4841 // Handling this case would require extra logic that would make this
4842 // transformation non-profitable
4847 Start = CurDAG->getTargetConstant(ShiftAmt, MVT::i32);
4848 Len = CurDAG->getTargetConstant(NumBits, MVT::i32);
4849 } else if (LHS->getOpcode() == ISD::SHL) {
4850 // Here, we have a pattern like:
4852 // (sra (shl val, NN), MM)
4854 // (srl (shl val, NN), MM)
4856 // If MM >= NN, we can efficiently optimize this with bfe
4857 Val = LHS->getOperand(0);
4859 SDValue ShlRHS = LHS->getOperand(1);
4860 ConstantSDNode *ShlCnst = dyn_cast<ConstantSDNode>(ShlRHS);
4862 // Shift amount must be constant
4865 uint64_t InnerShiftAmt = ShlCnst->getZExtValue();
4867 SDValue ShrRHS = RHS;
4868 ConstantSDNode *ShrCnst = dyn_cast<ConstantSDNode>(ShrRHS);
4870 // Shift amount must be constant
4873 uint64_t OuterShiftAmt = ShrCnst->getZExtValue();
4875 // To avoid extra codegen and be profitable, we need Outer >= Inner
4876 if (OuterShiftAmt < InnerShiftAmt) {
4880 // If the outer shift is more than the type size, we have no bitfield to
4881 // extract (since we also check that the inner shift is <= the outer shift
4882 // then this also implies that the inner shift is < the type size)
4883 if (OuterShiftAmt >= Val.getValueType().getSizeInBits()) {
4888 CurDAG->getTargetConstant(OuterShiftAmt - InnerShiftAmt, MVT::i32);
4890 CurDAG->getTargetConstant(Val.getValueType().getSizeInBits() -
4891 OuterShiftAmt, MVT::i32);
4893 if (N->getOpcode() == ISD::SRA) {
4894 // If we have a arithmetic right shift, we need to use the signed bfe
4909 // For the BFE operations we form here from "and" and "srl", always use the
4910 // unsigned variants.
4911 if (Val.getValueType() == MVT::i32) {
4913 Opc = NVPTX::BFE_S32rii;
4915 Opc = NVPTX::BFE_U32rii;
4917 } else if (Val.getValueType() == MVT::i64) {
4919 Opc = NVPTX::BFE_S64rii;
4921 Opc = NVPTX::BFE_U64rii;
4924 // We cannot handle this type
4933 CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);
4938 // SelectDirectAddr - Match a direct address for DAG.
4939 // A direct address could be a globaladdress or externalsymbol.
4940 bool NVPTXDAGToDAGISel::SelectDirectAddr(SDValue N, SDValue &Address) {
4941 // Return true if TGA or ES.
4942 if (N.getOpcode() == ISD::TargetGlobalAddress ||
4943 N.getOpcode() == ISD::TargetExternalSymbol) {
4947 if (N.getOpcode() == NVPTXISD::Wrapper) {
4948 Address = N.getOperand(0);
4951 if (N.getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
4952 unsigned IID = cast<ConstantSDNode>(N.getOperand(0))->getZExtValue();
4953 if (IID == Intrinsic::nvvm_ptr_gen_to_param)
4954 if (N.getOperand(1).getOpcode() == NVPTXISD::MoveParam)
4955 return (SelectDirectAddr(N.getOperand(1).getOperand(0), Address));
4961 bool NVPTXDAGToDAGISel::SelectADDRsi_imp(
4962 SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) {
4963 if (Addr.getOpcode() == ISD::ADD) {
4964 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
4965 SDValue base = Addr.getOperand(0);
4966 if (SelectDirectAddr(base, Base)) {
4967 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), mvt);
4976 bool NVPTXDAGToDAGISel::SelectADDRsi(SDNode *OpNode, SDValue Addr,
4977 SDValue &Base, SDValue &Offset) {
4978 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i32);
4982 bool NVPTXDAGToDAGISel::SelectADDRsi64(SDNode *OpNode, SDValue Addr,
4983 SDValue &Base, SDValue &Offset) {
4984 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i64);
4988 bool NVPTXDAGToDAGISel::SelectADDRri_imp(
4989 SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) {
4990 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
4991 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
4992 Offset = CurDAG->getTargetConstant(0, mvt);
4995 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
4996 Addr.getOpcode() == ISD::TargetGlobalAddress)
4997 return false; // direct calls.
4999 if (Addr.getOpcode() == ISD::ADD) {
5000 if (SelectDirectAddr(Addr.getOperand(0), Addr)) {
5003 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
5004 if (FrameIndexSDNode *FIN =
5005 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
5006 // Constant offset from frame ref.
5007 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
5009 Base = Addr.getOperand(0);
5010 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), mvt);
5018 bool NVPTXDAGToDAGISel::SelectADDRri(SDNode *OpNode, SDValue Addr,
5019 SDValue &Base, SDValue &Offset) {
5020 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i32);
5024 bool NVPTXDAGToDAGISel::SelectADDRri64(SDNode *OpNode, SDValue Addr,
5025 SDValue &Base, SDValue &Offset) {
5026 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i64);
5029 bool NVPTXDAGToDAGISel::ChkMemSDNodeAddressSpace(SDNode *N,
5030 unsigned int spN) const {
5031 const Value *Src = nullptr;
5032 if (MemSDNode *mN = dyn_cast<MemSDNode>(N)) {
5033 if (spN == 0 && mN->getMemOperand()->getPseudoValue())
5035 Src = mN->getMemOperand()->getValue();
5039 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
5040 return (PT->getAddressSpace() == spN);
5044 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
5045 /// inline asm expressions.
5046 bool NVPTXDAGToDAGISel::SelectInlineAsmMemoryOperand(
5047 const SDValue &Op, char ConstraintCode, std::vector<SDValue> &OutOps) {
5049 switch (ConstraintCode) {
5053 if (SelectDirectAddr(Op, Op0)) {
5054 OutOps.push_back(Op0);
5055 OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
5058 if (SelectADDRri(Op.getNode(), Op, Op0, Op1)) {
5059 OutOps.push_back(Op0);
5060 OutOps.push_back(Op1);