1 //===-- NVPTXISelDAGToDAG.cpp - A dag to dag inst selector for NVPTX ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the NVPTX target.
12 //===----------------------------------------------------------------------===//
14 #include "NVPTXISelDAGToDAG.h"
15 #include "llvm/IR/GlobalValue.h"
16 #include "llvm/IR/Instructions.h"
17 #include "llvm/Support/CommandLine.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Support/raw_ostream.h"
21 #include "llvm/Target/TargetIntrinsicInfo.h"
25 #define DEBUG_TYPE "nvptx-isel"
27 static cl::opt<int> UsePrecDivF32(
28 "nvptx-prec-divf32", cl::ZeroOrMore, cl::Hidden,
29 cl::desc("NVPTX Specifies: 0 use div.approx, 1 use div.full, 2 use"
30 " IEEE Compliant F32 div.rnd if available."),
34 UsePrecSqrtF32("nvptx-prec-sqrtf32", cl::Hidden,
35 cl::desc("NVPTX Specific: 0 use sqrt.approx, 1 use sqrt.rn."),
39 FtzEnabled("nvptx-f32ftz", cl::ZeroOrMore, cl::Hidden,
40 cl::desc("NVPTX Specific: Flush f32 subnormals to sign-preserving zero."),
44 /// createNVPTXISelDag - This pass converts a legalized DAG into a
45 /// NVPTX-specific DAG, ready for instruction scheduling.
46 FunctionPass *llvm::createNVPTXISelDag(NVPTXTargetMachine &TM,
47 llvm::CodeGenOpt::Level OptLevel) {
48 return new NVPTXDAGToDAGISel(TM, OptLevel);
51 NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
52 CodeGenOpt::Level OptLevel)
53 : SelectionDAGISel(tm, OptLevel), TM(tm) {
54 doMulWide = (OptLevel > 0);
57 bool NVPTXDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
58 Subtarget = &static_cast<const NVPTXSubtarget &>(MF.getSubtarget());
59 return SelectionDAGISel::runOnMachineFunction(MF);
62 int NVPTXDAGToDAGISel::getDivF32Level() const {
63 if (UsePrecDivF32.getNumOccurrences() > 0) {
64 // If nvptx-prec-div32=N is used on the command-line, always honor it
67 // Otherwise, use div.approx if fast math is enabled
68 if (TM.Options.UnsafeFPMath)
75 bool NVPTXDAGToDAGISel::usePrecSqrtF32() const {
76 if (UsePrecSqrtF32.getNumOccurrences() > 0) {
77 // If nvptx-prec-sqrtf32 is used on the command-line, always honor it
78 return UsePrecSqrtF32;
80 // Otherwise, use sqrt.approx if fast math is enabled
81 return !TM.Options.UnsafeFPMath;
85 bool NVPTXDAGToDAGISel::useF32FTZ() const {
86 if (FtzEnabled.getNumOccurrences() > 0) {
87 // If nvptx-f32ftz is used on the command-line, always honor it
90 const Function *F = MF->getFunction();
91 // Otherwise, check for an nvptx-f32ftz attribute on the function
92 if (F->hasFnAttribute("nvptx-f32ftz"))
93 return F->getFnAttribute("nvptx-f32ftz").getValueAsString() == "true";
99 bool NVPTXDAGToDAGISel::allowFMA() const {
100 const NVPTXTargetLowering *TL = Subtarget->getTargetLowering();
101 return TL->allowFMA(*MF, OptLevel);
104 /// Select - Select instructions not customized! Used for
105 /// expanded, promoted and normal instructions.
106 SDNode *NVPTXDAGToDAGISel::Select(SDNode *N) {
108 if (N->isMachineOpcode()) {
110 return nullptr; // Already selected.
113 SDNode *ResNode = nullptr;
114 switch (N->getOpcode()) {
116 ResNode = SelectLoad(N);
119 ResNode = SelectStore(N);
121 case NVPTXISD::LoadV2:
122 case NVPTXISD::LoadV4:
123 ResNode = SelectLoadVector(N);
125 case NVPTXISD::LDGV2:
126 case NVPTXISD::LDGV4:
127 case NVPTXISD::LDUV2:
128 case NVPTXISD::LDUV4:
129 ResNode = SelectLDGLDU(N);
131 case NVPTXISD::StoreV2:
132 case NVPTXISD::StoreV4:
133 ResNode = SelectStoreVector(N);
135 case NVPTXISD::LoadParam:
136 case NVPTXISD::LoadParamV2:
137 case NVPTXISD::LoadParamV4:
138 ResNode = SelectLoadParam(N);
140 case NVPTXISD::StoreRetval:
141 case NVPTXISD::StoreRetvalV2:
142 case NVPTXISD::StoreRetvalV4:
143 ResNode = SelectStoreRetval(N);
145 case NVPTXISD::StoreParam:
146 case NVPTXISD::StoreParamV2:
147 case NVPTXISD::StoreParamV4:
148 case NVPTXISD::StoreParamS32:
149 case NVPTXISD::StoreParamU32:
150 ResNode = SelectStoreParam(N);
152 case ISD::INTRINSIC_WO_CHAIN:
153 ResNode = SelectIntrinsicNoChain(N);
155 case ISD::INTRINSIC_W_CHAIN:
156 ResNode = SelectIntrinsicChain(N);
158 case NVPTXISD::Tex1DFloatS32:
159 case NVPTXISD::Tex1DFloatFloat:
160 case NVPTXISD::Tex1DFloatFloatLevel:
161 case NVPTXISD::Tex1DFloatFloatGrad:
162 case NVPTXISD::Tex1DS32S32:
163 case NVPTXISD::Tex1DS32Float:
164 case NVPTXISD::Tex1DS32FloatLevel:
165 case NVPTXISD::Tex1DS32FloatGrad:
166 case NVPTXISD::Tex1DU32S32:
167 case NVPTXISD::Tex1DU32Float:
168 case NVPTXISD::Tex1DU32FloatLevel:
169 case NVPTXISD::Tex1DU32FloatGrad:
170 case NVPTXISD::Tex1DArrayFloatS32:
171 case NVPTXISD::Tex1DArrayFloatFloat:
172 case NVPTXISD::Tex1DArrayFloatFloatLevel:
173 case NVPTXISD::Tex1DArrayFloatFloatGrad:
174 case NVPTXISD::Tex1DArrayS32S32:
175 case NVPTXISD::Tex1DArrayS32Float:
176 case NVPTXISD::Tex1DArrayS32FloatLevel:
177 case NVPTXISD::Tex1DArrayS32FloatGrad:
178 case NVPTXISD::Tex1DArrayU32S32:
179 case NVPTXISD::Tex1DArrayU32Float:
180 case NVPTXISD::Tex1DArrayU32FloatLevel:
181 case NVPTXISD::Tex1DArrayU32FloatGrad:
182 case NVPTXISD::Tex2DFloatS32:
183 case NVPTXISD::Tex2DFloatFloat:
184 case NVPTXISD::Tex2DFloatFloatLevel:
185 case NVPTXISD::Tex2DFloatFloatGrad:
186 case NVPTXISD::Tex2DS32S32:
187 case NVPTXISD::Tex2DS32Float:
188 case NVPTXISD::Tex2DS32FloatLevel:
189 case NVPTXISD::Tex2DS32FloatGrad:
190 case NVPTXISD::Tex2DU32S32:
191 case NVPTXISD::Tex2DU32Float:
192 case NVPTXISD::Tex2DU32FloatLevel:
193 case NVPTXISD::Tex2DU32FloatGrad:
194 case NVPTXISD::Tex2DArrayFloatS32:
195 case NVPTXISD::Tex2DArrayFloatFloat:
196 case NVPTXISD::Tex2DArrayFloatFloatLevel:
197 case NVPTXISD::Tex2DArrayFloatFloatGrad:
198 case NVPTXISD::Tex2DArrayS32S32:
199 case NVPTXISD::Tex2DArrayS32Float:
200 case NVPTXISD::Tex2DArrayS32FloatLevel:
201 case NVPTXISD::Tex2DArrayS32FloatGrad:
202 case NVPTXISD::Tex2DArrayU32S32:
203 case NVPTXISD::Tex2DArrayU32Float:
204 case NVPTXISD::Tex2DArrayU32FloatLevel:
205 case NVPTXISD::Tex2DArrayU32FloatGrad:
206 case NVPTXISD::Tex3DFloatS32:
207 case NVPTXISD::Tex3DFloatFloat:
208 case NVPTXISD::Tex3DFloatFloatLevel:
209 case NVPTXISD::Tex3DFloatFloatGrad:
210 case NVPTXISD::Tex3DS32S32:
211 case NVPTXISD::Tex3DS32Float:
212 case NVPTXISD::Tex3DS32FloatLevel:
213 case NVPTXISD::Tex3DS32FloatGrad:
214 case NVPTXISD::Tex3DU32S32:
215 case NVPTXISD::Tex3DU32Float:
216 case NVPTXISD::Tex3DU32FloatLevel:
217 case NVPTXISD::Tex3DU32FloatGrad:
218 case NVPTXISD::TexCubeFloatFloat:
219 case NVPTXISD::TexCubeFloatFloatLevel:
220 case NVPTXISD::TexCubeS32Float:
221 case NVPTXISD::TexCubeS32FloatLevel:
222 case NVPTXISD::TexCubeU32Float:
223 case NVPTXISD::TexCubeU32FloatLevel:
224 case NVPTXISD::TexCubeArrayFloatFloat:
225 case NVPTXISD::TexCubeArrayFloatFloatLevel:
226 case NVPTXISD::TexCubeArrayS32Float:
227 case NVPTXISD::TexCubeArrayS32FloatLevel:
228 case NVPTXISD::TexCubeArrayU32Float:
229 case NVPTXISD::TexCubeArrayU32FloatLevel:
230 case NVPTXISD::Tld4R2DFloatFloat:
231 case NVPTXISD::Tld4G2DFloatFloat:
232 case NVPTXISD::Tld4B2DFloatFloat:
233 case NVPTXISD::Tld4A2DFloatFloat:
234 case NVPTXISD::Tld4R2DS64Float:
235 case NVPTXISD::Tld4G2DS64Float:
236 case NVPTXISD::Tld4B2DS64Float:
237 case NVPTXISD::Tld4A2DS64Float:
238 case NVPTXISD::Tld4R2DU64Float:
239 case NVPTXISD::Tld4G2DU64Float:
240 case NVPTXISD::Tld4B2DU64Float:
241 case NVPTXISD::Tld4A2DU64Float:
242 case NVPTXISD::TexUnified1DFloatS32:
243 case NVPTXISD::TexUnified1DFloatFloat:
244 case NVPTXISD::TexUnified1DFloatFloatLevel:
245 case NVPTXISD::TexUnified1DFloatFloatGrad:
246 case NVPTXISD::TexUnified1DS32S32:
247 case NVPTXISD::TexUnified1DS32Float:
248 case NVPTXISD::TexUnified1DS32FloatLevel:
249 case NVPTXISD::TexUnified1DS32FloatGrad:
250 case NVPTXISD::TexUnified1DU32S32:
251 case NVPTXISD::TexUnified1DU32Float:
252 case NVPTXISD::TexUnified1DU32FloatLevel:
253 case NVPTXISD::TexUnified1DU32FloatGrad:
254 case NVPTXISD::TexUnified1DArrayFloatS32:
255 case NVPTXISD::TexUnified1DArrayFloatFloat:
256 case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
257 case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
258 case NVPTXISD::TexUnified1DArrayS32S32:
259 case NVPTXISD::TexUnified1DArrayS32Float:
260 case NVPTXISD::TexUnified1DArrayS32FloatLevel:
261 case NVPTXISD::TexUnified1DArrayS32FloatGrad:
262 case NVPTXISD::TexUnified1DArrayU32S32:
263 case NVPTXISD::TexUnified1DArrayU32Float:
264 case NVPTXISD::TexUnified1DArrayU32FloatLevel:
265 case NVPTXISD::TexUnified1DArrayU32FloatGrad:
266 case NVPTXISD::TexUnified2DFloatS32:
267 case NVPTXISD::TexUnified2DFloatFloat:
268 case NVPTXISD::TexUnified2DFloatFloatLevel:
269 case NVPTXISD::TexUnified2DFloatFloatGrad:
270 case NVPTXISD::TexUnified2DS32S32:
271 case NVPTXISD::TexUnified2DS32Float:
272 case NVPTXISD::TexUnified2DS32FloatLevel:
273 case NVPTXISD::TexUnified2DS32FloatGrad:
274 case NVPTXISD::TexUnified2DU32S32:
275 case NVPTXISD::TexUnified2DU32Float:
276 case NVPTXISD::TexUnified2DU32FloatLevel:
277 case NVPTXISD::TexUnified2DU32FloatGrad:
278 case NVPTXISD::TexUnified2DArrayFloatS32:
279 case NVPTXISD::TexUnified2DArrayFloatFloat:
280 case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
281 case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
282 case NVPTXISD::TexUnified2DArrayS32S32:
283 case NVPTXISD::TexUnified2DArrayS32Float:
284 case NVPTXISD::TexUnified2DArrayS32FloatLevel:
285 case NVPTXISD::TexUnified2DArrayS32FloatGrad:
286 case NVPTXISD::TexUnified2DArrayU32S32:
287 case NVPTXISD::TexUnified2DArrayU32Float:
288 case NVPTXISD::TexUnified2DArrayU32FloatLevel:
289 case NVPTXISD::TexUnified2DArrayU32FloatGrad:
290 case NVPTXISD::TexUnified3DFloatS32:
291 case NVPTXISD::TexUnified3DFloatFloat:
292 case NVPTXISD::TexUnified3DFloatFloatLevel:
293 case NVPTXISD::TexUnified3DFloatFloatGrad:
294 case NVPTXISD::TexUnified3DS32S32:
295 case NVPTXISD::TexUnified3DS32Float:
296 case NVPTXISD::TexUnified3DS32FloatLevel:
297 case NVPTXISD::TexUnified3DS32FloatGrad:
298 case NVPTXISD::TexUnified3DU32S32:
299 case NVPTXISD::TexUnified3DU32Float:
300 case NVPTXISD::TexUnified3DU32FloatLevel:
301 case NVPTXISD::TexUnified3DU32FloatGrad:
302 case NVPTXISD::TexUnifiedCubeFloatFloat:
303 case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
304 case NVPTXISD::TexUnifiedCubeS32Float:
305 case NVPTXISD::TexUnifiedCubeS32FloatLevel:
306 case NVPTXISD::TexUnifiedCubeU32Float:
307 case NVPTXISD::TexUnifiedCubeU32FloatLevel:
308 case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
309 case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
310 case NVPTXISD::TexUnifiedCubeArrayS32Float:
311 case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
312 case NVPTXISD::TexUnifiedCubeArrayU32Float:
313 case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
314 case NVPTXISD::Tld4UnifiedR2DFloatFloat:
315 case NVPTXISD::Tld4UnifiedG2DFloatFloat:
316 case NVPTXISD::Tld4UnifiedB2DFloatFloat:
317 case NVPTXISD::Tld4UnifiedA2DFloatFloat:
318 case NVPTXISD::Tld4UnifiedR2DS64Float:
319 case NVPTXISD::Tld4UnifiedG2DS64Float:
320 case NVPTXISD::Tld4UnifiedB2DS64Float:
321 case NVPTXISD::Tld4UnifiedA2DS64Float:
322 case NVPTXISD::Tld4UnifiedR2DU64Float:
323 case NVPTXISD::Tld4UnifiedG2DU64Float:
324 case NVPTXISD::Tld4UnifiedB2DU64Float:
325 case NVPTXISD::Tld4UnifiedA2DU64Float:
326 ResNode = SelectTextureIntrinsic(N);
328 case NVPTXISD::Suld1DI8Clamp:
329 case NVPTXISD::Suld1DI16Clamp:
330 case NVPTXISD::Suld1DI32Clamp:
331 case NVPTXISD::Suld1DI64Clamp:
332 case NVPTXISD::Suld1DV2I8Clamp:
333 case NVPTXISD::Suld1DV2I16Clamp:
334 case NVPTXISD::Suld1DV2I32Clamp:
335 case NVPTXISD::Suld1DV2I64Clamp:
336 case NVPTXISD::Suld1DV4I8Clamp:
337 case NVPTXISD::Suld1DV4I16Clamp:
338 case NVPTXISD::Suld1DV4I32Clamp:
339 case NVPTXISD::Suld1DArrayI8Clamp:
340 case NVPTXISD::Suld1DArrayI16Clamp:
341 case NVPTXISD::Suld1DArrayI32Clamp:
342 case NVPTXISD::Suld1DArrayI64Clamp:
343 case NVPTXISD::Suld1DArrayV2I8Clamp:
344 case NVPTXISD::Suld1DArrayV2I16Clamp:
345 case NVPTXISD::Suld1DArrayV2I32Clamp:
346 case NVPTXISD::Suld1DArrayV2I64Clamp:
347 case NVPTXISD::Suld1DArrayV4I8Clamp:
348 case NVPTXISD::Suld1DArrayV4I16Clamp:
349 case NVPTXISD::Suld1DArrayV4I32Clamp:
350 case NVPTXISD::Suld2DI8Clamp:
351 case NVPTXISD::Suld2DI16Clamp:
352 case NVPTXISD::Suld2DI32Clamp:
353 case NVPTXISD::Suld2DI64Clamp:
354 case NVPTXISD::Suld2DV2I8Clamp:
355 case NVPTXISD::Suld2DV2I16Clamp:
356 case NVPTXISD::Suld2DV2I32Clamp:
357 case NVPTXISD::Suld2DV2I64Clamp:
358 case NVPTXISD::Suld2DV4I8Clamp:
359 case NVPTXISD::Suld2DV4I16Clamp:
360 case NVPTXISD::Suld2DV4I32Clamp:
361 case NVPTXISD::Suld2DArrayI8Clamp:
362 case NVPTXISD::Suld2DArrayI16Clamp:
363 case NVPTXISD::Suld2DArrayI32Clamp:
364 case NVPTXISD::Suld2DArrayI64Clamp:
365 case NVPTXISD::Suld2DArrayV2I8Clamp:
366 case NVPTXISD::Suld2DArrayV2I16Clamp:
367 case NVPTXISD::Suld2DArrayV2I32Clamp:
368 case NVPTXISD::Suld2DArrayV2I64Clamp:
369 case NVPTXISD::Suld2DArrayV4I8Clamp:
370 case NVPTXISD::Suld2DArrayV4I16Clamp:
371 case NVPTXISD::Suld2DArrayV4I32Clamp:
372 case NVPTXISD::Suld3DI8Clamp:
373 case NVPTXISD::Suld3DI16Clamp:
374 case NVPTXISD::Suld3DI32Clamp:
375 case NVPTXISD::Suld3DI64Clamp:
376 case NVPTXISD::Suld3DV2I8Clamp:
377 case NVPTXISD::Suld3DV2I16Clamp:
378 case NVPTXISD::Suld3DV2I32Clamp:
379 case NVPTXISD::Suld3DV2I64Clamp:
380 case NVPTXISD::Suld3DV4I8Clamp:
381 case NVPTXISD::Suld3DV4I16Clamp:
382 case NVPTXISD::Suld3DV4I32Clamp:
383 case NVPTXISD::Suld1DI8Trap:
384 case NVPTXISD::Suld1DI16Trap:
385 case NVPTXISD::Suld1DI32Trap:
386 case NVPTXISD::Suld1DI64Trap:
387 case NVPTXISD::Suld1DV2I8Trap:
388 case NVPTXISD::Suld1DV2I16Trap:
389 case NVPTXISD::Suld1DV2I32Trap:
390 case NVPTXISD::Suld1DV2I64Trap:
391 case NVPTXISD::Suld1DV4I8Trap:
392 case NVPTXISD::Suld1DV4I16Trap:
393 case NVPTXISD::Suld1DV4I32Trap:
394 case NVPTXISD::Suld1DArrayI8Trap:
395 case NVPTXISD::Suld1DArrayI16Trap:
396 case NVPTXISD::Suld1DArrayI32Trap:
397 case NVPTXISD::Suld1DArrayI64Trap:
398 case NVPTXISD::Suld1DArrayV2I8Trap:
399 case NVPTXISD::Suld1DArrayV2I16Trap:
400 case NVPTXISD::Suld1DArrayV2I32Trap:
401 case NVPTXISD::Suld1DArrayV2I64Trap:
402 case NVPTXISD::Suld1DArrayV4I8Trap:
403 case NVPTXISD::Suld1DArrayV4I16Trap:
404 case NVPTXISD::Suld1DArrayV4I32Trap:
405 case NVPTXISD::Suld2DI8Trap:
406 case NVPTXISD::Suld2DI16Trap:
407 case NVPTXISD::Suld2DI32Trap:
408 case NVPTXISD::Suld2DI64Trap:
409 case NVPTXISD::Suld2DV2I8Trap:
410 case NVPTXISD::Suld2DV2I16Trap:
411 case NVPTXISD::Suld2DV2I32Trap:
412 case NVPTXISD::Suld2DV2I64Trap:
413 case NVPTXISD::Suld2DV4I8Trap:
414 case NVPTXISD::Suld2DV4I16Trap:
415 case NVPTXISD::Suld2DV4I32Trap:
416 case NVPTXISD::Suld2DArrayI8Trap:
417 case NVPTXISD::Suld2DArrayI16Trap:
418 case NVPTXISD::Suld2DArrayI32Trap:
419 case NVPTXISD::Suld2DArrayI64Trap:
420 case NVPTXISD::Suld2DArrayV2I8Trap:
421 case NVPTXISD::Suld2DArrayV2I16Trap:
422 case NVPTXISD::Suld2DArrayV2I32Trap:
423 case NVPTXISD::Suld2DArrayV2I64Trap:
424 case NVPTXISD::Suld2DArrayV4I8Trap:
425 case NVPTXISD::Suld2DArrayV4I16Trap:
426 case NVPTXISD::Suld2DArrayV4I32Trap:
427 case NVPTXISD::Suld3DI8Trap:
428 case NVPTXISD::Suld3DI16Trap:
429 case NVPTXISD::Suld3DI32Trap:
430 case NVPTXISD::Suld3DI64Trap:
431 case NVPTXISD::Suld3DV2I8Trap:
432 case NVPTXISD::Suld3DV2I16Trap:
433 case NVPTXISD::Suld3DV2I32Trap:
434 case NVPTXISD::Suld3DV2I64Trap:
435 case NVPTXISD::Suld3DV4I8Trap:
436 case NVPTXISD::Suld3DV4I16Trap:
437 case NVPTXISD::Suld3DV4I32Trap:
438 case NVPTXISD::Suld1DI8Zero:
439 case NVPTXISD::Suld1DI16Zero:
440 case NVPTXISD::Suld1DI32Zero:
441 case NVPTXISD::Suld1DI64Zero:
442 case NVPTXISD::Suld1DV2I8Zero:
443 case NVPTXISD::Suld1DV2I16Zero:
444 case NVPTXISD::Suld1DV2I32Zero:
445 case NVPTXISD::Suld1DV2I64Zero:
446 case NVPTXISD::Suld1DV4I8Zero:
447 case NVPTXISD::Suld1DV4I16Zero:
448 case NVPTXISD::Suld1DV4I32Zero:
449 case NVPTXISD::Suld1DArrayI8Zero:
450 case NVPTXISD::Suld1DArrayI16Zero:
451 case NVPTXISD::Suld1DArrayI32Zero:
452 case NVPTXISD::Suld1DArrayI64Zero:
453 case NVPTXISD::Suld1DArrayV2I8Zero:
454 case NVPTXISD::Suld1DArrayV2I16Zero:
455 case NVPTXISD::Suld1DArrayV2I32Zero:
456 case NVPTXISD::Suld1DArrayV2I64Zero:
457 case NVPTXISD::Suld1DArrayV4I8Zero:
458 case NVPTXISD::Suld1DArrayV4I16Zero:
459 case NVPTXISD::Suld1DArrayV4I32Zero:
460 case NVPTXISD::Suld2DI8Zero:
461 case NVPTXISD::Suld2DI16Zero:
462 case NVPTXISD::Suld2DI32Zero:
463 case NVPTXISD::Suld2DI64Zero:
464 case NVPTXISD::Suld2DV2I8Zero:
465 case NVPTXISD::Suld2DV2I16Zero:
466 case NVPTXISD::Suld2DV2I32Zero:
467 case NVPTXISD::Suld2DV2I64Zero:
468 case NVPTXISD::Suld2DV4I8Zero:
469 case NVPTXISD::Suld2DV4I16Zero:
470 case NVPTXISD::Suld2DV4I32Zero:
471 case NVPTXISD::Suld2DArrayI8Zero:
472 case NVPTXISD::Suld2DArrayI16Zero:
473 case NVPTXISD::Suld2DArrayI32Zero:
474 case NVPTXISD::Suld2DArrayI64Zero:
475 case NVPTXISD::Suld2DArrayV2I8Zero:
476 case NVPTXISD::Suld2DArrayV2I16Zero:
477 case NVPTXISD::Suld2DArrayV2I32Zero:
478 case NVPTXISD::Suld2DArrayV2I64Zero:
479 case NVPTXISD::Suld2DArrayV4I8Zero:
480 case NVPTXISD::Suld2DArrayV4I16Zero:
481 case NVPTXISD::Suld2DArrayV4I32Zero:
482 case NVPTXISD::Suld3DI8Zero:
483 case NVPTXISD::Suld3DI16Zero:
484 case NVPTXISD::Suld3DI32Zero:
485 case NVPTXISD::Suld3DI64Zero:
486 case NVPTXISD::Suld3DV2I8Zero:
487 case NVPTXISD::Suld3DV2I16Zero:
488 case NVPTXISD::Suld3DV2I32Zero:
489 case NVPTXISD::Suld3DV2I64Zero:
490 case NVPTXISD::Suld3DV4I8Zero:
491 case NVPTXISD::Suld3DV4I16Zero:
492 case NVPTXISD::Suld3DV4I32Zero:
493 ResNode = SelectSurfaceIntrinsic(N);
499 ResNode = SelectBFE(N);
501 case ISD::ADDRSPACECAST:
502 ResNode = SelectAddrSpaceCast(N);
509 return SelectCode(N);
512 SDNode *NVPTXDAGToDAGISel::SelectIntrinsicChain(SDNode *N) {
513 unsigned IID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
517 case Intrinsic::nvvm_ldg_global_f:
518 case Intrinsic::nvvm_ldg_global_i:
519 case Intrinsic::nvvm_ldg_global_p:
520 case Intrinsic::nvvm_ldu_global_f:
521 case Intrinsic::nvvm_ldu_global_i:
522 case Intrinsic::nvvm_ldu_global_p:
523 return SelectLDGLDU(N);
527 static unsigned int getCodeAddrSpace(MemSDNode *N) {
528 const Value *Src = N->getMemOperand()->getValue();
531 return NVPTX::PTXLdStInstCode::GENERIC;
533 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) {
534 switch (PT->getAddressSpace()) {
535 case llvm::ADDRESS_SPACE_LOCAL: return NVPTX::PTXLdStInstCode::LOCAL;
536 case llvm::ADDRESS_SPACE_GLOBAL: return NVPTX::PTXLdStInstCode::GLOBAL;
537 case llvm::ADDRESS_SPACE_SHARED: return NVPTX::PTXLdStInstCode::SHARED;
538 case llvm::ADDRESS_SPACE_GENERIC: return NVPTX::PTXLdStInstCode::GENERIC;
539 case llvm::ADDRESS_SPACE_PARAM: return NVPTX::PTXLdStInstCode::PARAM;
540 case llvm::ADDRESS_SPACE_CONST: return NVPTX::PTXLdStInstCode::CONSTANT;
544 return NVPTX::PTXLdStInstCode::GENERIC;
547 SDNode *NVPTXDAGToDAGISel::SelectIntrinsicNoChain(SDNode *N) {
548 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
552 case Intrinsic::nvvm_texsurf_handle_internal:
553 return SelectTexSurfHandle(N);
557 SDNode *NVPTXDAGToDAGISel::SelectTexSurfHandle(SDNode *N) {
558 // Op 0 is the intrinsic ID
559 SDValue Wrapper = N->getOperand(1);
560 SDValue GlobalVal = Wrapper.getOperand(0);
561 return CurDAG->getMachineNode(NVPTX::texsurf_handles, SDLoc(N), MVT::i64,
565 SDNode *NVPTXDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
566 SDValue Src = N->getOperand(0);
567 AddrSpaceCastSDNode *CastN = cast<AddrSpaceCastSDNode>(N);
568 unsigned SrcAddrSpace = CastN->getSrcAddressSpace();
569 unsigned DstAddrSpace = CastN->getDestAddressSpace();
571 assert(SrcAddrSpace != DstAddrSpace &&
572 "addrspacecast must be between different address spaces");
574 if (DstAddrSpace == ADDRESS_SPACE_GENERIC) {
575 // Specific to generic
577 switch (SrcAddrSpace) {
578 default: report_fatal_error("Bad address space in addrspacecast");
579 case ADDRESS_SPACE_GLOBAL:
580 Opc = TM.is64Bit() ? NVPTX::cvta_global_yes_64 : NVPTX::cvta_global_yes;
582 case ADDRESS_SPACE_SHARED:
583 Opc = TM.is64Bit() ? NVPTX::cvta_shared_yes_64 : NVPTX::cvta_shared_yes;
585 case ADDRESS_SPACE_CONST:
586 Opc = TM.is64Bit() ? NVPTX::cvta_const_yes_64 : NVPTX::cvta_const_yes;
588 case ADDRESS_SPACE_LOCAL:
589 Opc = TM.is64Bit() ? NVPTX::cvta_local_yes_64 : NVPTX::cvta_local_yes;
592 return CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), Src);
594 // Generic to specific
595 if (SrcAddrSpace != 0)
596 report_fatal_error("Cannot cast between two non-generic address spaces");
598 switch (DstAddrSpace) {
599 default: report_fatal_error("Bad address space in addrspacecast");
600 case ADDRESS_SPACE_GLOBAL:
601 Opc = TM.is64Bit() ? NVPTX::cvta_to_global_yes_64
602 : NVPTX::cvta_to_global_yes;
604 case ADDRESS_SPACE_SHARED:
605 Opc = TM.is64Bit() ? NVPTX::cvta_to_shared_yes_64
606 : NVPTX::cvta_to_shared_yes;
608 case ADDRESS_SPACE_CONST:
610 TM.is64Bit() ? NVPTX::cvta_to_const_yes_64 : NVPTX::cvta_to_const_yes;
612 case ADDRESS_SPACE_LOCAL:
614 TM.is64Bit() ? NVPTX::cvta_to_local_yes_64 : NVPTX::cvta_to_local_yes;
616 case ADDRESS_SPACE_PARAM:
617 Opc = TM.is64Bit() ? NVPTX::nvvm_ptr_gen_to_param_64
618 : NVPTX::nvvm_ptr_gen_to_param;
621 return CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), Src);
625 SDNode *NVPTXDAGToDAGISel::SelectLoad(SDNode *N) {
627 LoadSDNode *LD = cast<LoadSDNode>(N);
628 EVT LoadedVT = LD->getMemoryVT();
629 SDNode *NVPTXLD = nullptr;
631 // do not support pre/post inc/dec
635 if (!LoadedVT.isSimple())
638 // Address Space Setting
639 unsigned int codeAddrSpace = getCodeAddrSpace(LD);
642 // - .volatile is only availalble for .global and .shared
643 bool isVolatile = LD->isVolatile();
644 if (codeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
645 codeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
646 codeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
650 MVT SimpleVT = LoadedVT.getSimpleVT();
651 unsigned vecType = NVPTX::PTXLdStInstCode::Scalar;
652 if (SimpleVT.isVector()) {
653 unsigned num = SimpleVT.getVectorNumElements();
655 vecType = NVPTX::PTXLdStInstCode::V2;
657 vecType = NVPTX::PTXLdStInstCode::V4;
662 // Type Setting: fromType + fromTypeWidth
664 // Sign : ISD::SEXTLOAD
665 // Unsign : ISD::ZEXTLOAD, ISD::NON_EXTLOAD or ISD::EXTLOAD and the
667 // Float : ISD::NON_EXTLOAD or ISD::EXTLOAD and the type is float
668 MVT ScalarVT = SimpleVT.getScalarType();
669 // Read at least 8 bits (predicates are stored as 8-bit values)
670 unsigned fromTypeWidth = std::max(8U, ScalarVT.getSizeInBits());
671 unsigned int fromType;
672 if ((LD->getExtensionType() == ISD::SEXTLOAD))
673 fromType = NVPTX::PTXLdStInstCode::Signed;
674 else if (ScalarVT.isFloatingPoint())
675 fromType = NVPTX::PTXLdStInstCode::Float;
677 fromType = NVPTX::PTXLdStInstCode::Unsigned;
679 // Create the machine instruction DAG
680 SDValue Chain = N->getOperand(0);
681 SDValue N1 = N->getOperand(1);
683 SDValue Offset, Base;
685 MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy;
687 if (SelectDirectAddr(N1, Addr)) {
690 Opcode = NVPTX::LD_i8_avar;
693 Opcode = NVPTX::LD_i16_avar;
696 Opcode = NVPTX::LD_i32_avar;
699 Opcode = NVPTX::LD_i64_avar;
702 Opcode = NVPTX::LD_f32_avar;
705 Opcode = NVPTX::LD_f64_avar;
710 SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl),
711 getI32Imm(vecType, dl), getI32Imm(fromType, dl),
712 getI32Imm(fromTypeWidth, dl), Addr, Chain };
713 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
714 } else if (TM.is64Bit() ? SelectADDRsi64(N1.getNode(), N1, Base, Offset)
715 : SelectADDRsi(N1.getNode(), N1, Base, Offset)) {
718 Opcode = NVPTX::LD_i8_asi;
721 Opcode = NVPTX::LD_i16_asi;
724 Opcode = NVPTX::LD_i32_asi;
727 Opcode = NVPTX::LD_i64_asi;
730 Opcode = NVPTX::LD_f32_asi;
733 Opcode = NVPTX::LD_f64_asi;
738 SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl),
739 getI32Imm(vecType, dl), getI32Imm(fromType, dl),
740 getI32Imm(fromTypeWidth, dl), Base, Offset, Chain };
741 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
742 } else if (TM.is64Bit() ? SelectADDRri64(N1.getNode(), N1, Base, Offset)
743 : SelectADDRri(N1.getNode(), N1, Base, Offset)) {
747 Opcode = NVPTX::LD_i8_ari_64;
750 Opcode = NVPTX::LD_i16_ari_64;
753 Opcode = NVPTX::LD_i32_ari_64;
756 Opcode = NVPTX::LD_i64_ari_64;
759 Opcode = NVPTX::LD_f32_ari_64;
762 Opcode = NVPTX::LD_f64_ari_64;
770 Opcode = NVPTX::LD_i8_ari;
773 Opcode = NVPTX::LD_i16_ari;
776 Opcode = NVPTX::LD_i32_ari;
779 Opcode = NVPTX::LD_i64_ari;
782 Opcode = NVPTX::LD_f32_ari;
785 Opcode = NVPTX::LD_f64_ari;
791 SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl),
792 getI32Imm(vecType, dl), getI32Imm(fromType, dl),
793 getI32Imm(fromTypeWidth, dl), Base, Offset, Chain };
794 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
799 Opcode = NVPTX::LD_i8_areg_64;
802 Opcode = NVPTX::LD_i16_areg_64;
805 Opcode = NVPTX::LD_i32_areg_64;
808 Opcode = NVPTX::LD_i64_areg_64;
811 Opcode = NVPTX::LD_f32_areg_64;
814 Opcode = NVPTX::LD_f64_areg_64;
822 Opcode = NVPTX::LD_i8_areg;
825 Opcode = NVPTX::LD_i16_areg;
828 Opcode = NVPTX::LD_i32_areg;
831 Opcode = NVPTX::LD_i64_areg;
834 Opcode = NVPTX::LD_f32_areg;
837 Opcode = NVPTX::LD_f64_areg;
843 SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl),
844 getI32Imm(vecType, dl), getI32Imm(fromType, dl),
845 getI32Imm(fromTypeWidth, dl), N1, Chain };
846 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
850 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
851 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
852 cast<MachineSDNode>(NVPTXLD)->setMemRefs(MemRefs0, MemRefs0 + 1);
858 SDNode *NVPTXDAGToDAGISel::SelectLoadVector(SDNode *N) {
860 SDValue Chain = N->getOperand(0);
861 SDValue Op1 = N->getOperand(1);
862 SDValue Addr, Offset, Base;
866 MemSDNode *MemSD = cast<MemSDNode>(N);
867 EVT LoadedVT = MemSD->getMemoryVT();
869 if (!LoadedVT.isSimple())
872 // Address Space Setting
873 unsigned int CodeAddrSpace = getCodeAddrSpace(MemSD);
876 // - .volatile is only availalble for .global and .shared
877 bool IsVolatile = MemSD->isVolatile();
878 if (CodeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
879 CodeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
880 CodeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
884 MVT SimpleVT = LoadedVT.getSimpleVT();
886 // Type Setting: fromType + fromTypeWidth
888 // Sign : ISD::SEXTLOAD
889 // Unsign : ISD::ZEXTLOAD, ISD::NON_EXTLOAD or ISD::EXTLOAD and the
891 // Float : ISD::NON_EXTLOAD or ISD::EXTLOAD and the type is float
892 MVT ScalarVT = SimpleVT.getScalarType();
893 // Read at least 8 bits (predicates are stored as 8-bit values)
894 unsigned FromTypeWidth = std::max(8U, ScalarVT.getSizeInBits());
895 unsigned int FromType;
896 // The last operand holds the original LoadSDNode::getExtensionType() value
897 unsigned ExtensionType = cast<ConstantSDNode>(
898 N->getOperand(N->getNumOperands() - 1))->getZExtValue();
899 if (ExtensionType == ISD::SEXTLOAD)
900 FromType = NVPTX::PTXLdStInstCode::Signed;
901 else if (ScalarVT.isFloatingPoint())
902 FromType = NVPTX::PTXLdStInstCode::Float;
904 FromType = NVPTX::PTXLdStInstCode::Unsigned;
908 switch (N->getOpcode()) {
909 case NVPTXISD::LoadV2:
910 VecType = NVPTX::PTXLdStInstCode::V2;
912 case NVPTXISD::LoadV4:
913 VecType = NVPTX::PTXLdStInstCode::V4;
919 EVT EltVT = N->getValueType(0);
921 if (SelectDirectAddr(Op1, Addr)) {
922 switch (N->getOpcode()) {
925 case NVPTXISD::LoadV2:
926 switch (EltVT.getSimpleVT().SimpleTy) {
930 Opcode = NVPTX::LDV_i8_v2_avar;
933 Opcode = NVPTX::LDV_i16_v2_avar;
936 Opcode = NVPTX::LDV_i32_v2_avar;
939 Opcode = NVPTX::LDV_i64_v2_avar;
942 Opcode = NVPTX::LDV_f32_v2_avar;
945 Opcode = NVPTX::LDV_f64_v2_avar;
949 case NVPTXISD::LoadV4:
950 switch (EltVT.getSimpleVT().SimpleTy) {
954 Opcode = NVPTX::LDV_i8_v4_avar;
957 Opcode = NVPTX::LDV_i16_v4_avar;
960 Opcode = NVPTX::LDV_i32_v4_avar;
963 Opcode = NVPTX::LDV_f32_v4_avar;
969 SDValue Ops[] = { getI32Imm(IsVolatile, DL), getI32Imm(CodeAddrSpace, DL),
970 getI32Imm(VecType, DL), getI32Imm(FromType, DL),
971 getI32Imm(FromTypeWidth, DL), Addr, Chain };
972 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
973 } else if (TM.is64Bit() ? SelectADDRsi64(Op1.getNode(), Op1, Base, Offset)
974 : SelectADDRsi(Op1.getNode(), Op1, Base, Offset)) {
975 switch (N->getOpcode()) {
978 case NVPTXISD::LoadV2:
979 switch (EltVT.getSimpleVT().SimpleTy) {
983 Opcode = NVPTX::LDV_i8_v2_asi;
986 Opcode = NVPTX::LDV_i16_v2_asi;
989 Opcode = NVPTX::LDV_i32_v2_asi;
992 Opcode = NVPTX::LDV_i64_v2_asi;
995 Opcode = NVPTX::LDV_f32_v2_asi;
998 Opcode = NVPTX::LDV_f64_v2_asi;
1002 case NVPTXISD::LoadV4:
1003 switch (EltVT.getSimpleVT().SimpleTy) {
1007 Opcode = NVPTX::LDV_i8_v4_asi;
1010 Opcode = NVPTX::LDV_i16_v4_asi;
1013 Opcode = NVPTX::LDV_i32_v4_asi;
1016 Opcode = NVPTX::LDV_f32_v4_asi;
1022 SDValue Ops[] = { getI32Imm(IsVolatile, DL), getI32Imm(CodeAddrSpace, DL),
1023 getI32Imm(VecType, DL), getI32Imm(FromType, DL),
1024 getI32Imm(FromTypeWidth, DL), Base, Offset, Chain };
1025 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1026 } else if (TM.is64Bit() ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
1027 : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
1029 switch (N->getOpcode()) {
1032 case NVPTXISD::LoadV2:
1033 switch (EltVT.getSimpleVT().SimpleTy) {
1037 Opcode = NVPTX::LDV_i8_v2_ari_64;
1040 Opcode = NVPTX::LDV_i16_v2_ari_64;
1043 Opcode = NVPTX::LDV_i32_v2_ari_64;
1046 Opcode = NVPTX::LDV_i64_v2_ari_64;
1049 Opcode = NVPTX::LDV_f32_v2_ari_64;
1052 Opcode = NVPTX::LDV_f64_v2_ari_64;
1056 case NVPTXISD::LoadV4:
1057 switch (EltVT.getSimpleVT().SimpleTy) {
1061 Opcode = NVPTX::LDV_i8_v4_ari_64;
1064 Opcode = NVPTX::LDV_i16_v4_ari_64;
1067 Opcode = NVPTX::LDV_i32_v4_ari_64;
1070 Opcode = NVPTX::LDV_f32_v4_ari_64;
1076 switch (N->getOpcode()) {
1079 case NVPTXISD::LoadV2:
1080 switch (EltVT.getSimpleVT().SimpleTy) {
1084 Opcode = NVPTX::LDV_i8_v2_ari;
1087 Opcode = NVPTX::LDV_i16_v2_ari;
1090 Opcode = NVPTX::LDV_i32_v2_ari;
1093 Opcode = NVPTX::LDV_i64_v2_ari;
1096 Opcode = NVPTX::LDV_f32_v2_ari;
1099 Opcode = NVPTX::LDV_f64_v2_ari;
1103 case NVPTXISD::LoadV4:
1104 switch (EltVT.getSimpleVT().SimpleTy) {
1108 Opcode = NVPTX::LDV_i8_v4_ari;
1111 Opcode = NVPTX::LDV_i16_v4_ari;
1114 Opcode = NVPTX::LDV_i32_v4_ari;
1117 Opcode = NVPTX::LDV_f32_v4_ari;
1124 SDValue Ops[] = { getI32Imm(IsVolatile, DL), getI32Imm(CodeAddrSpace, DL),
1125 getI32Imm(VecType, DL), getI32Imm(FromType, DL),
1126 getI32Imm(FromTypeWidth, DL), Base, Offset, Chain };
1128 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1131 switch (N->getOpcode()) {
1134 case NVPTXISD::LoadV2:
1135 switch (EltVT.getSimpleVT().SimpleTy) {
1139 Opcode = NVPTX::LDV_i8_v2_areg_64;
1142 Opcode = NVPTX::LDV_i16_v2_areg_64;
1145 Opcode = NVPTX::LDV_i32_v2_areg_64;
1148 Opcode = NVPTX::LDV_i64_v2_areg_64;
1151 Opcode = NVPTX::LDV_f32_v2_areg_64;
1154 Opcode = NVPTX::LDV_f64_v2_areg_64;
1158 case NVPTXISD::LoadV4:
1159 switch (EltVT.getSimpleVT().SimpleTy) {
1163 Opcode = NVPTX::LDV_i8_v4_areg_64;
1166 Opcode = NVPTX::LDV_i16_v4_areg_64;
1169 Opcode = NVPTX::LDV_i32_v4_areg_64;
1172 Opcode = NVPTX::LDV_f32_v4_areg_64;
1178 switch (N->getOpcode()) {
1181 case NVPTXISD::LoadV2:
1182 switch (EltVT.getSimpleVT().SimpleTy) {
1186 Opcode = NVPTX::LDV_i8_v2_areg;
1189 Opcode = NVPTX::LDV_i16_v2_areg;
1192 Opcode = NVPTX::LDV_i32_v2_areg;
1195 Opcode = NVPTX::LDV_i64_v2_areg;
1198 Opcode = NVPTX::LDV_f32_v2_areg;
1201 Opcode = NVPTX::LDV_f64_v2_areg;
1205 case NVPTXISD::LoadV4:
1206 switch (EltVT.getSimpleVT().SimpleTy) {
1210 Opcode = NVPTX::LDV_i8_v4_areg;
1213 Opcode = NVPTX::LDV_i16_v4_areg;
1216 Opcode = NVPTX::LDV_i32_v4_areg;
1219 Opcode = NVPTX::LDV_f32_v4_areg;
1226 SDValue Ops[] = { getI32Imm(IsVolatile, DL), getI32Imm(CodeAddrSpace, DL),
1227 getI32Imm(VecType, DL), getI32Imm(FromType, DL),
1228 getI32Imm(FromTypeWidth, DL), Op1, Chain };
1229 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1232 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
1233 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
1234 cast<MachineSDNode>(LD)->setMemRefs(MemRefs0, MemRefs0 + 1);
1239 SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(SDNode *N) {
1241 SDValue Chain = N->getOperand(0);
1246 // If this is an LDG intrinsic, the address is the third operand. Its its an
1247 // LDG/LDU SD node (from custom vector handling), then its the second operand
1248 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
1249 Op1 = N->getOperand(2);
1250 Mem = cast<MemIntrinsicSDNode>(N);
1251 unsigned IID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
1255 case Intrinsic::nvvm_ldg_global_f:
1256 case Intrinsic::nvvm_ldg_global_i:
1257 case Intrinsic::nvvm_ldg_global_p:
1260 case Intrinsic::nvvm_ldu_global_f:
1261 case Intrinsic::nvvm_ldu_global_i:
1262 case Intrinsic::nvvm_ldu_global_p:
1267 Op1 = N->getOperand(1);
1268 Mem = cast<MemSDNode>(N);
1274 SDValue Base, Offset, Addr;
1276 EVT EltVT = Mem->getMemoryVT();
1277 if (EltVT.isVector()) {
1278 EltVT = EltVT.getVectorElementType();
1281 if (SelectDirectAddr(Op1, Addr)) {
1282 switch (N->getOpcode()) {
1285 case ISD::INTRINSIC_W_CHAIN:
1287 switch (EltVT.getSimpleVT().SimpleTy) {
1291 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8avar;
1294 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16avar;
1297 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32avar;
1300 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64avar;
1303 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32avar;
1306 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64avar;
1310 switch (EltVT.getSimpleVT().SimpleTy) {
1314 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8avar;
1317 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16avar;
1320 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32avar;
1323 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64avar;
1326 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32avar;
1329 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64avar;
1334 case NVPTXISD::LDGV2:
1335 switch (EltVT.getSimpleVT().SimpleTy) {
1339 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_avar;
1342 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_avar;
1345 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_avar;
1348 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_avar;
1351 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_avar;
1354 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_avar;
1358 case NVPTXISD::LDUV2:
1359 switch (EltVT.getSimpleVT().SimpleTy) {
1363 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_avar;
1366 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_avar;
1369 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_avar;
1372 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_avar;
1375 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_avar;
1378 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_avar;
1382 case NVPTXISD::LDGV4:
1383 switch (EltVT.getSimpleVT().SimpleTy) {
1387 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_avar;
1390 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_avar;
1393 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_avar;
1396 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_avar;
1400 case NVPTXISD::LDUV4:
1401 switch (EltVT.getSimpleVT().SimpleTy) {
1405 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_avar;
1408 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_avar;
1411 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_avar;
1414 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_avar;
1420 SDValue Ops[] = { Addr, Chain };
1421 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1422 } else if (TM.is64Bit() ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
1423 : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
1425 switch (N->getOpcode()) {
1428 case ISD::INTRINSIC_W_CHAIN:
1430 switch (EltVT.getSimpleVT().SimpleTy) {
1434 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8ari64;
1437 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16ari64;
1440 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32ari64;
1443 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64ari64;
1446 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32ari64;
1449 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64ari64;
1453 switch (EltVT.getSimpleVT().SimpleTy) {
1457 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8ari64;
1460 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16ari64;
1463 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32ari64;
1466 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64ari64;
1469 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32ari64;
1472 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64ari64;
1477 case NVPTXISD::LDGV2:
1478 switch (EltVT.getSimpleVT().SimpleTy) {
1482 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_ari64;
1485 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_ari64;
1488 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_ari64;
1491 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_ari64;
1494 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_ari64;
1497 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_ari64;
1501 case NVPTXISD::LDUV2:
1502 switch (EltVT.getSimpleVT().SimpleTy) {
1506 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_ari64;
1509 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_ari64;
1512 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_ari64;
1515 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_ari64;
1518 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_ari64;
1521 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_ari64;
1525 case NVPTXISD::LDGV4:
1526 switch (EltVT.getSimpleVT().SimpleTy) {
1530 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari64;
1533 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_ari64;
1536 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_ari64;
1539 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_ari64;
1543 case NVPTXISD::LDUV4:
1544 switch (EltVT.getSimpleVT().SimpleTy) {
1548 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari64;
1551 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_ari64;
1554 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_ari64;
1557 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_ari64;
1563 switch (N->getOpcode()) {
1566 case ISD::INTRINSIC_W_CHAIN:
1568 switch (EltVT.getSimpleVT().SimpleTy) {
1572 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8ari;
1575 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16ari;
1578 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32ari;
1581 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64ari;
1584 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32ari;
1587 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64ari;
1591 switch (EltVT.getSimpleVT().SimpleTy) {
1595 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8ari;
1598 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16ari;
1601 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32ari;
1604 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64ari;
1607 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32ari;
1610 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64ari;
1615 case NVPTXISD::LDGV2:
1616 switch (EltVT.getSimpleVT().SimpleTy) {
1620 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_ari32;
1623 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_ari32;
1626 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_ari32;
1629 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_ari32;
1632 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_ari32;
1635 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_ari32;
1639 case NVPTXISD::LDUV2:
1640 switch (EltVT.getSimpleVT().SimpleTy) {
1644 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_ari32;
1647 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_ari32;
1650 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_ari32;
1653 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_ari32;
1656 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_ari32;
1659 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_ari32;
1663 case NVPTXISD::LDGV4:
1664 switch (EltVT.getSimpleVT().SimpleTy) {
1668 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari32;
1671 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_ari32;
1674 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_ari32;
1677 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_ari32;
1681 case NVPTXISD::LDUV4:
1682 switch (EltVT.getSimpleVT().SimpleTy) {
1686 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari32;
1689 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_ari32;
1692 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_ari32;
1695 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_ari32;
1702 SDValue Ops[] = { Base, Offset, Chain };
1704 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1707 switch (N->getOpcode()) {
1710 case ISD::INTRINSIC_W_CHAIN:
1712 switch (EltVT.getSimpleVT().SimpleTy) {
1716 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8areg64;
1719 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16areg64;
1722 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32areg64;
1725 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64areg64;
1728 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32areg64;
1731 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64areg64;
1735 switch (EltVT.getSimpleVT().SimpleTy) {
1739 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8areg64;
1742 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16areg64;
1745 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32areg64;
1748 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64areg64;
1751 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32areg64;
1754 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64areg64;
1759 case NVPTXISD::LDGV2:
1760 switch (EltVT.getSimpleVT().SimpleTy) {
1764 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_areg64;
1767 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_areg64;
1770 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_areg64;
1773 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_areg64;
1776 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_areg64;
1779 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_areg64;
1783 case NVPTXISD::LDUV2:
1784 switch (EltVT.getSimpleVT().SimpleTy) {
1788 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_areg64;
1791 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_areg64;
1794 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_areg64;
1797 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_areg64;
1800 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_areg64;
1803 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_areg64;
1807 case NVPTXISD::LDGV4:
1808 switch (EltVT.getSimpleVT().SimpleTy) {
1812 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg64;
1815 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg64;
1818 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg64;
1821 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg64;
1825 case NVPTXISD::LDUV4:
1826 switch (EltVT.getSimpleVT().SimpleTy) {
1830 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg64;
1833 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg64;
1836 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg64;
1839 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg64;
1845 switch (N->getOpcode()) {
1848 case ISD::INTRINSIC_W_CHAIN:
1850 switch (EltVT.getSimpleVT().SimpleTy) {
1854 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8areg;
1857 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16areg;
1860 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32areg;
1863 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64areg;
1866 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32areg;
1869 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64areg;
1873 switch (EltVT.getSimpleVT().SimpleTy) {
1877 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8areg;
1880 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16areg;
1883 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32areg;
1886 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64areg;
1889 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32areg;
1892 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64areg;
1897 case NVPTXISD::LDGV2:
1898 switch (EltVT.getSimpleVT().SimpleTy) {
1902 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_areg32;
1905 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_areg32;
1908 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_areg32;
1911 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_areg32;
1914 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_areg32;
1917 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_areg32;
1921 case NVPTXISD::LDUV2:
1922 switch (EltVT.getSimpleVT().SimpleTy) {
1926 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_areg32;
1929 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_areg32;
1932 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_areg32;
1935 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_areg32;
1938 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_areg32;
1941 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_areg32;
1945 case NVPTXISD::LDGV4:
1946 switch (EltVT.getSimpleVT().SimpleTy) {
1950 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg32;
1953 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg32;
1956 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg32;
1959 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg32;
1963 case NVPTXISD::LDUV4:
1964 switch (EltVT.getSimpleVT().SimpleTy) {
1968 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg32;
1971 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg32;
1974 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg32;
1977 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg32;
1984 SDValue Ops[] = { Op1, Chain };
1985 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1988 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
1989 MemRefs0[0] = Mem->getMemOperand();
1990 cast<MachineSDNode>(LD)->setMemRefs(MemRefs0, MemRefs0 + 1);
1995 SDNode *NVPTXDAGToDAGISel::SelectStore(SDNode *N) {
1997 StoreSDNode *ST = cast<StoreSDNode>(N);
1998 EVT StoreVT = ST->getMemoryVT();
1999 SDNode *NVPTXST = nullptr;
2001 // do not support pre/post inc/dec
2002 if (ST->isIndexed())
2005 if (!StoreVT.isSimple())
2008 // Address Space Setting
2009 unsigned int codeAddrSpace = getCodeAddrSpace(ST);
2012 // - .volatile is only availalble for .global and .shared
2013 bool isVolatile = ST->isVolatile();
2014 if (codeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
2015 codeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
2016 codeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
2020 MVT SimpleVT = StoreVT.getSimpleVT();
2021 unsigned vecType = NVPTX::PTXLdStInstCode::Scalar;
2022 if (SimpleVT.isVector()) {
2023 unsigned num = SimpleVT.getVectorNumElements();
2025 vecType = NVPTX::PTXLdStInstCode::V2;
2027 vecType = NVPTX::PTXLdStInstCode::V4;
2032 // Type Setting: toType + toTypeWidth
2033 // - for integer type, always use 'u'
2035 MVT ScalarVT = SimpleVT.getScalarType();
2036 unsigned toTypeWidth = ScalarVT.getSizeInBits();
2037 unsigned int toType;
2038 if (ScalarVT.isFloatingPoint())
2039 toType = NVPTX::PTXLdStInstCode::Float;
2041 toType = NVPTX::PTXLdStInstCode::Unsigned;
2043 // Create the machine instruction DAG
2044 SDValue Chain = N->getOperand(0);
2045 SDValue N1 = N->getOperand(1);
2046 SDValue N2 = N->getOperand(2);
2048 SDValue Offset, Base;
2050 MVT::SimpleValueType SourceVT = N1.getNode()->getSimpleValueType(0).SimpleTy;
2052 if (SelectDirectAddr(N2, Addr)) {
2055 Opcode = NVPTX::ST_i8_avar;
2058 Opcode = NVPTX::ST_i16_avar;
2061 Opcode = NVPTX::ST_i32_avar;
2064 Opcode = NVPTX::ST_i64_avar;
2067 Opcode = NVPTX::ST_f32_avar;
2070 Opcode = NVPTX::ST_f64_avar;
2075 SDValue Ops[] = { N1, getI32Imm(isVolatile, dl),
2076 getI32Imm(codeAddrSpace, dl), getI32Imm(vecType, dl),
2077 getI32Imm(toType, dl), getI32Imm(toTypeWidth, dl), Addr,
2079 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
2080 } else if (TM.is64Bit() ? SelectADDRsi64(N2.getNode(), N2, Base, Offset)
2081 : SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
2084 Opcode = NVPTX::ST_i8_asi;
2087 Opcode = NVPTX::ST_i16_asi;
2090 Opcode = NVPTX::ST_i32_asi;
2093 Opcode = NVPTX::ST_i64_asi;
2096 Opcode = NVPTX::ST_f32_asi;
2099 Opcode = NVPTX::ST_f64_asi;
2104 SDValue Ops[] = { N1, getI32Imm(isVolatile, dl),
2105 getI32Imm(codeAddrSpace, dl), getI32Imm(vecType, dl),
2106 getI32Imm(toType, dl), getI32Imm(toTypeWidth, dl), Base,
2108 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
2109 } else if (TM.is64Bit() ? SelectADDRri64(N2.getNode(), N2, Base, Offset)
2110 : SelectADDRri(N2.getNode(), N2, Base, Offset)) {
2114 Opcode = NVPTX::ST_i8_ari_64;
2117 Opcode = NVPTX::ST_i16_ari_64;
2120 Opcode = NVPTX::ST_i32_ari_64;
2123 Opcode = NVPTX::ST_i64_ari_64;
2126 Opcode = NVPTX::ST_f32_ari_64;
2129 Opcode = NVPTX::ST_f64_ari_64;
2137 Opcode = NVPTX::ST_i8_ari;
2140 Opcode = NVPTX::ST_i16_ari;
2143 Opcode = NVPTX::ST_i32_ari;
2146 Opcode = NVPTX::ST_i64_ari;
2149 Opcode = NVPTX::ST_f32_ari;
2152 Opcode = NVPTX::ST_f64_ari;
2158 SDValue Ops[] = { N1, getI32Imm(isVolatile, dl),
2159 getI32Imm(codeAddrSpace, dl), getI32Imm(vecType, dl),
2160 getI32Imm(toType, dl), getI32Imm(toTypeWidth, dl), Base,
2162 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
2167 Opcode = NVPTX::ST_i8_areg_64;
2170 Opcode = NVPTX::ST_i16_areg_64;
2173 Opcode = NVPTX::ST_i32_areg_64;
2176 Opcode = NVPTX::ST_i64_areg_64;
2179 Opcode = NVPTX::ST_f32_areg_64;
2182 Opcode = NVPTX::ST_f64_areg_64;
2190 Opcode = NVPTX::ST_i8_areg;
2193 Opcode = NVPTX::ST_i16_areg;
2196 Opcode = NVPTX::ST_i32_areg;
2199 Opcode = NVPTX::ST_i64_areg;
2202 Opcode = NVPTX::ST_f32_areg;
2205 Opcode = NVPTX::ST_f64_areg;
2211 SDValue Ops[] = { N1, getI32Imm(isVolatile, dl),
2212 getI32Imm(codeAddrSpace, dl), getI32Imm(vecType, dl),
2213 getI32Imm(toType, dl), getI32Imm(toTypeWidth, dl), N2,
2215 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
2219 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2220 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2221 cast<MachineSDNode>(NVPTXST)->setMemRefs(MemRefs0, MemRefs0 + 1);
2227 SDNode *NVPTXDAGToDAGISel::SelectStoreVector(SDNode *N) {
2228 SDValue Chain = N->getOperand(0);
2229 SDValue Op1 = N->getOperand(1);
2230 SDValue Addr, Offset, Base;
2234 EVT EltVT = Op1.getValueType();
2235 MemSDNode *MemSD = cast<MemSDNode>(N);
2236 EVT StoreVT = MemSD->getMemoryVT();
2238 // Address Space Setting
2239 unsigned CodeAddrSpace = getCodeAddrSpace(MemSD);
2241 if (CodeAddrSpace == NVPTX::PTXLdStInstCode::CONSTANT) {
2242 report_fatal_error("Cannot store to pointer that points to constant "
2247 // - .volatile is only availalble for .global and .shared
2248 bool IsVolatile = MemSD->isVolatile();
2249 if (CodeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
2250 CodeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
2251 CodeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
2254 // Type Setting: toType + toTypeWidth
2255 // - for integer type, always use 'u'
2256 assert(StoreVT.isSimple() && "Store value is not simple");
2257 MVT ScalarVT = StoreVT.getSimpleVT().getScalarType();
2258 unsigned ToTypeWidth = ScalarVT.getSizeInBits();
2260 if (ScalarVT.isFloatingPoint())
2261 ToType = NVPTX::PTXLdStInstCode::Float;
2263 ToType = NVPTX::PTXLdStInstCode::Unsigned;
2265 SmallVector<SDValue, 12> StOps;
2269 switch (N->getOpcode()) {
2270 case NVPTXISD::StoreV2:
2271 VecType = NVPTX::PTXLdStInstCode::V2;
2272 StOps.push_back(N->getOperand(1));
2273 StOps.push_back(N->getOperand(2));
2274 N2 = N->getOperand(3);
2276 case NVPTXISD::StoreV4:
2277 VecType = NVPTX::PTXLdStInstCode::V4;
2278 StOps.push_back(N->getOperand(1));
2279 StOps.push_back(N->getOperand(2));
2280 StOps.push_back(N->getOperand(3));
2281 StOps.push_back(N->getOperand(4));
2282 N2 = N->getOperand(5);
2288 StOps.push_back(getI32Imm(IsVolatile, DL));
2289 StOps.push_back(getI32Imm(CodeAddrSpace, DL));
2290 StOps.push_back(getI32Imm(VecType, DL));
2291 StOps.push_back(getI32Imm(ToType, DL));
2292 StOps.push_back(getI32Imm(ToTypeWidth, DL));
2294 if (SelectDirectAddr(N2, Addr)) {
2295 switch (N->getOpcode()) {
2298 case NVPTXISD::StoreV2:
2299 switch (EltVT.getSimpleVT().SimpleTy) {
2303 Opcode = NVPTX::STV_i8_v2_avar;
2306 Opcode = NVPTX::STV_i16_v2_avar;
2309 Opcode = NVPTX::STV_i32_v2_avar;
2312 Opcode = NVPTX::STV_i64_v2_avar;
2315 Opcode = NVPTX::STV_f32_v2_avar;
2318 Opcode = NVPTX::STV_f64_v2_avar;
2322 case NVPTXISD::StoreV4:
2323 switch (EltVT.getSimpleVT().SimpleTy) {
2327 Opcode = NVPTX::STV_i8_v4_avar;
2330 Opcode = NVPTX::STV_i16_v4_avar;
2333 Opcode = NVPTX::STV_i32_v4_avar;
2336 Opcode = NVPTX::STV_f32_v4_avar;
2341 StOps.push_back(Addr);
2342 } else if (TM.is64Bit() ? SelectADDRsi64(N2.getNode(), N2, Base, Offset)
2343 : SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
2344 switch (N->getOpcode()) {
2347 case NVPTXISD::StoreV2:
2348 switch (EltVT.getSimpleVT().SimpleTy) {
2352 Opcode = NVPTX::STV_i8_v2_asi;
2355 Opcode = NVPTX::STV_i16_v2_asi;
2358 Opcode = NVPTX::STV_i32_v2_asi;
2361 Opcode = NVPTX::STV_i64_v2_asi;
2364 Opcode = NVPTX::STV_f32_v2_asi;
2367 Opcode = NVPTX::STV_f64_v2_asi;
2371 case NVPTXISD::StoreV4:
2372 switch (EltVT.getSimpleVT().SimpleTy) {
2376 Opcode = NVPTX::STV_i8_v4_asi;
2379 Opcode = NVPTX::STV_i16_v4_asi;
2382 Opcode = NVPTX::STV_i32_v4_asi;
2385 Opcode = NVPTX::STV_f32_v4_asi;
2390 StOps.push_back(Base);
2391 StOps.push_back(Offset);
2392 } else if (TM.is64Bit() ? SelectADDRri64(N2.getNode(), N2, Base, Offset)
2393 : SelectADDRri(N2.getNode(), N2, Base, Offset)) {
2395 switch (N->getOpcode()) {
2398 case NVPTXISD::StoreV2:
2399 switch (EltVT.getSimpleVT().SimpleTy) {
2403 Opcode = NVPTX::STV_i8_v2_ari_64;
2406 Opcode = NVPTX::STV_i16_v2_ari_64;
2409 Opcode = NVPTX::STV_i32_v2_ari_64;
2412 Opcode = NVPTX::STV_i64_v2_ari_64;
2415 Opcode = NVPTX::STV_f32_v2_ari_64;
2418 Opcode = NVPTX::STV_f64_v2_ari_64;
2422 case NVPTXISD::StoreV4:
2423 switch (EltVT.getSimpleVT().SimpleTy) {
2427 Opcode = NVPTX::STV_i8_v4_ari_64;
2430 Opcode = NVPTX::STV_i16_v4_ari_64;
2433 Opcode = NVPTX::STV_i32_v4_ari_64;
2436 Opcode = NVPTX::STV_f32_v4_ari_64;
2442 switch (N->getOpcode()) {
2445 case NVPTXISD::StoreV2:
2446 switch (EltVT.getSimpleVT().SimpleTy) {
2450 Opcode = NVPTX::STV_i8_v2_ari;
2453 Opcode = NVPTX::STV_i16_v2_ari;
2456 Opcode = NVPTX::STV_i32_v2_ari;
2459 Opcode = NVPTX::STV_i64_v2_ari;
2462 Opcode = NVPTX::STV_f32_v2_ari;
2465 Opcode = NVPTX::STV_f64_v2_ari;
2469 case NVPTXISD::StoreV4:
2470 switch (EltVT.getSimpleVT().SimpleTy) {
2474 Opcode = NVPTX::STV_i8_v4_ari;
2477 Opcode = NVPTX::STV_i16_v4_ari;
2480 Opcode = NVPTX::STV_i32_v4_ari;
2483 Opcode = NVPTX::STV_f32_v4_ari;
2489 StOps.push_back(Base);
2490 StOps.push_back(Offset);
2493 switch (N->getOpcode()) {
2496 case NVPTXISD::StoreV2:
2497 switch (EltVT.getSimpleVT().SimpleTy) {
2501 Opcode = NVPTX::STV_i8_v2_areg_64;
2504 Opcode = NVPTX::STV_i16_v2_areg_64;
2507 Opcode = NVPTX::STV_i32_v2_areg_64;
2510 Opcode = NVPTX::STV_i64_v2_areg_64;
2513 Opcode = NVPTX::STV_f32_v2_areg_64;
2516 Opcode = NVPTX::STV_f64_v2_areg_64;
2520 case NVPTXISD::StoreV4:
2521 switch (EltVT.getSimpleVT().SimpleTy) {
2525 Opcode = NVPTX::STV_i8_v4_areg_64;
2528 Opcode = NVPTX::STV_i16_v4_areg_64;
2531 Opcode = NVPTX::STV_i32_v4_areg_64;
2534 Opcode = NVPTX::STV_f32_v4_areg_64;
2540 switch (N->getOpcode()) {
2543 case NVPTXISD::StoreV2:
2544 switch (EltVT.getSimpleVT().SimpleTy) {
2548 Opcode = NVPTX::STV_i8_v2_areg;
2551 Opcode = NVPTX::STV_i16_v2_areg;
2554 Opcode = NVPTX::STV_i32_v2_areg;
2557 Opcode = NVPTX::STV_i64_v2_areg;
2560 Opcode = NVPTX::STV_f32_v2_areg;
2563 Opcode = NVPTX::STV_f64_v2_areg;
2567 case NVPTXISD::StoreV4:
2568 switch (EltVT.getSimpleVT().SimpleTy) {
2572 Opcode = NVPTX::STV_i8_v4_areg;
2575 Opcode = NVPTX::STV_i16_v4_areg;
2578 Opcode = NVPTX::STV_i32_v4_areg;
2581 Opcode = NVPTX::STV_f32_v4_areg;
2587 StOps.push_back(N2);
2590 StOps.push_back(Chain);
2592 ST = CurDAG->getMachineNode(Opcode, DL, MVT::Other, StOps);
2594 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2595 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2596 cast<MachineSDNode>(ST)->setMemRefs(MemRefs0, MemRefs0 + 1);
2601 SDNode *NVPTXDAGToDAGISel::SelectLoadParam(SDNode *Node) {
2602 SDValue Chain = Node->getOperand(0);
2603 SDValue Offset = Node->getOperand(2);
2604 SDValue Flag = Node->getOperand(3);
2606 MemSDNode *Mem = cast<MemSDNode>(Node);
2609 switch (Node->getOpcode()) {
2612 case NVPTXISD::LoadParam:
2615 case NVPTXISD::LoadParamV2:
2618 case NVPTXISD::LoadParamV4:
2623 EVT EltVT = Node->getValueType(0);
2624 EVT MemVT = Mem->getMemoryVT();
2632 switch (MemVT.getSimpleVT().SimpleTy) {
2636 Opc = NVPTX::LoadParamMemI8;
2639 Opc = NVPTX::LoadParamMemI8;
2642 Opc = NVPTX::LoadParamMemI16;
2645 Opc = NVPTX::LoadParamMemI32;
2648 Opc = NVPTX::LoadParamMemI64;
2651 Opc = NVPTX::LoadParamMemF32;
2654 Opc = NVPTX::LoadParamMemF64;
2659 switch (MemVT.getSimpleVT().SimpleTy) {
2663 Opc = NVPTX::LoadParamMemV2I8;
2666 Opc = NVPTX::LoadParamMemV2I8;
2669 Opc = NVPTX::LoadParamMemV2I16;
2672 Opc = NVPTX::LoadParamMemV2I32;
2675 Opc = NVPTX::LoadParamMemV2I64;
2678 Opc = NVPTX::LoadParamMemV2F32;
2681 Opc = NVPTX::LoadParamMemV2F64;
2686 switch (MemVT.getSimpleVT().SimpleTy) {
2690 Opc = NVPTX::LoadParamMemV4I8;
2693 Opc = NVPTX::LoadParamMemV4I8;
2696 Opc = NVPTX::LoadParamMemV4I16;
2699 Opc = NVPTX::LoadParamMemV4I32;
2702 Opc = NVPTX::LoadParamMemV4F32;
2710 VTs = CurDAG->getVTList(EltVT, MVT::Other, MVT::Glue);
2711 } else if (VecSize == 2) {
2712 VTs = CurDAG->getVTList(EltVT, EltVT, MVT::Other, MVT::Glue);
2714 EVT EVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other, MVT::Glue };
2715 VTs = CurDAG->getVTList(EVTs);
2718 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2720 SmallVector<SDValue, 2> Ops;
2721 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, DL, MVT::i32));
2722 Ops.push_back(Chain);
2723 Ops.push_back(Flag);
2725 return CurDAG->getMachineNode(Opc, DL, VTs, Ops);
2728 SDNode *NVPTXDAGToDAGISel::SelectStoreRetval(SDNode *N) {
2730 SDValue Chain = N->getOperand(0);
2731 SDValue Offset = N->getOperand(1);
2732 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2733 MemSDNode *Mem = cast<MemSDNode>(N);
2735 // How many elements do we have?
2736 unsigned NumElts = 1;
2737 switch (N->getOpcode()) {
2740 case NVPTXISD::StoreRetval:
2743 case NVPTXISD::StoreRetvalV2:
2746 case NVPTXISD::StoreRetvalV4:
2751 // Build vector of operands
2752 SmallVector<SDValue, 6> Ops;
2753 for (unsigned i = 0; i < NumElts; ++i)
2754 Ops.push_back(N->getOperand(i + 2));
2755 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, DL, MVT::i32));
2756 Ops.push_back(Chain);
2758 // Determine target opcode
2759 // If we have an i1, use an 8-bit store. The lowering code in
2760 // NVPTXISelLowering will have already emitted an upcast.
2761 unsigned Opcode = 0;
2766 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2770 Opcode = NVPTX::StoreRetvalI8;
2773 Opcode = NVPTX::StoreRetvalI8;
2776 Opcode = NVPTX::StoreRetvalI16;
2779 Opcode = NVPTX::StoreRetvalI32;
2782 Opcode = NVPTX::StoreRetvalI64;
2785 Opcode = NVPTX::StoreRetvalF32;
2788 Opcode = NVPTX::StoreRetvalF64;
2793 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2797 Opcode = NVPTX::StoreRetvalV2I8;
2800 Opcode = NVPTX::StoreRetvalV2I8;
2803 Opcode = NVPTX::StoreRetvalV2I16;
2806 Opcode = NVPTX::StoreRetvalV2I32;
2809 Opcode = NVPTX::StoreRetvalV2I64;
2812 Opcode = NVPTX::StoreRetvalV2F32;
2815 Opcode = NVPTX::StoreRetvalV2F64;
2820 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2824 Opcode = NVPTX::StoreRetvalV4I8;
2827 Opcode = NVPTX::StoreRetvalV4I8;
2830 Opcode = NVPTX::StoreRetvalV4I16;
2833 Opcode = NVPTX::StoreRetvalV4I32;
2836 Opcode = NVPTX::StoreRetvalV4F32;
2843 CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops);
2844 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2845 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2846 cast<MachineSDNode>(Ret)->setMemRefs(MemRefs0, MemRefs0 + 1);
2851 SDNode *NVPTXDAGToDAGISel::SelectStoreParam(SDNode *N) {
2853 SDValue Chain = N->getOperand(0);
2854 SDValue Param = N->getOperand(1);
2855 unsigned ParamVal = cast<ConstantSDNode>(Param)->getZExtValue();
2856 SDValue Offset = N->getOperand(2);
2857 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2858 MemSDNode *Mem = cast<MemSDNode>(N);
2859 SDValue Flag = N->getOperand(N->getNumOperands() - 1);
2861 // How many elements do we have?
2862 unsigned NumElts = 1;
2863 switch (N->getOpcode()) {
2866 case NVPTXISD::StoreParamU32:
2867 case NVPTXISD::StoreParamS32:
2868 case NVPTXISD::StoreParam:
2871 case NVPTXISD::StoreParamV2:
2874 case NVPTXISD::StoreParamV4:
2879 // Build vector of operands
2880 SmallVector<SDValue, 8> Ops;
2881 for (unsigned i = 0; i < NumElts; ++i)
2882 Ops.push_back(N->getOperand(i + 3));
2883 Ops.push_back(CurDAG->getTargetConstant(ParamVal, DL, MVT::i32));
2884 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, DL, MVT::i32));
2885 Ops.push_back(Chain);
2886 Ops.push_back(Flag);
2888 // Determine target opcode
2889 // If we have an i1, use an 8-bit store. The lowering code in
2890 // NVPTXISelLowering will have already emitted an upcast.
2891 unsigned Opcode = 0;
2892 switch (N->getOpcode()) {
2898 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2902 Opcode = NVPTX::StoreParamI8;
2905 Opcode = NVPTX::StoreParamI8;
2908 Opcode = NVPTX::StoreParamI16;
2911 Opcode = NVPTX::StoreParamI32;
2914 Opcode = NVPTX::StoreParamI64;
2917 Opcode = NVPTX::StoreParamF32;
2920 Opcode = NVPTX::StoreParamF64;
2925 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2929 Opcode = NVPTX::StoreParamV2I8;
2932 Opcode = NVPTX::StoreParamV2I8;
2935 Opcode = NVPTX::StoreParamV2I16;
2938 Opcode = NVPTX::StoreParamV2I32;
2941 Opcode = NVPTX::StoreParamV2I64;
2944 Opcode = NVPTX::StoreParamV2F32;
2947 Opcode = NVPTX::StoreParamV2F64;
2952 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2956 Opcode = NVPTX::StoreParamV4I8;
2959 Opcode = NVPTX::StoreParamV4I8;
2962 Opcode = NVPTX::StoreParamV4I16;
2965 Opcode = NVPTX::StoreParamV4I32;
2968 Opcode = NVPTX::StoreParamV4F32;
2974 // Special case: if we have a sign-extend/zero-extend node, insert the
2975 // conversion instruction first, and use that as the value operand to
2976 // the selected StoreParam node.
2977 case NVPTXISD::StoreParamU32: {
2978 Opcode = NVPTX::StoreParamI32;
2979 SDValue CvtNone = CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE, DL,
2981 SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_u32_u16, DL,
2982 MVT::i32, Ops[0], CvtNone);
2983 Ops[0] = SDValue(Cvt, 0);
2986 case NVPTXISD::StoreParamS32: {
2987 Opcode = NVPTX::StoreParamI32;
2988 SDValue CvtNone = CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE, DL,
2990 SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_s32_s16, DL,
2991 MVT::i32, Ops[0], CvtNone);
2992 Ops[0] = SDValue(Cvt, 0);
2997 SDVTList RetVTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
2999 CurDAG->getMachineNode(Opcode, DL, RetVTs, Ops);
3000 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
3001 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
3002 cast<MachineSDNode>(Ret)->setMemRefs(MemRefs0, MemRefs0 + 1);
3007 SDNode *NVPTXDAGToDAGISel::SelectTextureIntrinsic(SDNode *N) {
3008 SDValue Chain = N->getOperand(0);
3009 SDNode *Ret = nullptr;
3011 SmallVector<SDValue, 8> Ops;
3013 switch (N->getOpcode()) {
3014 default: return nullptr;
3015 case NVPTXISD::Tex1DFloatS32:
3016 Opc = NVPTX::TEX_1D_F32_S32;
3018 case NVPTXISD::Tex1DFloatFloat:
3019 Opc = NVPTX::TEX_1D_F32_F32;
3021 case NVPTXISD::Tex1DFloatFloatLevel:
3022 Opc = NVPTX::TEX_1D_F32_F32_LEVEL;
3024 case NVPTXISD::Tex1DFloatFloatGrad:
3025 Opc = NVPTX::TEX_1D_F32_F32_GRAD;
3027 case NVPTXISD::Tex1DS32S32:
3028 Opc = NVPTX::TEX_1D_S32_S32;
3030 case NVPTXISD::Tex1DS32Float:
3031 Opc = NVPTX::TEX_1D_S32_F32;
3033 case NVPTXISD::Tex1DS32FloatLevel:
3034 Opc = NVPTX::TEX_1D_S32_F32_LEVEL;
3036 case NVPTXISD::Tex1DS32FloatGrad:
3037 Opc = NVPTX::TEX_1D_S32_F32_GRAD;
3039 case NVPTXISD::Tex1DU32S32:
3040 Opc = NVPTX::TEX_1D_U32_S32;
3042 case NVPTXISD::Tex1DU32Float:
3043 Opc = NVPTX::TEX_1D_U32_F32;
3045 case NVPTXISD::Tex1DU32FloatLevel:
3046 Opc = NVPTX::TEX_1D_U32_F32_LEVEL;
3048 case NVPTXISD::Tex1DU32FloatGrad:
3049 Opc = NVPTX::TEX_1D_U32_F32_GRAD;
3051 case NVPTXISD::Tex1DArrayFloatS32:
3052 Opc = NVPTX::TEX_1D_ARRAY_F32_S32;
3054 case NVPTXISD::Tex1DArrayFloatFloat:
3055 Opc = NVPTX::TEX_1D_ARRAY_F32_F32;
3057 case NVPTXISD::Tex1DArrayFloatFloatLevel:
3058 Opc = NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL;
3060 case NVPTXISD::Tex1DArrayFloatFloatGrad:
3061 Opc = NVPTX::TEX_1D_ARRAY_F32_F32_GRAD;
3063 case NVPTXISD::Tex1DArrayS32S32:
3064 Opc = NVPTX::TEX_1D_ARRAY_S32_S32;
3066 case NVPTXISD::Tex1DArrayS32Float:
3067 Opc = NVPTX::TEX_1D_ARRAY_S32_F32;
3069 case NVPTXISD::Tex1DArrayS32FloatLevel:
3070 Opc = NVPTX::TEX_1D_ARRAY_S32_F32_LEVEL;
3072 case NVPTXISD::Tex1DArrayS32FloatGrad:
3073 Opc = NVPTX::TEX_1D_ARRAY_S32_F32_GRAD;
3075 case NVPTXISD::Tex1DArrayU32S32:
3076 Opc = NVPTX::TEX_1D_ARRAY_U32_S32;
3078 case NVPTXISD::Tex1DArrayU32Float:
3079 Opc = NVPTX::TEX_1D_ARRAY_U32_F32;
3081 case NVPTXISD::Tex1DArrayU32FloatLevel:
3082 Opc = NVPTX::TEX_1D_ARRAY_U32_F32_LEVEL;
3084 case NVPTXISD::Tex1DArrayU32FloatGrad:
3085 Opc = NVPTX::TEX_1D_ARRAY_U32_F32_GRAD;
3087 case NVPTXISD::Tex2DFloatS32:
3088 Opc = NVPTX::TEX_2D_F32_S32;
3090 case NVPTXISD::Tex2DFloatFloat:
3091 Opc = NVPTX::TEX_2D_F32_F32;
3093 case NVPTXISD::Tex2DFloatFloatLevel:
3094 Opc = NVPTX::TEX_2D_F32_F32_LEVEL;
3096 case NVPTXISD::Tex2DFloatFloatGrad:
3097 Opc = NVPTX::TEX_2D_F32_F32_GRAD;
3099 case NVPTXISD::Tex2DS32S32:
3100 Opc = NVPTX::TEX_2D_S32_S32;
3102 case NVPTXISD::Tex2DS32Float:
3103 Opc = NVPTX::TEX_2D_S32_F32;
3105 case NVPTXISD::Tex2DS32FloatLevel:
3106 Opc = NVPTX::TEX_2D_S32_F32_LEVEL;
3108 case NVPTXISD::Tex2DS32FloatGrad:
3109 Opc = NVPTX::TEX_2D_S32_F32_GRAD;
3111 case NVPTXISD::Tex2DU32S32:
3112 Opc = NVPTX::TEX_2D_U32_S32;
3114 case NVPTXISD::Tex2DU32Float:
3115 Opc = NVPTX::TEX_2D_U32_F32;
3117 case NVPTXISD::Tex2DU32FloatLevel:
3118 Opc = NVPTX::TEX_2D_U32_F32_LEVEL;
3120 case NVPTXISD::Tex2DU32FloatGrad:
3121 Opc = NVPTX::TEX_2D_U32_F32_GRAD;
3123 case NVPTXISD::Tex2DArrayFloatS32:
3124 Opc = NVPTX::TEX_2D_ARRAY_F32_S32;
3126 case NVPTXISD::Tex2DArrayFloatFloat:
3127 Opc = NVPTX::TEX_2D_ARRAY_F32_F32;
3129 case NVPTXISD::Tex2DArrayFloatFloatLevel:
3130 Opc = NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL;
3132 case NVPTXISD::Tex2DArrayFloatFloatGrad:
3133 Opc = NVPTX::TEX_2D_ARRAY_F32_F32_GRAD;
3135 case NVPTXISD::Tex2DArrayS32S32:
3136 Opc = NVPTX::TEX_2D_ARRAY_S32_S32;
3138 case NVPTXISD::Tex2DArrayS32Float:
3139 Opc = NVPTX::TEX_2D_ARRAY_S32_F32;
3141 case NVPTXISD::Tex2DArrayS32FloatLevel:
3142 Opc = NVPTX::TEX_2D_ARRAY_S32_F32_LEVEL;
3144 case NVPTXISD::Tex2DArrayS32FloatGrad:
3145 Opc = NVPTX::TEX_2D_ARRAY_S32_F32_GRAD;
3147 case NVPTXISD::Tex2DArrayU32S32:
3148 Opc = NVPTX::TEX_2D_ARRAY_U32_S32;
3150 case NVPTXISD::Tex2DArrayU32Float:
3151 Opc = NVPTX::TEX_2D_ARRAY_U32_F32;
3153 case NVPTXISD::Tex2DArrayU32FloatLevel:
3154 Opc = NVPTX::TEX_2D_ARRAY_U32_F32_LEVEL;
3156 case NVPTXISD::Tex2DArrayU32FloatGrad:
3157 Opc = NVPTX::TEX_2D_ARRAY_U32_F32_GRAD;
3159 case NVPTXISD::Tex3DFloatS32:
3160 Opc = NVPTX::TEX_3D_F32_S32;
3162 case NVPTXISD::Tex3DFloatFloat:
3163 Opc = NVPTX::TEX_3D_F32_F32;
3165 case NVPTXISD::Tex3DFloatFloatLevel:
3166 Opc = NVPTX::TEX_3D_F32_F32_LEVEL;
3168 case NVPTXISD::Tex3DFloatFloatGrad:
3169 Opc = NVPTX::TEX_3D_F32_F32_GRAD;
3171 case NVPTXISD::Tex3DS32S32:
3172 Opc = NVPTX::TEX_3D_S32_S32;
3174 case NVPTXISD::Tex3DS32Float:
3175 Opc = NVPTX::TEX_3D_S32_F32;
3177 case NVPTXISD::Tex3DS32FloatLevel:
3178 Opc = NVPTX::TEX_3D_S32_F32_LEVEL;
3180 case NVPTXISD::Tex3DS32FloatGrad:
3181 Opc = NVPTX::TEX_3D_S32_F32_GRAD;
3183 case NVPTXISD::Tex3DU32S32:
3184 Opc = NVPTX::TEX_3D_U32_S32;
3186 case NVPTXISD::Tex3DU32Float:
3187 Opc = NVPTX::TEX_3D_U32_F32;
3189 case NVPTXISD::Tex3DU32FloatLevel:
3190 Opc = NVPTX::TEX_3D_U32_F32_LEVEL;
3192 case NVPTXISD::Tex3DU32FloatGrad:
3193 Opc = NVPTX::TEX_3D_U32_F32_GRAD;
3195 case NVPTXISD::TexCubeFloatFloat:
3196 Opc = NVPTX::TEX_CUBE_F32_F32;
3198 case NVPTXISD::TexCubeFloatFloatLevel:
3199 Opc = NVPTX::TEX_CUBE_F32_F32_LEVEL;
3201 case NVPTXISD::TexCubeS32Float:
3202 Opc = NVPTX::TEX_CUBE_S32_F32;
3204 case NVPTXISD::TexCubeS32FloatLevel:
3205 Opc = NVPTX::TEX_CUBE_S32_F32_LEVEL;
3207 case NVPTXISD::TexCubeU32Float:
3208 Opc = NVPTX::TEX_CUBE_U32_F32;
3210 case NVPTXISD::TexCubeU32FloatLevel:
3211 Opc = NVPTX::TEX_CUBE_U32_F32_LEVEL;
3213 case NVPTXISD::TexCubeArrayFloatFloat:
3214 Opc = NVPTX::TEX_CUBE_ARRAY_F32_F32;
3216 case NVPTXISD::TexCubeArrayFloatFloatLevel:
3217 Opc = NVPTX::TEX_CUBE_ARRAY_F32_F32_LEVEL;
3219 case NVPTXISD::TexCubeArrayS32Float:
3220 Opc = NVPTX::TEX_CUBE_ARRAY_S32_F32;
3222 case NVPTXISD::TexCubeArrayS32FloatLevel:
3223 Opc = NVPTX::TEX_CUBE_ARRAY_S32_F32_LEVEL;
3225 case NVPTXISD::TexCubeArrayU32Float:
3226 Opc = NVPTX::TEX_CUBE_ARRAY_U32_F32;
3228 case NVPTXISD::TexCubeArrayU32FloatLevel:
3229 Opc = NVPTX::TEX_CUBE_ARRAY_U32_F32_LEVEL;
3231 case NVPTXISD::Tld4R2DFloatFloat:
3232 Opc = NVPTX::TLD4_R_2D_F32_F32;
3234 case NVPTXISD::Tld4G2DFloatFloat:
3235 Opc = NVPTX::TLD4_G_2D_F32_F32;
3237 case NVPTXISD::Tld4B2DFloatFloat:
3238 Opc = NVPTX::TLD4_B_2D_F32_F32;
3240 case NVPTXISD::Tld4A2DFloatFloat:
3241 Opc = NVPTX::TLD4_A_2D_F32_F32;
3243 case NVPTXISD::Tld4R2DS64Float:
3244 Opc = NVPTX::TLD4_R_2D_S32_F32;
3246 case NVPTXISD::Tld4G2DS64Float:
3247 Opc = NVPTX::TLD4_G_2D_S32_F32;
3249 case NVPTXISD::Tld4B2DS64Float:
3250 Opc = NVPTX::TLD4_B_2D_S32_F32;
3252 case NVPTXISD::Tld4A2DS64Float:
3253 Opc = NVPTX::TLD4_A_2D_S32_F32;
3255 case NVPTXISD::Tld4R2DU64Float:
3256 Opc = NVPTX::TLD4_R_2D_U32_F32;
3258 case NVPTXISD::Tld4G2DU64Float:
3259 Opc = NVPTX::TLD4_G_2D_U32_F32;
3261 case NVPTXISD::Tld4B2DU64Float:
3262 Opc = NVPTX::TLD4_B_2D_U32_F32;
3264 case NVPTXISD::Tld4A2DU64Float:
3265 Opc = NVPTX::TLD4_A_2D_U32_F32;
3267 case NVPTXISD::TexUnified1DFloatS32:
3268 Opc = NVPTX::TEX_UNIFIED_1D_F32_S32;
3270 case NVPTXISD::TexUnified1DFloatFloat:
3271 Opc = NVPTX::TEX_UNIFIED_1D_F32_F32;
3273 case NVPTXISD::TexUnified1DFloatFloatLevel:
3274 Opc = NVPTX::TEX_UNIFIED_1D_F32_F32_LEVEL;
3276 case NVPTXISD::TexUnified1DFloatFloatGrad:
3277 Opc = NVPTX::TEX_UNIFIED_1D_F32_F32_GRAD;
3279 case NVPTXISD::TexUnified1DS32S32:
3280 Opc = NVPTX::TEX_UNIFIED_1D_S32_S32;
3282 case NVPTXISD::TexUnified1DS32Float:
3283 Opc = NVPTX::TEX_UNIFIED_1D_S32_F32;
3285 case NVPTXISD::TexUnified1DS32FloatLevel:
3286 Opc = NVPTX::TEX_UNIFIED_1D_S32_F32_LEVEL;
3288 case NVPTXISD::TexUnified1DS32FloatGrad:
3289 Opc = NVPTX::TEX_UNIFIED_1D_S32_F32_GRAD;
3291 case NVPTXISD::TexUnified1DU32S32:
3292 Opc = NVPTX::TEX_UNIFIED_1D_U32_S32;
3294 case NVPTXISD::TexUnified1DU32Float:
3295 Opc = NVPTX::TEX_UNIFIED_1D_U32_F32;
3297 case NVPTXISD::TexUnified1DU32FloatLevel:
3298 Opc = NVPTX::TEX_UNIFIED_1D_U32_F32_LEVEL;
3300 case NVPTXISD::TexUnified1DU32FloatGrad:
3301 Opc = NVPTX::TEX_UNIFIED_1D_U32_F32_GRAD;
3303 case NVPTXISD::TexUnified1DArrayFloatS32:
3304 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_S32;
3306 case NVPTXISD::TexUnified1DArrayFloatFloat:
3307 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32;
3309 case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
3310 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_LEVEL;
3312 case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
3313 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_GRAD;
3315 case NVPTXISD::TexUnified1DArrayS32S32:
3316 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_S32;
3318 case NVPTXISD::TexUnified1DArrayS32Float:
3319 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32;
3321 case NVPTXISD::TexUnified1DArrayS32FloatLevel:
3322 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_LEVEL;
3324 case NVPTXISD::TexUnified1DArrayS32FloatGrad:
3325 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_GRAD;
3327 case NVPTXISD::TexUnified1DArrayU32S32:
3328 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_S32;
3330 case NVPTXISD::TexUnified1DArrayU32Float:
3331 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32;
3333 case NVPTXISD::TexUnified1DArrayU32FloatLevel:
3334 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_LEVEL;
3336 case NVPTXISD::TexUnified1DArrayU32FloatGrad:
3337 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_GRAD;
3339 case NVPTXISD::TexUnified2DFloatS32:
3340 Opc = NVPTX::TEX_UNIFIED_2D_F32_S32;
3342 case NVPTXISD::TexUnified2DFloatFloat:
3343 Opc = NVPTX::TEX_UNIFIED_2D_F32_F32;
3345 case NVPTXISD::TexUnified2DFloatFloatLevel:
3346 Opc = NVPTX::TEX_UNIFIED_2D_F32_F32_LEVEL;
3348 case NVPTXISD::TexUnified2DFloatFloatGrad:
3349 Opc = NVPTX::TEX_UNIFIED_2D_F32_F32_GRAD;
3351 case NVPTXISD::TexUnified2DS32S32:
3352 Opc = NVPTX::TEX_UNIFIED_2D_S32_S32;
3354 case NVPTXISD::TexUnified2DS32Float:
3355 Opc = NVPTX::TEX_UNIFIED_2D_S32_F32;
3357 case NVPTXISD::TexUnified2DS32FloatLevel:
3358 Opc = NVPTX::TEX_UNIFIED_2D_S32_F32_LEVEL;
3360 case NVPTXISD::TexUnified2DS32FloatGrad:
3361 Opc = NVPTX::TEX_UNIFIED_2D_S32_F32_GRAD;
3363 case NVPTXISD::TexUnified2DU32S32:
3364 Opc = NVPTX::TEX_UNIFIED_2D_U32_S32;
3366 case NVPTXISD::TexUnified2DU32Float:
3367 Opc = NVPTX::TEX_UNIFIED_2D_U32_F32;
3369 case NVPTXISD::TexUnified2DU32FloatLevel:
3370 Opc = NVPTX::TEX_UNIFIED_2D_U32_F32_LEVEL;
3372 case NVPTXISD::TexUnified2DU32FloatGrad:
3373 Opc = NVPTX::TEX_UNIFIED_2D_U32_F32_GRAD;
3375 case NVPTXISD::TexUnified2DArrayFloatS32:
3376 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_S32;
3378 case NVPTXISD::TexUnified2DArrayFloatFloat:
3379 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32;
3381 case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
3382 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_LEVEL;
3384 case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
3385 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_GRAD;
3387 case NVPTXISD::TexUnified2DArrayS32S32:
3388 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_S32;
3390 case NVPTXISD::TexUnified2DArrayS32Float:
3391 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32;
3393 case NVPTXISD::TexUnified2DArrayS32FloatLevel:
3394 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_LEVEL;
3396 case NVPTXISD::TexUnified2DArrayS32FloatGrad:
3397 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_GRAD;
3399 case NVPTXISD::TexUnified2DArrayU32S32:
3400 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_S32;
3402 case NVPTXISD::TexUnified2DArrayU32Float:
3403 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32;
3405 case NVPTXISD::TexUnified2DArrayU32FloatLevel:
3406 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_LEVEL;
3408 case NVPTXISD::TexUnified2DArrayU32FloatGrad:
3409 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_GRAD;
3411 case NVPTXISD::TexUnified3DFloatS32:
3412 Opc = NVPTX::TEX_UNIFIED_3D_F32_S32;
3414 case NVPTXISD::TexUnified3DFloatFloat:
3415 Opc = NVPTX::TEX_UNIFIED_3D_F32_F32;
3417 case NVPTXISD::TexUnified3DFloatFloatLevel:
3418 Opc = NVPTX::TEX_UNIFIED_3D_F32_F32_LEVEL;
3420 case NVPTXISD::TexUnified3DFloatFloatGrad:
3421 Opc = NVPTX::TEX_UNIFIED_3D_F32_F32_GRAD;
3423 case NVPTXISD::TexUnified3DS32S32:
3424 Opc = NVPTX::TEX_UNIFIED_3D_S32_S32;
3426 case NVPTXISD::TexUnified3DS32Float:
3427 Opc = NVPTX::TEX_UNIFIED_3D_S32_F32;
3429 case NVPTXISD::TexUnified3DS32FloatLevel:
3430 Opc = NVPTX::TEX_UNIFIED_3D_S32_F32_LEVEL;
3432 case NVPTXISD::TexUnified3DS32FloatGrad:
3433 Opc = NVPTX::TEX_UNIFIED_3D_S32_F32_GRAD;
3435 case NVPTXISD::TexUnified3DU32S32:
3436 Opc = NVPTX::TEX_UNIFIED_3D_U32_S32;
3438 case NVPTXISD::TexUnified3DU32Float:
3439 Opc = NVPTX::TEX_UNIFIED_3D_U32_F32;
3441 case NVPTXISD::TexUnified3DU32FloatLevel:
3442 Opc = NVPTX::TEX_UNIFIED_3D_U32_F32_LEVEL;
3444 case NVPTXISD::TexUnified3DU32FloatGrad:
3445 Opc = NVPTX::TEX_UNIFIED_3D_U32_F32_GRAD;
3447 case NVPTXISD::TexUnifiedCubeFloatFloat:
3448 Opc = NVPTX::TEX_UNIFIED_CUBE_F32_F32;
3450 case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
3451 Opc = NVPTX::TEX_UNIFIED_CUBE_F32_F32_LEVEL;
3453 case NVPTXISD::TexUnifiedCubeS32Float:
3454 Opc = NVPTX::TEX_UNIFIED_CUBE_S32_F32;
3456 case NVPTXISD::TexUnifiedCubeS32FloatLevel:
3457 Opc = NVPTX::TEX_UNIFIED_CUBE_S32_F32_LEVEL;
3459 case NVPTXISD::TexUnifiedCubeU32Float:
3460 Opc = NVPTX::TEX_UNIFIED_CUBE_U32_F32;
3462 case NVPTXISD::TexUnifiedCubeU32FloatLevel:
3463 Opc = NVPTX::TEX_UNIFIED_CUBE_U32_F32_LEVEL;
3465 case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
3466 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32;
3468 case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
3469 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32_LEVEL;
3471 case NVPTXISD::TexUnifiedCubeArrayS32Float:
3472 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32;
3474 case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
3475 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32_LEVEL;
3477 case NVPTXISD::TexUnifiedCubeArrayU32Float:
3478 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32;
3480 case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
3481 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32_LEVEL;
3483 case NVPTXISD::Tld4UnifiedR2DFloatFloat:
3484 Opc = NVPTX::TLD4_UNIFIED_R_2D_F32_F32;
3486 case NVPTXISD::Tld4UnifiedG2DFloatFloat:
3487 Opc = NVPTX::TLD4_UNIFIED_G_2D_F32_F32;
3489 case NVPTXISD::Tld4UnifiedB2DFloatFloat:
3490 Opc = NVPTX::TLD4_UNIFIED_B_2D_F32_F32;
3492 case NVPTXISD::Tld4UnifiedA2DFloatFloat:
3493 Opc = NVPTX::TLD4_UNIFIED_A_2D_F32_F32;
3495 case NVPTXISD::Tld4UnifiedR2DS64Float:
3496 Opc = NVPTX::TLD4_UNIFIED_R_2D_S32_F32;
3498 case NVPTXISD::Tld4UnifiedG2DS64Float:
3499 Opc = NVPTX::TLD4_UNIFIED_G_2D_S32_F32;
3501 case NVPTXISD::Tld4UnifiedB2DS64Float:
3502 Opc = NVPTX::TLD4_UNIFIED_B_2D_S32_F32;
3504 case NVPTXISD::Tld4UnifiedA2DS64Float:
3505 Opc = NVPTX::TLD4_UNIFIED_A_2D_S32_F32;
3507 case NVPTXISD::Tld4UnifiedR2DU64Float:
3508 Opc = NVPTX::TLD4_UNIFIED_R_2D_U32_F32;
3510 case NVPTXISD::Tld4UnifiedG2DU64Float:
3511 Opc = NVPTX::TLD4_UNIFIED_G_2D_U32_F32;
3513 case NVPTXISD::Tld4UnifiedB2DU64Float:
3514 Opc = NVPTX::TLD4_UNIFIED_B_2D_U32_F32;
3516 case NVPTXISD::Tld4UnifiedA2DU64Float:
3517 Opc = NVPTX::TLD4_UNIFIED_A_2D_U32_F32;
3521 // Copy over operands
3522 for (unsigned i = 1; i < N->getNumOperands(); ++i) {
3523 Ops.push_back(N->getOperand(i));
3526 Ops.push_back(Chain);
3527 Ret = CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);
3531 SDNode *NVPTXDAGToDAGISel::SelectSurfaceIntrinsic(SDNode *N) {
3532 SDValue Chain = N->getOperand(0);
3533 SDValue TexHandle = N->getOperand(1);
3534 SDNode *Ret = nullptr;
3536 SmallVector<SDValue, 8> Ops;
3537 switch (N->getOpcode()) {
3538 default: return nullptr;
3539 case NVPTXISD::Suld1DI8Clamp:
3540 Opc = NVPTX::SULD_1D_I8_CLAMP;
3541 Ops.push_back(TexHandle);
3542 Ops.push_back(N->getOperand(2));
3543 Ops.push_back(Chain);
3545 case NVPTXISD::Suld1DI16Clamp:
3546 Opc = NVPTX::SULD_1D_I16_CLAMP;
3547 Ops.push_back(TexHandle);
3548 Ops.push_back(N->getOperand(2));
3549 Ops.push_back(Chain);
3551 case NVPTXISD::Suld1DI32Clamp:
3552 Opc = NVPTX::SULD_1D_I32_CLAMP;
3553 Ops.push_back(TexHandle);
3554 Ops.push_back(N->getOperand(2));
3555 Ops.push_back(Chain);
3557 case NVPTXISD::Suld1DI64Clamp:
3558 Opc = NVPTX::SULD_1D_I64_CLAMP;
3559 Ops.push_back(TexHandle);
3560 Ops.push_back(N->getOperand(2));
3561 Ops.push_back(Chain);
3563 case NVPTXISD::Suld1DV2I8Clamp:
3564 Opc = NVPTX::SULD_1D_V2I8_CLAMP;
3565 Ops.push_back(TexHandle);
3566 Ops.push_back(N->getOperand(2));
3567 Ops.push_back(Chain);
3569 case NVPTXISD::Suld1DV2I16Clamp:
3570 Opc = NVPTX::SULD_1D_V2I16_CLAMP;
3571 Ops.push_back(TexHandle);
3572 Ops.push_back(N->getOperand(2));
3573 Ops.push_back(Chain);
3575 case NVPTXISD::Suld1DV2I32Clamp:
3576 Opc = NVPTX::SULD_1D_V2I32_CLAMP;
3577 Ops.push_back(TexHandle);
3578 Ops.push_back(N->getOperand(2));
3579 Ops.push_back(Chain);
3581 case NVPTXISD::Suld1DV2I64Clamp:
3582 Opc = NVPTX::SULD_1D_V2I64_CLAMP;
3583 Ops.push_back(TexHandle);
3584 Ops.push_back(N->getOperand(2));
3585 Ops.push_back(Chain);
3587 case NVPTXISD::Suld1DV4I8Clamp:
3588 Opc = NVPTX::SULD_1D_V4I8_CLAMP;
3589 Ops.push_back(TexHandle);
3590 Ops.push_back(N->getOperand(2));
3591 Ops.push_back(Chain);
3593 case NVPTXISD::Suld1DV4I16Clamp:
3594 Opc = NVPTX::SULD_1D_V4I16_CLAMP;
3595 Ops.push_back(TexHandle);
3596 Ops.push_back(N->getOperand(2));
3597 Ops.push_back(Chain);
3599 case NVPTXISD::Suld1DV4I32Clamp:
3600 Opc = NVPTX::SULD_1D_V4I32_CLAMP;
3601 Ops.push_back(TexHandle);
3602 Ops.push_back(N->getOperand(2));
3603 Ops.push_back(Chain);
3605 case NVPTXISD::Suld1DArrayI8Clamp:
3606 Opc = NVPTX::SULD_1D_ARRAY_I8_CLAMP;
3607 Ops.push_back(TexHandle);
3608 Ops.push_back(N->getOperand(2));
3609 Ops.push_back(N->getOperand(3));
3610 Ops.push_back(Chain);
3612 case NVPTXISD::Suld1DArrayI16Clamp:
3613 Opc = NVPTX::SULD_1D_ARRAY_I16_CLAMP;
3614 Ops.push_back(TexHandle);
3615 Ops.push_back(N->getOperand(2));
3616 Ops.push_back(N->getOperand(3));
3617 Ops.push_back(Chain);
3619 case NVPTXISD::Suld1DArrayI32Clamp:
3620 Opc = NVPTX::SULD_1D_ARRAY_I32_CLAMP;
3621 Ops.push_back(TexHandle);
3622 Ops.push_back(N->getOperand(2));
3623 Ops.push_back(N->getOperand(3));
3624 Ops.push_back(Chain);
3626 case NVPTXISD::Suld1DArrayI64Clamp:
3627 Opc = NVPTX::SULD_1D_ARRAY_I64_CLAMP;
3628 Ops.push_back(TexHandle);
3629 Ops.push_back(N->getOperand(2));
3630 Ops.push_back(N->getOperand(3));
3631 Ops.push_back(Chain);
3633 case NVPTXISD::Suld1DArrayV2I8Clamp:
3634 Opc = NVPTX::SULD_1D_ARRAY_V2I8_CLAMP;
3635 Ops.push_back(TexHandle);
3636 Ops.push_back(N->getOperand(2));
3637 Ops.push_back(N->getOperand(3));
3638 Ops.push_back(Chain);
3640 case NVPTXISD::Suld1DArrayV2I16Clamp:
3641 Opc = NVPTX::SULD_1D_ARRAY_V2I16_CLAMP;
3642 Ops.push_back(TexHandle);
3643 Ops.push_back(N->getOperand(2));
3644 Ops.push_back(N->getOperand(3));
3645 Ops.push_back(Chain);
3647 case NVPTXISD::Suld1DArrayV2I32Clamp:
3648 Opc = NVPTX::SULD_1D_ARRAY_V2I32_CLAMP;
3649 Ops.push_back(TexHandle);
3650 Ops.push_back(N->getOperand(2));
3651 Ops.push_back(N->getOperand(3));
3652 Ops.push_back(Chain);
3654 case NVPTXISD::Suld1DArrayV2I64Clamp:
3655 Opc = NVPTX::SULD_1D_ARRAY_V2I64_CLAMP;
3656 Ops.push_back(TexHandle);
3657 Ops.push_back(N->getOperand(2));
3658 Ops.push_back(N->getOperand(3));
3659 Ops.push_back(Chain);
3661 case NVPTXISD::Suld1DArrayV4I8Clamp:
3662 Opc = NVPTX::SULD_1D_ARRAY_V4I8_CLAMP;
3663 Ops.push_back(TexHandle);
3664 Ops.push_back(N->getOperand(2));
3665 Ops.push_back(N->getOperand(3));
3666 Ops.push_back(Chain);
3668 case NVPTXISD::Suld1DArrayV4I16Clamp:
3669 Opc = NVPTX::SULD_1D_ARRAY_V4I16_CLAMP;
3670 Ops.push_back(TexHandle);
3671 Ops.push_back(N->getOperand(2));
3672 Ops.push_back(N->getOperand(3));
3673 Ops.push_back(Chain);
3675 case NVPTXISD::Suld1DArrayV4I32Clamp:
3676 Opc = NVPTX::SULD_1D_ARRAY_V4I32_CLAMP;
3677 Ops.push_back(TexHandle);
3678 Ops.push_back(N->getOperand(2));
3679 Ops.push_back(N->getOperand(3));
3680 Ops.push_back(Chain);
3682 case NVPTXISD::Suld2DI8Clamp:
3683 Opc = NVPTX::SULD_2D_I8_CLAMP;
3684 Ops.push_back(TexHandle);
3685 Ops.push_back(N->getOperand(2));
3686 Ops.push_back(N->getOperand(3));
3687 Ops.push_back(Chain);
3689 case NVPTXISD::Suld2DI16Clamp:
3690 Opc = NVPTX::SULD_2D_I16_CLAMP;
3691 Ops.push_back(TexHandle);
3692 Ops.push_back(N->getOperand(2));
3693 Ops.push_back(N->getOperand(3));
3694 Ops.push_back(Chain);
3696 case NVPTXISD::Suld2DI32Clamp:
3697 Opc = NVPTX::SULD_2D_I32_CLAMP;
3698 Ops.push_back(TexHandle);
3699 Ops.push_back(N->getOperand(2));
3700 Ops.push_back(N->getOperand(3));
3701 Ops.push_back(Chain);
3703 case NVPTXISD::Suld2DI64Clamp:
3704 Opc = NVPTX::SULD_2D_I64_CLAMP;
3705 Ops.push_back(TexHandle);
3706 Ops.push_back(N->getOperand(2));
3707 Ops.push_back(N->getOperand(3));
3708 Ops.push_back(Chain);
3710 case NVPTXISD::Suld2DV2I8Clamp:
3711 Opc = NVPTX::SULD_2D_V2I8_CLAMP;
3712 Ops.push_back(TexHandle);
3713 Ops.push_back(N->getOperand(2));
3714 Ops.push_back(N->getOperand(3));
3715 Ops.push_back(Chain);
3717 case NVPTXISD::Suld2DV2I16Clamp:
3718 Opc = NVPTX::SULD_2D_V2I16_CLAMP;
3719 Ops.push_back(TexHandle);
3720 Ops.push_back(N->getOperand(2));
3721 Ops.push_back(N->getOperand(3));
3722 Ops.push_back(Chain);
3724 case NVPTXISD::Suld2DV2I32Clamp:
3725 Opc = NVPTX::SULD_2D_V2I32_CLAMP;
3726 Ops.push_back(TexHandle);
3727 Ops.push_back(N->getOperand(2));
3728 Ops.push_back(N->getOperand(3));
3729 Ops.push_back(Chain);
3731 case NVPTXISD::Suld2DV2I64Clamp:
3732 Opc = NVPTX::SULD_2D_V2I64_CLAMP;
3733 Ops.push_back(TexHandle);
3734 Ops.push_back(N->getOperand(2));
3735 Ops.push_back(N->getOperand(3));
3736 Ops.push_back(Chain);
3738 case NVPTXISD::Suld2DV4I8Clamp:
3739 Opc = NVPTX::SULD_2D_V4I8_CLAMP;
3740 Ops.push_back(TexHandle);
3741 Ops.push_back(N->getOperand(2));
3742 Ops.push_back(N->getOperand(3));
3743 Ops.push_back(Chain);
3745 case NVPTXISD::Suld2DV4I16Clamp:
3746 Opc = NVPTX::SULD_2D_V4I16_CLAMP;
3747 Ops.push_back(TexHandle);
3748 Ops.push_back(N->getOperand(2));
3749 Ops.push_back(N->getOperand(3));
3750 Ops.push_back(Chain);
3752 case NVPTXISD::Suld2DV4I32Clamp:
3753 Opc = NVPTX::SULD_2D_V4I32_CLAMP;
3754 Ops.push_back(TexHandle);
3755 Ops.push_back(N->getOperand(2));
3756 Ops.push_back(N->getOperand(3));
3757 Ops.push_back(Chain);
3759 case NVPTXISD::Suld2DArrayI8Clamp:
3760 Opc = NVPTX::SULD_2D_ARRAY_I8_CLAMP;
3761 Ops.push_back(TexHandle);
3762 Ops.push_back(N->getOperand(2));
3763 Ops.push_back(N->getOperand(3));
3764 Ops.push_back(N->getOperand(4));
3765 Ops.push_back(Chain);
3767 case NVPTXISD::Suld2DArrayI16Clamp:
3768 Opc = NVPTX::SULD_2D_ARRAY_I16_CLAMP;
3769 Ops.push_back(TexHandle);
3770 Ops.push_back(N->getOperand(2));
3771 Ops.push_back(N->getOperand(3));
3772 Ops.push_back(N->getOperand(4));
3773 Ops.push_back(Chain);
3775 case NVPTXISD::Suld2DArrayI32Clamp:
3776 Opc = NVPTX::SULD_2D_ARRAY_I32_CLAMP;
3777 Ops.push_back(TexHandle);
3778 Ops.push_back(N->getOperand(2));
3779 Ops.push_back(N->getOperand(3));
3780 Ops.push_back(N->getOperand(4));
3781 Ops.push_back(Chain);
3783 case NVPTXISD::Suld2DArrayI64Clamp:
3784 Opc = NVPTX::SULD_2D_ARRAY_I64_CLAMP;
3785 Ops.push_back(TexHandle);
3786 Ops.push_back(N->getOperand(2));
3787 Ops.push_back(N->getOperand(3));
3788 Ops.push_back(N->getOperand(4));
3789 Ops.push_back(Chain);
3791 case NVPTXISD::Suld2DArrayV2I8Clamp:
3792 Opc = NVPTX::SULD_2D_ARRAY_V2I8_CLAMP;
3793 Ops.push_back(TexHandle);
3794 Ops.push_back(N->getOperand(2));
3795 Ops.push_back(N->getOperand(3));
3796 Ops.push_back(N->getOperand(4));
3797 Ops.push_back(Chain);
3799 case NVPTXISD::Suld2DArrayV2I16Clamp:
3800 Opc = NVPTX::SULD_2D_ARRAY_V2I16_CLAMP;
3801 Ops.push_back(TexHandle);
3802 Ops.push_back(N->getOperand(2));
3803 Ops.push_back(N->getOperand(3));
3804 Ops.push_back(N->getOperand(4));
3805 Ops.push_back(Chain);
3807 case NVPTXISD::Suld2DArrayV2I32Clamp:
3808 Opc = NVPTX::SULD_2D_ARRAY_V2I32_CLAMP;
3809 Ops.push_back(TexHandle);
3810 Ops.push_back(N->getOperand(2));
3811 Ops.push_back(N->getOperand(3));
3812 Ops.push_back(N->getOperand(4));
3813 Ops.push_back(Chain);
3815 case NVPTXISD::Suld2DArrayV2I64Clamp:
3816 Opc = NVPTX::SULD_2D_ARRAY_V2I64_CLAMP;
3817 Ops.push_back(TexHandle);
3818 Ops.push_back(N->getOperand(2));
3819 Ops.push_back(N->getOperand(3));
3820 Ops.push_back(N->getOperand(4));
3821 Ops.push_back(Chain);
3823 case NVPTXISD::Suld2DArrayV4I8Clamp:
3824 Opc = NVPTX::SULD_2D_ARRAY_V4I8_CLAMP;
3825 Ops.push_back(TexHandle);
3826 Ops.push_back(N->getOperand(2));
3827 Ops.push_back(N->getOperand(3));
3828 Ops.push_back(N->getOperand(4));
3829 Ops.push_back(Chain);
3831 case NVPTXISD::Suld2DArrayV4I16Clamp:
3832 Opc = NVPTX::SULD_2D_ARRAY_V4I16_CLAMP;
3833 Ops.push_back(TexHandle);
3834 Ops.push_back(N->getOperand(2));
3835 Ops.push_back(N->getOperand(3));
3836 Ops.push_back(N->getOperand(4));
3837 Ops.push_back(Chain);
3839 case NVPTXISD::Suld2DArrayV4I32Clamp:
3840 Opc = NVPTX::SULD_2D_ARRAY_V4I32_CLAMP;
3841 Ops.push_back(TexHandle);
3842 Ops.push_back(N->getOperand(2));
3843 Ops.push_back(N->getOperand(3));
3844 Ops.push_back(N->getOperand(4));
3845 Ops.push_back(Chain);
3847 case NVPTXISD::Suld3DI8Clamp:
3848 Opc = NVPTX::SULD_3D_I8_CLAMP;
3849 Ops.push_back(TexHandle);
3850 Ops.push_back(N->getOperand(2));
3851 Ops.push_back(N->getOperand(3));
3852 Ops.push_back(N->getOperand(4));
3853 Ops.push_back(Chain);
3855 case NVPTXISD::Suld3DI16Clamp:
3856 Opc = NVPTX::SULD_3D_I16_CLAMP;
3857 Ops.push_back(TexHandle);
3858 Ops.push_back(N->getOperand(2));
3859 Ops.push_back(N->getOperand(3));
3860 Ops.push_back(N->getOperand(4));
3861 Ops.push_back(Chain);
3863 case NVPTXISD::Suld3DI32Clamp:
3864 Opc = NVPTX::SULD_3D_I32_CLAMP;
3865 Ops.push_back(TexHandle);
3866 Ops.push_back(N->getOperand(2));
3867 Ops.push_back(N->getOperand(3));
3868 Ops.push_back(N->getOperand(4));
3869 Ops.push_back(Chain);
3871 case NVPTXISD::Suld3DI64Clamp:
3872 Opc = NVPTX::SULD_3D_I64_CLAMP;
3873 Ops.push_back(TexHandle);
3874 Ops.push_back(N->getOperand(2));
3875 Ops.push_back(N->getOperand(3));
3876 Ops.push_back(N->getOperand(4));
3877 Ops.push_back(Chain);
3879 case NVPTXISD::Suld3DV2I8Clamp:
3880 Opc = NVPTX::SULD_3D_V2I8_CLAMP;
3881 Ops.push_back(TexHandle);
3882 Ops.push_back(N->getOperand(2));
3883 Ops.push_back(N->getOperand(3));
3884 Ops.push_back(N->getOperand(4));
3885 Ops.push_back(Chain);
3887 case NVPTXISD::Suld3DV2I16Clamp:
3888 Opc = NVPTX::SULD_3D_V2I16_CLAMP;
3889 Ops.push_back(TexHandle);
3890 Ops.push_back(N->getOperand(2));
3891 Ops.push_back(N->getOperand(3));
3892 Ops.push_back(N->getOperand(4));
3893 Ops.push_back(Chain);
3895 case NVPTXISD::Suld3DV2I32Clamp:
3896 Opc = NVPTX::SULD_3D_V2I32_CLAMP;
3897 Ops.push_back(TexHandle);
3898 Ops.push_back(N->getOperand(2));
3899 Ops.push_back(N->getOperand(3));
3900 Ops.push_back(N->getOperand(4));
3901 Ops.push_back(Chain);
3903 case NVPTXISD::Suld3DV2I64Clamp:
3904 Opc = NVPTX::SULD_3D_V2I64_CLAMP;
3905 Ops.push_back(TexHandle);
3906 Ops.push_back(N->getOperand(2));
3907 Ops.push_back(N->getOperand(3));
3908 Ops.push_back(N->getOperand(4));
3909 Ops.push_back(Chain);
3911 case NVPTXISD::Suld3DV4I8Clamp:
3912 Opc = NVPTX::SULD_3D_V4I8_CLAMP;
3913 Ops.push_back(TexHandle);
3914 Ops.push_back(N->getOperand(2));
3915 Ops.push_back(N->getOperand(3));
3916 Ops.push_back(N->getOperand(4));
3917 Ops.push_back(Chain);
3919 case NVPTXISD::Suld3DV4I16Clamp:
3920 Opc = NVPTX::SULD_3D_V4I16_CLAMP;
3921 Ops.push_back(TexHandle);
3922 Ops.push_back(N->getOperand(2));
3923 Ops.push_back(N->getOperand(3));
3924 Ops.push_back(N->getOperand(4));
3925 Ops.push_back(Chain);
3927 case NVPTXISD::Suld3DV4I32Clamp:
3928 Opc = NVPTX::SULD_3D_V4I32_CLAMP;
3929 Ops.push_back(TexHandle);
3930 Ops.push_back(N->getOperand(2));
3931 Ops.push_back(N->getOperand(3));
3932 Ops.push_back(N->getOperand(4));
3933 Ops.push_back(Chain);
3935 case NVPTXISD::Suld1DI8Trap:
3936 Opc = NVPTX::SULD_1D_I8_TRAP;
3937 Ops.push_back(TexHandle);
3938 Ops.push_back(N->getOperand(2));
3939 Ops.push_back(Chain);
3941 case NVPTXISD::Suld1DI16Trap:
3942 Opc = NVPTX::SULD_1D_I16_TRAP;
3943 Ops.push_back(TexHandle);
3944 Ops.push_back(N->getOperand(2));
3945 Ops.push_back(Chain);
3947 case NVPTXISD::Suld1DI32Trap:
3948 Opc = NVPTX::SULD_1D_I32_TRAP;
3949 Ops.push_back(TexHandle);
3950 Ops.push_back(N->getOperand(2));
3951 Ops.push_back(Chain);
3953 case NVPTXISD::Suld1DI64Trap:
3954 Opc = NVPTX::SULD_1D_I64_TRAP;
3955 Ops.push_back(TexHandle);
3956 Ops.push_back(N->getOperand(2));
3957 Ops.push_back(Chain);
3959 case NVPTXISD::Suld1DV2I8Trap:
3960 Opc = NVPTX::SULD_1D_V2I8_TRAP;
3961 Ops.push_back(TexHandle);
3962 Ops.push_back(N->getOperand(2));
3963 Ops.push_back(Chain);
3965 case NVPTXISD::Suld1DV2I16Trap:
3966 Opc = NVPTX::SULD_1D_V2I16_TRAP;
3967 Ops.push_back(TexHandle);
3968 Ops.push_back(N->getOperand(2));
3969 Ops.push_back(Chain);
3971 case NVPTXISD::Suld1DV2I32Trap:
3972 Opc = NVPTX::SULD_1D_V2I32_TRAP;
3973 Ops.push_back(TexHandle);
3974 Ops.push_back(N->getOperand(2));
3975 Ops.push_back(Chain);
3977 case NVPTXISD::Suld1DV2I64Trap:
3978 Opc = NVPTX::SULD_1D_V2I64_TRAP;
3979 Ops.push_back(TexHandle);
3980 Ops.push_back(N->getOperand(2));
3981 Ops.push_back(Chain);
3983 case NVPTXISD::Suld1DV4I8Trap:
3984 Opc = NVPTX::SULD_1D_V4I8_TRAP;
3985 Ops.push_back(TexHandle);
3986 Ops.push_back(N->getOperand(2));
3987 Ops.push_back(Chain);
3989 case NVPTXISD::Suld1DV4I16Trap:
3990 Opc = NVPTX::SULD_1D_V4I16_TRAP;
3991 Ops.push_back(TexHandle);
3992 Ops.push_back(N->getOperand(2));
3993 Ops.push_back(Chain);
3995 case NVPTXISD::Suld1DV4I32Trap:
3996 Opc = NVPTX::SULD_1D_V4I32_TRAP;
3997 Ops.push_back(TexHandle);
3998 Ops.push_back(N->getOperand(2));
3999 Ops.push_back(Chain);
4001 case NVPTXISD::Suld1DArrayI8Trap:
4002 Opc = NVPTX::SULD_1D_ARRAY_I8_TRAP;
4003 Ops.push_back(TexHandle);
4004 Ops.push_back(N->getOperand(2));
4005 Ops.push_back(N->getOperand(3));
4006 Ops.push_back(Chain);
4008 case NVPTXISD::Suld1DArrayI16Trap:
4009 Opc = NVPTX::SULD_1D_ARRAY_I16_TRAP;
4010 Ops.push_back(TexHandle);
4011 Ops.push_back(N->getOperand(2));
4012 Ops.push_back(N->getOperand(3));
4013 Ops.push_back(Chain);
4015 case NVPTXISD::Suld1DArrayI32Trap:
4016 Opc = NVPTX::SULD_1D_ARRAY_I32_TRAP;
4017 Ops.push_back(TexHandle);
4018 Ops.push_back(N->getOperand(2));
4019 Ops.push_back(N->getOperand(3));
4020 Ops.push_back(Chain);
4022 case NVPTXISD::Suld1DArrayI64Trap:
4023 Opc = NVPTX::SULD_1D_ARRAY_I64_TRAP;
4024 Ops.push_back(TexHandle);
4025 Ops.push_back(N->getOperand(2));
4026 Ops.push_back(N->getOperand(3));
4027 Ops.push_back(Chain);
4029 case NVPTXISD::Suld1DArrayV2I8Trap:
4030 Opc = NVPTX::SULD_1D_ARRAY_V2I8_TRAP;
4031 Ops.push_back(TexHandle);
4032 Ops.push_back(N->getOperand(2));
4033 Ops.push_back(N->getOperand(3));
4034 Ops.push_back(Chain);
4036 case NVPTXISD::Suld1DArrayV2I16Trap:
4037 Opc = NVPTX::SULD_1D_ARRAY_V2I16_TRAP;
4038 Ops.push_back(TexHandle);
4039 Ops.push_back(N->getOperand(2));
4040 Ops.push_back(N->getOperand(3));
4041 Ops.push_back(Chain);
4043 case NVPTXISD::Suld1DArrayV2I32Trap:
4044 Opc = NVPTX::SULD_1D_ARRAY_V2I32_TRAP;
4045 Ops.push_back(TexHandle);
4046 Ops.push_back(N->getOperand(2));
4047 Ops.push_back(N->getOperand(3));
4048 Ops.push_back(Chain);
4050 case NVPTXISD::Suld1DArrayV2I64Trap:
4051 Opc = NVPTX::SULD_1D_ARRAY_V2I64_TRAP;
4052 Ops.push_back(TexHandle);
4053 Ops.push_back(N->getOperand(2));
4054 Ops.push_back(N->getOperand(3));
4055 Ops.push_back(Chain);
4057 case NVPTXISD::Suld1DArrayV4I8Trap:
4058 Opc = NVPTX::SULD_1D_ARRAY_V4I8_TRAP;
4059 Ops.push_back(TexHandle);
4060 Ops.push_back(N->getOperand(2));
4061 Ops.push_back(N->getOperand(3));
4062 Ops.push_back(Chain);
4064 case NVPTXISD::Suld1DArrayV4I16Trap:
4065 Opc = NVPTX::SULD_1D_ARRAY_V4I16_TRAP;
4066 Ops.push_back(TexHandle);
4067 Ops.push_back(N->getOperand(2));
4068 Ops.push_back(N->getOperand(3));
4069 Ops.push_back(Chain);
4071 case NVPTXISD::Suld1DArrayV4I32Trap:
4072 Opc = NVPTX::SULD_1D_ARRAY_V4I32_TRAP;
4073 Ops.push_back(TexHandle);
4074 Ops.push_back(N->getOperand(2));
4075 Ops.push_back(N->getOperand(3));
4076 Ops.push_back(Chain);
4078 case NVPTXISD::Suld2DI8Trap:
4079 Opc = NVPTX::SULD_2D_I8_TRAP;
4080 Ops.push_back(TexHandle);
4081 Ops.push_back(N->getOperand(2));
4082 Ops.push_back(N->getOperand(3));
4083 Ops.push_back(Chain);
4085 case NVPTXISD::Suld2DI16Trap:
4086 Opc = NVPTX::SULD_2D_I16_TRAP;
4087 Ops.push_back(TexHandle);
4088 Ops.push_back(N->getOperand(2));
4089 Ops.push_back(N->getOperand(3));
4090 Ops.push_back(Chain);
4092 case NVPTXISD::Suld2DI32Trap:
4093 Opc = NVPTX::SULD_2D_I32_TRAP;
4094 Ops.push_back(TexHandle);
4095 Ops.push_back(N->getOperand(2));
4096 Ops.push_back(N->getOperand(3));
4097 Ops.push_back(Chain);
4099 case NVPTXISD::Suld2DI64Trap:
4100 Opc = NVPTX::SULD_2D_I64_TRAP;
4101 Ops.push_back(TexHandle);
4102 Ops.push_back(N->getOperand(2));
4103 Ops.push_back(N->getOperand(3));
4104 Ops.push_back(Chain);
4106 case NVPTXISD::Suld2DV2I8Trap:
4107 Opc = NVPTX::SULD_2D_V2I8_TRAP;
4108 Ops.push_back(TexHandle);
4109 Ops.push_back(N->getOperand(2));
4110 Ops.push_back(N->getOperand(3));
4111 Ops.push_back(Chain);
4113 case NVPTXISD::Suld2DV2I16Trap:
4114 Opc = NVPTX::SULD_2D_V2I16_TRAP;
4115 Ops.push_back(TexHandle);
4116 Ops.push_back(N->getOperand(2));
4117 Ops.push_back(N->getOperand(3));
4118 Ops.push_back(Chain);
4120 case NVPTXISD::Suld2DV2I32Trap:
4121 Opc = NVPTX::SULD_2D_V2I32_TRAP;
4122 Ops.push_back(TexHandle);
4123 Ops.push_back(N->getOperand(2));
4124 Ops.push_back(N->getOperand(3));
4125 Ops.push_back(Chain);
4127 case NVPTXISD::Suld2DV2I64Trap:
4128 Opc = NVPTX::SULD_2D_V2I64_TRAP;
4129 Ops.push_back(TexHandle);
4130 Ops.push_back(N->getOperand(2));
4131 Ops.push_back(N->getOperand(3));
4132 Ops.push_back(Chain);
4134 case NVPTXISD::Suld2DV4I8Trap:
4135 Opc = NVPTX::SULD_2D_V4I8_TRAP;
4136 Ops.push_back(TexHandle);
4137 Ops.push_back(N->getOperand(2));
4138 Ops.push_back(N->getOperand(3));
4139 Ops.push_back(Chain);
4141 case NVPTXISD::Suld2DV4I16Trap:
4142 Opc = NVPTX::SULD_2D_V4I16_TRAP;
4143 Ops.push_back(TexHandle);
4144 Ops.push_back(N->getOperand(2));
4145 Ops.push_back(N->getOperand(3));
4146 Ops.push_back(Chain);
4148 case NVPTXISD::Suld2DV4I32Trap:
4149 Opc = NVPTX::SULD_2D_V4I32_TRAP;
4150 Ops.push_back(TexHandle);
4151 Ops.push_back(N->getOperand(2));
4152 Ops.push_back(N->getOperand(3));
4153 Ops.push_back(Chain);
4155 case NVPTXISD::Suld2DArrayI8Trap:
4156 Opc = NVPTX::SULD_2D_ARRAY_I8_TRAP;
4157 Ops.push_back(TexHandle);
4158 Ops.push_back(N->getOperand(2));
4159 Ops.push_back(N->getOperand(3));
4160 Ops.push_back(N->getOperand(4));
4161 Ops.push_back(Chain);
4163 case NVPTXISD::Suld2DArrayI16Trap:
4164 Opc = NVPTX::SULD_2D_ARRAY_I16_TRAP;
4165 Ops.push_back(TexHandle);
4166 Ops.push_back(N->getOperand(2));
4167 Ops.push_back(N->getOperand(3));
4168 Ops.push_back(N->getOperand(4));
4169 Ops.push_back(Chain);
4171 case NVPTXISD::Suld2DArrayI32Trap:
4172 Opc = NVPTX::SULD_2D_ARRAY_I32_TRAP;
4173 Ops.push_back(TexHandle);
4174 Ops.push_back(N->getOperand(2));
4175 Ops.push_back(N->getOperand(3));
4176 Ops.push_back(N->getOperand(4));
4177 Ops.push_back(Chain);
4179 case NVPTXISD::Suld2DArrayI64Trap:
4180 Opc = NVPTX::SULD_2D_ARRAY_I64_TRAP;
4181 Ops.push_back(TexHandle);
4182 Ops.push_back(N->getOperand(2));
4183 Ops.push_back(N->getOperand(3));
4184 Ops.push_back(N->getOperand(4));
4185 Ops.push_back(Chain);
4187 case NVPTXISD::Suld2DArrayV2I8Trap:
4188 Opc = NVPTX::SULD_2D_ARRAY_V2I8_TRAP;
4189 Ops.push_back(TexHandle);
4190 Ops.push_back(N->getOperand(2));
4191 Ops.push_back(N->getOperand(3));
4192 Ops.push_back(N->getOperand(4));
4193 Ops.push_back(Chain);
4195 case NVPTXISD::Suld2DArrayV2I16Trap:
4196 Opc = NVPTX::SULD_2D_ARRAY_V2I16_TRAP;
4197 Ops.push_back(TexHandle);
4198 Ops.push_back(N->getOperand(2));
4199 Ops.push_back(N->getOperand(3));
4200 Ops.push_back(N->getOperand(4));
4201 Ops.push_back(Chain);
4203 case NVPTXISD::Suld2DArrayV2I32Trap:
4204 Opc = NVPTX::SULD_2D_ARRAY_V2I32_TRAP;
4205 Ops.push_back(TexHandle);
4206 Ops.push_back(N->getOperand(2));
4207 Ops.push_back(N->getOperand(3));
4208 Ops.push_back(N->getOperand(4));
4209 Ops.push_back(Chain);
4211 case NVPTXISD::Suld2DArrayV2I64Trap:
4212 Opc = NVPTX::SULD_2D_ARRAY_V2I64_TRAP;
4213 Ops.push_back(TexHandle);
4214 Ops.push_back(N->getOperand(2));
4215 Ops.push_back(N->getOperand(3));
4216 Ops.push_back(N->getOperand(4));
4217 Ops.push_back(Chain);
4219 case NVPTXISD::Suld2DArrayV4I8Trap:
4220 Opc = NVPTX::SULD_2D_ARRAY_V4I8_TRAP;
4221 Ops.push_back(TexHandle);
4222 Ops.push_back(N->getOperand(2));
4223 Ops.push_back(N->getOperand(3));
4224 Ops.push_back(N->getOperand(4));
4225 Ops.push_back(Chain);
4227 case NVPTXISD::Suld2DArrayV4I16Trap:
4228 Opc = NVPTX::SULD_2D_ARRAY_V4I16_TRAP;
4229 Ops.push_back(TexHandle);
4230 Ops.push_back(N->getOperand(2));
4231 Ops.push_back(N->getOperand(3));
4232 Ops.push_back(N->getOperand(4));
4233 Ops.push_back(Chain);
4235 case NVPTXISD::Suld2DArrayV4I32Trap:
4236 Opc = NVPTX::SULD_2D_ARRAY_V4I32_TRAP;
4237 Ops.push_back(TexHandle);
4238 Ops.push_back(N->getOperand(2));
4239 Ops.push_back(N->getOperand(3));
4240 Ops.push_back(N->getOperand(4));
4241 Ops.push_back(Chain);
4243 case NVPTXISD::Suld3DI8Trap:
4244 Opc = NVPTX::SULD_3D_I8_TRAP;
4245 Ops.push_back(TexHandle);
4246 Ops.push_back(N->getOperand(2));
4247 Ops.push_back(N->getOperand(3));
4248 Ops.push_back(N->getOperand(4));
4249 Ops.push_back(Chain);
4251 case NVPTXISD::Suld3DI16Trap:
4252 Opc = NVPTX::SULD_3D_I16_TRAP;
4253 Ops.push_back(TexHandle);
4254 Ops.push_back(N->getOperand(2));
4255 Ops.push_back(N->getOperand(3));
4256 Ops.push_back(N->getOperand(4));
4257 Ops.push_back(Chain);
4259 case NVPTXISD::Suld3DI32Trap:
4260 Opc = NVPTX::SULD_3D_I32_TRAP;
4261 Ops.push_back(TexHandle);
4262 Ops.push_back(N->getOperand(2));
4263 Ops.push_back(N->getOperand(3));
4264 Ops.push_back(N->getOperand(4));
4265 Ops.push_back(Chain);
4267 case NVPTXISD::Suld3DI64Trap:
4268 Opc = NVPTX::SULD_3D_I64_TRAP;
4269 Ops.push_back(TexHandle);
4270 Ops.push_back(N->getOperand(2));
4271 Ops.push_back(N->getOperand(3));
4272 Ops.push_back(N->getOperand(4));
4273 Ops.push_back(Chain);
4275 case NVPTXISD::Suld3DV2I8Trap:
4276 Opc = NVPTX::SULD_3D_V2I8_TRAP;
4277 Ops.push_back(TexHandle);
4278 Ops.push_back(N->getOperand(2));
4279 Ops.push_back(N->getOperand(3));
4280 Ops.push_back(N->getOperand(4));
4281 Ops.push_back(Chain);
4283 case NVPTXISD::Suld3DV2I16Trap:
4284 Opc = NVPTX::SULD_3D_V2I16_TRAP;
4285 Ops.push_back(TexHandle);
4286 Ops.push_back(N->getOperand(2));
4287 Ops.push_back(N->getOperand(3));
4288 Ops.push_back(N->getOperand(4));
4289 Ops.push_back(Chain);
4291 case NVPTXISD::Suld3DV2I32Trap:
4292 Opc = NVPTX::SULD_3D_V2I32_TRAP;
4293 Ops.push_back(TexHandle);
4294 Ops.push_back(N->getOperand(2));
4295 Ops.push_back(N->getOperand(3));
4296 Ops.push_back(N->getOperand(4));
4297 Ops.push_back(Chain);
4299 case NVPTXISD::Suld3DV2I64Trap:
4300 Opc = NVPTX::SULD_3D_V2I64_TRAP;
4301 Ops.push_back(TexHandle);
4302 Ops.push_back(N->getOperand(2));
4303 Ops.push_back(N->getOperand(3));
4304 Ops.push_back(N->getOperand(4));
4305 Ops.push_back(Chain);
4307 case NVPTXISD::Suld3DV4I8Trap:
4308 Opc = NVPTX::SULD_3D_V4I8_TRAP;
4309 Ops.push_back(TexHandle);
4310 Ops.push_back(N->getOperand(2));
4311 Ops.push_back(N->getOperand(3));
4312 Ops.push_back(N->getOperand(4));
4313 Ops.push_back(Chain);
4315 case NVPTXISD::Suld3DV4I16Trap:
4316 Opc = NVPTX::SULD_3D_V4I16_TRAP;
4317 Ops.push_back(TexHandle);
4318 Ops.push_back(N->getOperand(2));
4319 Ops.push_back(N->getOperand(3));
4320 Ops.push_back(N->getOperand(4));
4321 Ops.push_back(Chain);
4323 case NVPTXISD::Suld3DV4I32Trap:
4324 Opc = NVPTX::SULD_3D_V4I32_TRAP;
4325 Ops.push_back(TexHandle);
4326 Ops.push_back(N->getOperand(2));
4327 Ops.push_back(N->getOperand(3));
4328 Ops.push_back(N->getOperand(4));
4329 Ops.push_back(Chain);
4331 case NVPTXISD::Suld1DI8Zero:
4332 Opc = NVPTX::SULD_1D_I8_ZERO;
4333 Ops.push_back(TexHandle);
4334 Ops.push_back(N->getOperand(2));
4335 Ops.push_back(Chain);
4337 case NVPTXISD::Suld1DI16Zero:
4338 Opc = NVPTX::SULD_1D_I16_ZERO;
4339 Ops.push_back(TexHandle);
4340 Ops.push_back(N->getOperand(2));
4341 Ops.push_back(Chain);
4343 case NVPTXISD::Suld1DI32Zero:
4344 Opc = NVPTX::SULD_1D_I32_ZERO;
4345 Ops.push_back(TexHandle);
4346 Ops.push_back(N->getOperand(2));
4347 Ops.push_back(Chain);
4349 case NVPTXISD::Suld1DI64Zero:
4350 Opc = NVPTX::SULD_1D_I64_ZERO;
4351 Ops.push_back(TexHandle);
4352 Ops.push_back(N->getOperand(2));
4353 Ops.push_back(Chain);
4355 case NVPTXISD::Suld1DV2I8Zero:
4356 Opc = NVPTX::SULD_1D_V2I8_ZERO;
4357 Ops.push_back(TexHandle);
4358 Ops.push_back(N->getOperand(2));
4359 Ops.push_back(Chain);
4361 case NVPTXISD::Suld1DV2I16Zero:
4362 Opc = NVPTX::SULD_1D_V2I16_ZERO;
4363 Ops.push_back(TexHandle);
4364 Ops.push_back(N->getOperand(2));
4365 Ops.push_back(Chain);
4367 case NVPTXISD::Suld1DV2I32Zero:
4368 Opc = NVPTX::SULD_1D_V2I32_ZERO;
4369 Ops.push_back(TexHandle);
4370 Ops.push_back(N->getOperand(2));
4371 Ops.push_back(Chain);
4373 case NVPTXISD::Suld1DV2I64Zero:
4374 Opc = NVPTX::SULD_1D_V2I64_ZERO;
4375 Ops.push_back(TexHandle);
4376 Ops.push_back(N->getOperand(2));
4377 Ops.push_back(Chain);
4379 case NVPTXISD::Suld1DV4I8Zero:
4380 Opc = NVPTX::SULD_1D_V4I8_ZERO;
4381 Ops.push_back(TexHandle);
4382 Ops.push_back(N->getOperand(2));
4383 Ops.push_back(Chain);
4385 case NVPTXISD::Suld1DV4I16Zero:
4386 Opc = NVPTX::SULD_1D_V4I16_ZERO;
4387 Ops.push_back(TexHandle);
4388 Ops.push_back(N->getOperand(2));
4389 Ops.push_back(Chain);
4391 case NVPTXISD::Suld1DV4I32Zero:
4392 Opc = NVPTX::SULD_1D_V4I32_ZERO;
4393 Ops.push_back(TexHandle);
4394 Ops.push_back(N->getOperand(2));
4395 Ops.push_back(Chain);
4397 case NVPTXISD::Suld1DArrayI8Zero:
4398 Opc = NVPTX::SULD_1D_ARRAY_I8_ZERO;
4399 Ops.push_back(TexHandle);
4400 Ops.push_back(N->getOperand(2));
4401 Ops.push_back(N->getOperand(3));
4402 Ops.push_back(Chain);
4404 case NVPTXISD::Suld1DArrayI16Zero:
4405 Opc = NVPTX::SULD_1D_ARRAY_I16_ZERO;
4406 Ops.push_back(TexHandle);
4407 Ops.push_back(N->getOperand(2));
4408 Ops.push_back(N->getOperand(3));
4409 Ops.push_back(Chain);
4411 case NVPTXISD::Suld1DArrayI32Zero:
4412 Opc = NVPTX::SULD_1D_ARRAY_I32_ZERO;
4413 Ops.push_back(TexHandle);
4414 Ops.push_back(N->getOperand(2));
4415 Ops.push_back(N->getOperand(3));
4416 Ops.push_back(Chain);
4418 case NVPTXISD::Suld1DArrayI64Zero:
4419 Opc = NVPTX::SULD_1D_ARRAY_I64_ZERO;
4420 Ops.push_back(TexHandle);
4421 Ops.push_back(N->getOperand(2));
4422 Ops.push_back(N->getOperand(3));
4423 Ops.push_back(Chain);
4425 case NVPTXISD::Suld1DArrayV2I8Zero:
4426 Opc = NVPTX::SULD_1D_ARRAY_V2I8_ZERO;
4427 Ops.push_back(TexHandle);
4428 Ops.push_back(N->getOperand(2));
4429 Ops.push_back(N->getOperand(3));
4430 Ops.push_back(Chain);
4432 case NVPTXISD::Suld1DArrayV2I16Zero:
4433 Opc = NVPTX::SULD_1D_ARRAY_V2I16_ZERO;
4434 Ops.push_back(TexHandle);
4435 Ops.push_back(N->getOperand(2));
4436 Ops.push_back(N->getOperand(3));
4437 Ops.push_back(Chain);
4439 case NVPTXISD::Suld1DArrayV2I32Zero:
4440 Opc = NVPTX::SULD_1D_ARRAY_V2I32_ZERO;
4441 Ops.push_back(TexHandle);
4442 Ops.push_back(N->getOperand(2));
4443 Ops.push_back(N->getOperand(3));
4444 Ops.push_back(Chain);
4446 case NVPTXISD::Suld1DArrayV2I64Zero:
4447 Opc = NVPTX::SULD_1D_ARRAY_V2I64_ZERO;
4448 Ops.push_back(TexHandle);
4449 Ops.push_back(N->getOperand(2));
4450 Ops.push_back(N->getOperand(3));
4451 Ops.push_back(Chain);
4453 case NVPTXISD::Suld1DArrayV4I8Zero:
4454 Opc = NVPTX::SULD_1D_ARRAY_V4I8_ZERO;
4455 Ops.push_back(TexHandle);
4456 Ops.push_back(N->getOperand(2));
4457 Ops.push_back(N->getOperand(3));
4458 Ops.push_back(Chain);
4460 case NVPTXISD::Suld1DArrayV4I16Zero:
4461 Opc = NVPTX::SULD_1D_ARRAY_V4I16_ZERO;
4462 Ops.push_back(TexHandle);
4463 Ops.push_back(N->getOperand(2));
4464 Ops.push_back(N->getOperand(3));
4465 Ops.push_back(Chain);
4467 case NVPTXISD::Suld1DArrayV4I32Zero:
4468 Opc = NVPTX::SULD_1D_ARRAY_V4I32_ZERO;
4469 Ops.push_back(TexHandle);
4470 Ops.push_back(N->getOperand(2));
4471 Ops.push_back(N->getOperand(3));
4472 Ops.push_back(Chain);
4474 case NVPTXISD::Suld2DI8Zero:
4475 Opc = NVPTX::SULD_2D_I8_ZERO;
4476 Ops.push_back(TexHandle);
4477 Ops.push_back(N->getOperand(2));
4478 Ops.push_back(N->getOperand(3));
4479 Ops.push_back(Chain);
4481 case NVPTXISD::Suld2DI16Zero:
4482 Opc = NVPTX::SULD_2D_I16_ZERO;
4483 Ops.push_back(TexHandle);
4484 Ops.push_back(N->getOperand(2));
4485 Ops.push_back(N->getOperand(3));
4486 Ops.push_back(Chain);
4488 case NVPTXISD::Suld2DI32Zero:
4489 Opc = NVPTX::SULD_2D_I32_ZERO;
4490 Ops.push_back(TexHandle);
4491 Ops.push_back(N->getOperand(2));
4492 Ops.push_back(N->getOperand(3));
4493 Ops.push_back(Chain);
4495 case NVPTXISD::Suld2DI64Zero:
4496 Opc = NVPTX::SULD_2D_I64_ZERO;
4497 Ops.push_back(TexHandle);
4498 Ops.push_back(N->getOperand(2));
4499 Ops.push_back(N->getOperand(3));
4500 Ops.push_back(Chain);
4502 case NVPTXISD::Suld2DV2I8Zero:
4503 Opc = NVPTX::SULD_2D_V2I8_ZERO;
4504 Ops.push_back(TexHandle);
4505 Ops.push_back(N->getOperand(2));
4506 Ops.push_back(N->getOperand(3));
4507 Ops.push_back(Chain);
4509 case NVPTXISD::Suld2DV2I16Zero:
4510 Opc = NVPTX::SULD_2D_V2I16_ZERO;
4511 Ops.push_back(TexHandle);
4512 Ops.push_back(N->getOperand(2));
4513 Ops.push_back(N->getOperand(3));
4514 Ops.push_back(Chain);
4516 case NVPTXISD::Suld2DV2I32Zero:
4517 Opc = NVPTX::SULD_2D_V2I32_ZERO;
4518 Ops.push_back(TexHandle);
4519 Ops.push_back(N->getOperand(2));
4520 Ops.push_back(N->getOperand(3));
4521 Ops.push_back(Chain);
4523 case NVPTXISD::Suld2DV2I64Zero:
4524 Opc = NVPTX::SULD_2D_V2I64_ZERO;
4525 Ops.push_back(TexHandle);
4526 Ops.push_back(N->getOperand(2));
4527 Ops.push_back(N->getOperand(3));
4528 Ops.push_back(Chain);
4530 case NVPTXISD::Suld2DV4I8Zero:
4531 Opc = NVPTX::SULD_2D_V4I8_ZERO;
4532 Ops.push_back(TexHandle);
4533 Ops.push_back(N->getOperand(2));
4534 Ops.push_back(N->getOperand(3));
4535 Ops.push_back(Chain);
4537 case NVPTXISD::Suld2DV4I16Zero:
4538 Opc = NVPTX::SULD_2D_V4I16_ZERO;
4539 Ops.push_back(TexHandle);
4540 Ops.push_back(N->getOperand(2));
4541 Ops.push_back(N->getOperand(3));
4542 Ops.push_back(Chain);
4544 case NVPTXISD::Suld2DV4I32Zero:
4545 Opc = NVPTX::SULD_2D_V4I32_ZERO;
4546 Ops.push_back(TexHandle);
4547 Ops.push_back(N->getOperand(2));
4548 Ops.push_back(N->getOperand(3));
4549 Ops.push_back(Chain);
4551 case NVPTXISD::Suld2DArrayI8Zero:
4552 Opc = NVPTX::SULD_2D_ARRAY_I8_ZERO;
4553 Ops.push_back(TexHandle);
4554 Ops.push_back(N->getOperand(2));
4555 Ops.push_back(N->getOperand(3));
4556 Ops.push_back(N->getOperand(4));
4557 Ops.push_back(Chain);
4559 case NVPTXISD::Suld2DArrayI16Zero:
4560 Opc = NVPTX::SULD_2D_ARRAY_I16_ZERO;
4561 Ops.push_back(TexHandle);
4562 Ops.push_back(N->getOperand(2));
4563 Ops.push_back(N->getOperand(3));
4564 Ops.push_back(N->getOperand(4));
4565 Ops.push_back(Chain);
4567 case NVPTXISD::Suld2DArrayI32Zero:
4568 Opc = NVPTX::SULD_2D_ARRAY_I32_ZERO;
4569 Ops.push_back(TexHandle);
4570 Ops.push_back(N->getOperand(2));
4571 Ops.push_back(N->getOperand(3));
4572 Ops.push_back(N->getOperand(4));
4573 Ops.push_back(Chain);
4575 case NVPTXISD::Suld2DArrayI64Zero:
4576 Opc = NVPTX::SULD_2D_ARRAY_I64_ZERO;
4577 Ops.push_back(TexHandle);
4578 Ops.push_back(N->getOperand(2));
4579 Ops.push_back(N->getOperand(3));
4580 Ops.push_back(N->getOperand(4));
4581 Ops.push_back(Chain);
4583 case NVPTXISD::Suld2DArrayV2I8Zero:
4584 Opc = NVPTX::SULD_2D_ARRAY_V2I8_ZERO;
4585 Ops.push_back(TexHandle);
4586 Ops.push_back(N->getOperand(2));
4587 Ops.push_back(N->getOperand(3));
4588 Ops.push_back(N->getOperand(4));
4589 Ops.push_back(Chain);
4591 case NVPTXISD::Suld2DArrayV2I16Zero:
4592 Opc = NVPTX::SULD_2D_ARRAY_V2I16_ZERO;
4593 Ops.push_back(TexHandle);
4594 Ops.push_back(N->getOperand(2));
4595 Ops.push_back(N->getOperand(3));
4596 Ops.push_back(N->getOperand(4));
4597 Ops.push_back(Chain);
4599 case NVPTXISD::Suld2DArrayV2I32Zero:
4600 Opc = NVPTX::SULD_2D_ARRAY_V2I32_ZERO;
4601 Ops.push_back(TexHandle);
4602 Ops.push_back(N->getOperand(2));
4603 Ops.push_back(N->getOperand(3));
4604 Ops.push_back(N->getOperand(4));
4605 Ops.push_back(Chain);
4607 case NVPTXISD::Suld2DArrayV2I64Zero:
4608 Opc = NVPTX::SULD_2D_ARRAY_V2I64_ZERO;
4609 Ops.push_back(TexHandle);
4610 Ops.push_back(N->getOperand(2));
4611 Ops.push_back(N->getOperand(3));
4612 Ops.push_back(N->getOperand(4));
4613 Ops.push_back(Chain);
4615 case NVPTXISD::Suld2DArrayV4I8Zero:
4616 Opc = NVPTX::SULD_2D_ARRAY_V4I8_ZERO;
4617 Ops.push_back(TexHandle);
4618 Ops.push_back(N->getOperand(2));
4619 Ops.push_back(N->getOperand(3));
4620 Ops.push_back(N->getOperand(4));
4621 Ops.push_back(Chain);
4623 case NVPTXISD::Suld2DArrayV4I16Zero:
4624 Opc = NVPTX::SULD_2D_ARRAY_V4I16_ZERO;
4625 Ops.push_back(TexHandle);
4626 Ops.push_back(N->getOperand(2));
4627 Ops.push_back(N->getOperand(3));
4628 Ops.push_back(N->getOperand(4));
4629 Ops.push_back(Chain);
4631 case NVPTXISD::Suld2DArrayV4I32Zero:
4632 Opc = NVPTX::SULD_2D_ARRAY_V4I32_ZERO;
4633 Ops.push_back(TexHandle);
4634 Ops.push_back(N->getOperand(2));
4635 Ops.push_back(N->getOperand(3));
4636 Ops.push_back(N->getOperand(4));
4637 Ops.push_back(Chain);
4639 case NVPTXISD::Suld3DI8Zero:
4640 Opc = NVPTX::SULD_3D_I8_ZERO;
4641 Ops.push_back(TexHandle);
4642 Ops.push_back(N->getOperand(2));
4643 Ops.push_back(N->getOperand(3));
4644 Ops.push_back(N->getOperand(4));
4645 Ops.push_back(Chain);
4647 case NVPTXISD::Suld3DI16Zero:
4648 Opc = NVPTX::SULD_3D_I16_ZERO;
4649 Ops.push_back(TexHandle);
4650 Ops.push_back(N->getOperand(2));
4651 Ops.push_back(N->getOperand(3));
4652 Ops.push_back(N->getOperand(4));
4653 Ops.push_back(Chain);
4655 case NVPTXISD::Suld3DI32Zero:
4656 Opc = NVPTX::SULD_3D_I32_ZERO;
4657 Ops.push_back(TexHandle);
4658 Ops.push_back(N->getOperand(2));
4659 Ops.push_back(N->getOperand(3));
4660 Ops.push_back(N->getOperand(4));
4661 Ops.push_back(Chain);
4663 case NVPTXISD::Suld3DI64Zero:
4664 Opc = NVPTX::SULD_3D_I64_ZERO;
4665 Ops.push_back(TexHandle);
4666 Ops.push_back(N->getOperand(2));
4667 Ops.push_back(N->getOperand(3));
4668 Ops.push_back(N->getOperand(4));
4669 Ops.push_back(Chain);
4671 case NVPTXISD::Suld3DV2I8Zero:
4672 Opc = NVPTX::SULD_3D_V2I8_ZERO;
4673 Ops.push_back(TexHandle);
4674 Ops.push_back(N->getOperand(2));
4675 Ops.push_back(N->getOperand(3));
4676 Ops.push_back(N->getOperand(4));
4677 Ops.push_back(Chain);
4679 case NVPTXISD::Suld3DV2I16Zero:
4680 Opc = NVPTX::SULD_3D_V2I16_ZERO;
4681 Ops.push_back(TexHandle);
4682 Ops.push_back(N->getOperand(2));
4683 Ops.push_back(N->getOperand(3));
4684 Ops.push_back(N->getOperand(4));
4685 Ops.push_back(Chain);
4687 case NVPTXISD::Suld3DV2I32Zero:
4688 Opc = NVPTX::SULD_3D_V2I32_ZERO;
4689 Ops.push_back(TexHandle);
4690 Ops.push_back(N->getOperand(2));
4691 Ops.push_back(N->getOperand(3));
4692 Ops.push_back(N->getOperand(4));
4693 Ops.push_back(Chain);
4695 case NVPTXISD::Suld3DV2I64Zero:
4696 Opc = NVPTX::SULD_3D_V2I64_ZERO;
4697 Ops.push_back(TexHandle);
4698 Ops.push_back(N->getOperand(2));
4699 Ops.push_back(N->getOperand(3));
4700 Ops.push_back(N->getOperand(4));
4701 Ops.push_back(Chain);
4703 case NVPTXISD::Suld3DV4I8Zero:
4704 Opc = NVPTX::SULD_3D_V4I8_ZERO;
4705 Ops.push_back(TexHandle);
4706 Ops.push_back(N->getOperand(2));
4707 Ops.push_back(N->getOperand(3));
4708 Ops.push_back(N->getOperand(4));
4709 Ops.push_back(Chain);
4711 case NVPTXISD::Suld3DV4I16Zero:
4712 Opc = NVPTX::SULD_3D_V4I16_ZERO;
4713 Ops.push_back(TexHandle);
4714 Ops.push_back(N->getOperand(2));
4715 Ops.push_back(N->getOperand(3));
4716 Ops.push_back(N->getOperand(4));
4717 Ops.push_back(Chain);
4719 case NVPTXISD::Suld3DV4I32Zero:
4720 Opc = NVPTX::SULD_3D_V4I32_ZERO;
4721 Ops.push_back(TexHandle);
4722 Ops.push_back(N->getOperand(2));
4723 Ops.push_back(N->getOperand(3));
4724 Ops.push_back(N->getOperand(4));
4725 Ops.push_back(Chain);
4728 Ret = CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);
4733 /// SelectBFE - Look for instruction sequences that can be made more efficient
4734 /// by using the 'bfe' (bit-field extract) PTX instruction
4735 SDNode *NVPTXDAGToDAGISel::SelectBFE(SDNode *N) {
4737 SDValue LHS = N->getOperand(0);
4738 SDValue RHS = N->getOperand(1);
4742 bool IsSigned = false;
4744 if (N->getOpcode() == ISD::AND) {
4745 // Canonicalize the operands
4746 // We want 'and %val, %mask'
4747 if (isa<ConstantSDNode>(LHS) && !isa<ConstantSDNode>(RHS)) {
4748 std::swap(LHS, RHS);
4751 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(RHS);
4753 // We need a constant mask on the RHS of the AND
4757 // Extract the mask bits
4758 uint64_t MaskVal = Mask->getZExtValue();
4759 if (!isMask_64(MaskVal)) {
4760 // We *could* handle shifted masks here, but doing so would require an
4761 // 'and' operation to fix up the low-order bits so we would trade
4762 // shr+and for bfe+and, which has the same throughput
4766 // How many bits are in our mask?
4767 uint64_t NumBits = countTrailingOnes(MaskVal);
4768 Len = CurDAG->getTargetConstant(NumBits, DL, MVT::i32);
4770 if (LHS.getOpcode() == ISD::SRL || LHS.getOpcode() == ISD::SRA) {
4771 // We have a 'srl/and' pair, extract the effective start bit and length
4772 Val = LHS.getNode()->getOperand(0);
4773 Start = LHS.getNode()->getOperand(1);
4774 ConstantSDNode *StartConst = dyn_cast<ConstantSDNode>(Start);
4776 uint64_t StartVal = StartConst->getZExtValue();
4777 // How many "good" bits do we have left? "good" is defined here as bits
4778 // that exist in the original value, not shifted in.
4779 uint64_t GoodBits = Start.getValueType().getSizeInBits() - StartVal;
4780 if (NumBits > GoodBits) {
4781 // Do not handle the case where bits have been shifted in. In theory
4782 // we could handle this, but the cost is likely higher than just
4783 // emitting the srl/and pair.
4786 Start = CurDAG->getTargetConstant(StartVal, DL, MVT::i32);
4788 // Do not handle the case where the shift amount (can be zero if no srl
4789 // was found) is not constant. We could handle this case, but it would
4790 // require run-time logic that would be more expensive than just
4791 // emitting the srl/and pair.
4795 // Do not handle the case where the LHS of the and is not a shift. While
4796 // it would be trivial to handle this case, it would just transform
4797 // 'and' -> 'bfe', but 'and' has higher-throughput.
4800 } else if (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) {
4801 if (LHS->getOpcode() == ISD::AND) {
4802 ConstantSDNode *ShiftCnst = dyn_cast<ConstantSDNode>(RHS);
4804 // Shift amount must be constant
4808 uint64_t ShiftAmt = ShiftCnst->getZExtValue();
4810 SDValue AndLHS = LHS->getOperand(0);
4811 SDValue AndRHS = LHS->getOperand(1);
4813 // Canonicalize the AND to have the mask on the RHS
4814 if (isa<ConstantSDNode>(AndLHS)) {
4815 std::swap(AndLHS, AndRHS);
4818 ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(AndRHS);
4820 // Mask must be constant
4824 uint64_t MaskVal = MaskCnst->getZExtValue();
4827 if (isMask_64(MaskVal)) {
4829 // The number of bits in the result bitfield will be the number of
4830 // trailing ones (the AND) minus the number of bits we shift off
4831 NumBits = countTrailingOnes(MaskVal) - ShiftAmt;
4832 } else if (isShiftedMask_64(MaskVal)) {
4833 NumZeros = countTrailingZeros(MaskVal);
4834 unsigned NumOnes = countTrailingOnes(MaskVal >> NumZeros);
4835 // The number of bits in the result bitfield will be the number of
4836 // trailing zeros plus the number of set bits in the mask minus the
4837 // number of bits we shift off
4838 NumBits = NumZeros + NumOnes - ShiftAmt;
4840 // This is not a mask we can handle
4844 if (ShiftAmt < NumZeros) {
4845 // Handling this case would require extra logic that would make this
4846 // transformation non-profitable
4851 Start = CurDAG->getTargetConstant(ShiftAmt, DL, MVT::i32);
4852 Len = CurDAG->getTargetConstant(NumBits, DL, MVT::i32);
4853 } else if (LHS->getOpcode() == ISD::SHL) {
4854 // Here, we have a pattern like:
4856 // (sra (shl val, NN), MM)
4858 // (srl (shl val, NN), MM)
4860 // If MM >= NN, we can efficiently optimize this with bfe
4861 Val = LHS->getOperand(0);
4863 SDValue ShlRHS = LHS->getOperand(1);
4864 ConstantSDNode *ShlCnst = dyn_cast<ConstantSDNode>(ShlRHS);
4866 // Shift amount must be constant
4869 uint64_t InnerShiftAmt = ShlCnst->getZExtValue();
4871 SDValue ShrRHS = RHS;
4872 ConstantSDNode *ShrCnst = dyn_cast<ConstantSDNode>(ShrRHS);
4874 // Shift amount must be constant
4877 uint64_t OuterShiftAmt = ShrCnst->getZExtValue();
4879 // To avoid extra codegen and be profitable, we need Outer >= Inner
4880 if (OuterShiftAmt < InnerShiftAmt) {
4884 // If the outer shift is more than the type size, we have no bitfield to
4885 // extract (since we also check that the inner shift is <= the outer shift
4886 // then this also implies that the inner shift is < the type size)
4887 if (OuterShiftAmt >= Val.getValueType().getSizeInBits()) {
4892 CurDAG->getTargetConstant(OuterShiftAmt - InnerShiftAmt, DL, MVT::i32);
4894 CurDAG->getTargetConstant(Val.getValueType().getSizeInBits() -
4895 OuterShiftAmt, DL, MVT::i32);
4897 if (N->getOpcode() == ISD::SRA) {
4898 // If we have a arithmetic right shift, we need to use the signed bfe
4913 // For the BFE operations we form here from "and" and "srl", always use the
4914 // unsigned variants.
4915 if (Val.getValueType() == MVT::i32) {
4917 Opc = NVPTX::BFE_S32rii;
4919 Opc = NVPTX::BFE_U32rii;
4921 } else if (Val.getValueType() == MVT::i64) {
4923 Opc = NVPTX::BFE_S64rii;
4925 Opc = NVPTX::BFE_U64rii;
4928 // We cannot handle this type
4936 return CurDAG->getMachineNode(Opc, DL, N->getVTList(), Ops);
4939 // SelectDirectAddr - Match a direct address for DAG.
4940 // A direct address could be a globaladdress or externalsymbol.
4941 bool NVPTXDAGToDAGISel::SelectDirectAddr(SDValue N, SDValue &Address) {
4942 // Return true if TGA or ES.
4943 if (N.getOpcode() == ISD::TargetGlobalAddress ||
4944 N.getOpcode() == ISD::TargetExternalSymbol) {
4948 if (N.getOpcode() == NVPTXISD::Wrapper) {
4949 Address = N.getOperand(0);
4952 if (N.getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
4953 unsigned IID = cast<ConstantSDNode>(N.getOperand(0))->getZExtValue();
4954 if (IID == Intrinsic::nvvm_ptr_gen_to_param)
4955 if (N.getOperand(1).getOpcode() == NVPTXISD::MoveParam)
4956 return (SelectDirectAddr(N.getOperand(1).getOperand(0), Address));
4962 bool NVPTXDAGToDAGISel::SelectADDRsi_imp(
4963 SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) {
4964 if (Addr.getOpcode() == ISD::ADD) {
4965 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
4966 SDValue base = Addr.getOperand(0);
4967 if (SelectDirectAddr(base, Base)) {
4968 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(OpNode),
4978 bool NVPTXDAGToDAGISel::SelectADDRsi(SDNode *OpNode, SDValue Addr,
4979 SDValue &Base, SDValue &Offset) {
4980 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i32);
4984 bool NVPTXDAGToDAGISel::SelectADDRsi64(SDNode *OpNode, SDValue Addr,
4985 SDValue &Base, SDValue &Offset) {
4986 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i64);
4990 bool NVPTXDAGToDAGISel::SelectADDRri_imp(
4991 SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) {
4992 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
4993 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
4994 Offset = CurDAG->getTargetConstant(0, SDLoc(OpNode), mvt);
4997 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
4998 Addr.getOpcode() == ISD::TargetGlobalAddress)
4999 return false; // direct calls.
5001 if (Addr.getOpcode() == ISD::ADD) {
5002 if (SelectDirectAddr(Addr.getOperand(0), Addr)) {
5005 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
5006 if (FrameIndexSDNode *FIN =
5007 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
5008 // Constant offset from frame ref.
5009 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
5011 Base = Addr.getOperand(0);
5012 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(OpNode),
5021 bool NVPTXDAGToDAGISel::SelectADDRri(SDNode *OpNode, SDValue Addr,
5022 SDValue &Base, SDValue &Offset) {
5023 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i32);
5027 bool NVPTXDAGToDAGISel::SelectADDRri64(SDNode *OpNode, SDValue Addr,
5028 SDValue &Base, SDValue &Offset) {
5029 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i64);
5032 bool NVPTXDAGToDAGISel::ChkMemSDNodeAddressSpace(SDNode *N,
5033 unsigned int spN) const {
5034 const Value *Src = nullptr;
5035 if (MemSDNode *mN = dyn_cast<MemSDNode>(N)) {
5036 if (spN == 0 && mN->getMemOperand()->getPseudoValue())
5038 Src = mN->getMemOperand()->getValue();
5042 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
5043 return (PT->getAddressSpace() == spN);
5047 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
5048 /// inline asm expressions.
5049 bool NVPTXDAGToDAGISel::SelectInlineAsmMemoryOperand(
5050 const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
5052 switch (ConstraintID) {
5055 case InlineAsm::Constraint_m: // memory
5056 if (SelectDirectAddr(Op, Op0)) {
5057 OutOps.push_back(Op0);
5058 OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
5061 if (SelectADDRri(Op.getNode(), Op, Op0, Op1)) {
5062 OutOps.push_back(Op0);
5063 OutOps.push_back(Op1);