1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implements the info about Mips target spec.
12 //===----------------------------------------------------------------------===//
15 #include "MipsTargetMachine.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/Support/TargetRegistry.h"
20 extern "C" void LLVMInitializeMipsTarget() {
21 // Register the target.
22 RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
23 RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
24 RegisterTargetMachine<Mips64ebTargetMachine> A(TheMips64Target);
25 RegisterTargetMachine<Mips64elTargetMachine> B(TheMips64elTarget);
28 // DataLayout --> Big-endian, 32-bit pointer/ABI/alignment
29 // The stack is always 8 byte aligned
30 // On function prologue, the stack is created by decrementing
31 // its pointer. Once decremented, all references are done with positive
32 // offset from the stack/frame pointer, using StackGrowsUp enables
33 // an easier handling.
34 // Using CodeModel::Large enables different CALL behavior.
36 MipsTargetMachine(const Target &T, StringRef TT,
37 StringRef CPU, StringRef FS,
38 Reloc::Model RM, CodeModel::Model CM,
41 LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
42 Subtarget(TT, CPU, FS, isLittle),
44 (Subtarget.isABI_N64() ?
45 "e-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" :
46 "e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
47 (Subtarget.isABI_N64() ?
48 "E-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" :
49 "E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
51 FrameLowering(Subtarget),
52 TLInfo(*this), TSInfo(*this), JITInfo() {
56 MipsebTargetMachine(const Target &T, StringRef TT,
57 StringRef CPU, StringRef FS,
58 Reloc::Model RM, CodeModel::Model CM,
59 CodeGenOpt::Level OL) :
60 MipsTargetMachine(T, TT, CPU, FS, RM, CM, OL, false) {}
63 MipselTargetMachine(const Target &T, StringRef TT,
64 StringRef CPU, StringRef FS,
65 Reloc::Model RM, CodeModel::Model CM,
66 CodeGenOpt::Level OL) :
67 MipsTargetMachine(T, TT, CPU, FS, RM, CM, OL, true) {}
69 Mips64ebTargetMachine::
70 Mips64ebTargetMachine(const Target &T, StringRef TT,
71 StringRef CPU, StringRef FS,
72 Reloc::Model RM, CodeModel::Model CM,
73 CodeGenOpt::Level OL) :
74 MipsTargetMachine(T, TT, CPU, FS, RM, CM, OL, false) {}
76 Mips64elTargetMachine::
77 Mips64elTargetMachine(const Target &T, StringRef TT,
78 StringRef CPU, StringRef FS,
79 Reloc::Model RM, CodeModel::Model CM,
80 CodeGenOpt::Level OL) :
81 MipsTargetMachine(T, TT, CPU, FS, RM, CM, OL, true) {}
83 // Install an instruction selector pass using
84 // the ISelDag to gen Mips code.
85 bool MipsTargetMachine::
86 addInstSelector(PassManagerBase &PM)
88 PM.add(createMipsISelDag(*this));
92 // Implemented by targets that want to run passes immediately before
93 // machine code is emitted. return true if -print-machineinstrs should
94 // print out the code after the passes.
95 bool MipsTargetMachine::
96 addPreEmitPass(PassManagerBase &PM)
98 PM.add(createMipsDelaySlotFillerPass(*this));
102 bool MipsTargetMachine::
103 addPreRegAlloc(PassManagerBase &PM) {
104 // Do not restore $gp if target is Mips64.
105 // In N32/64, $gp is a callee-saved register.
106 if (!Subtarget.hasMips64())
107 PM.add(createMipsEmitGPRestorePass(*this));
111 bool MipsTargetMachine::
112 addPostRegAlloc(PassManagerBase &PM) {
113 PM.add(createMipsExpandPseudoPass(*this));
117 bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM,
118 JITCodeEmitter &JCE) {
119 // Machine code emitter pass for Mips.
120 PM.add(createMipsJITCodeEmitterPass(*this, JCE));