1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implements the info about Mips target spec.
12 //===----------------------------------------------------------------------===//
14 #include "MipsTargetMachine.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/Support/TargetRegistry.h"
21 extern "C" void LLVMInitializeMipsTarget() {
22 // Register the target.
23 RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
24 RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
25 RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target);
26 RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
29 // DataLayout --> Big-endian, 32-bit pointer/ABI/alignment
30 // The stack is always 8 byte aligned
31 // On function prologue, the stack is created by decrementing
32 // its pointer. Once decremented, all references are done with positive
33 // offset from the stack/frame pointer, using StackGrowsUp enables
34 // an easier handling.
35 // Using CodeModel::Large enables different CALL behavior.
37 MipsTargetMachine(const Target &T, StringRef TT,
38 StringRef CPU, StringRef FS, const TargetOptions &Options,
39 Reloc::Model RM, CodeModel::Model CM,
42 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
43 Subtarget(TT, CPU, FS, isLittle),
45 (Subtarget.isABI_N64() ?
46 "e-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" :
47 "e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
48 (Subtarget.isABI_N64() ?
49 "E-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" :
50 "E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
52 FrameLowering(Subtarget),
53 TLInfo(*this), TSInfo(*this), JITInfo() {
56 void MipsebTargetMachine::anchor() { }
59 MipsebTargetMachine(const Target &T, StringRef TT,
60 StringRef CPU, StringRef FS, const TargetOptions &Options,
61 Reloc::Model RM, CodeModel::Model CM,
63 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
65 void MipselTargetMachine::anchor() { }
68 MipselTargetMachine(const Target &T, StringRef TT,
69 StringRef CPU, StringRef FS, const TargetOptions &Options,
70 Reloc::Model RM, CodeModel::Model CM,
72 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
75 /// Mips Code Generator Pass Configuration Options.
76 class MipsPassConfig : public TargetPassConfig {
78 MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
79 : TargetPassConfig(TM, PM) {}
81 MipsTargetMachine &getMipsTargetMachine() const {
82 return getTM<MipsTargetMachine>();
85 const MipsSubtarget &getMipsSubtarget() const {
86 return *getMipsTargetMachine().getSubtargetImpl();
89 virtual bool addInstSelector();
90 virtual bool addPreEmitPass();
94 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
95 return new MipsPassConfig(this, PM);
98 // Install an instruction selector pass using
99 // the ISelDag to gen Mips code.
100 bool MipsPassConfig::addInstSelector() {
101 addPass(createMipsISelDag(getMipsTargetMachine()));
105 // Implemented by targets that want to run passes immediately before
106 // machine code is emitted. return true if -print-machineinstrs should
107 // print out the code after the passes.
108 bool MipsPassConfig::addPreEmitPass() {
109 MipsTargetMachine &TM = getMipsTargetMachine();
110 addPass(createMipsDelaySlotFillerPass(TM));
112 // NOTE: long branch has not been implemented for mips16.
113 if (TM.getSubtarget<MipsSubtarget>().hasStandardEncoding())
114 addPass(createMipsLongBranchPass(TM));
119 bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM,
120 JITCodeEmitter &JCE) {
121 // Machine code emitter pass for Mips.
122 PM.add(createMipsJITCodeEmitterPass(*this, JCE));