1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implements the info about Mips target spec.
12 //===----------------------------------------------------------------------===//
14 #include "MipsTargetMachine.h"
16 #include "Mips16FrameLowering.h"
17 #include "Mips16ISelDAGToDAG.h"
18 #include "Mips16ISelLowering.h"
19 #include "Mips16InstrInfo.h"
20 #include "MipsFrameLowering.h"
21 #include "MipsInstrInfo.h"
22 #include "MipsSEFrameLowering.h"
23 #include "MipsSEISelDAGToDAG.h"
24 #include "MipsSEISelLowering.h"
25 #include "MipsSEInstrInfo.h"
26 #include "MipsTargetObjectFile.h"
27 #include "llvm/Analysis/TargetTransformInfo.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/IR/LegacyPassManager.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/TargetRegistry.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Transforms/Scalar.h"
37 #define DEBUG_TYPE "mips"
39 extern "C" void LLVMInitializeMipsTarget() {
40 // Register the target.
41 RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
42 RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
43 RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target);
44 RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
47 static std::string computeDataLayout(StringRef TT, StringRef CPU,
48 const TargetOptions &Options,
52 MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options.MCOptions);
54 // There are both little and big endian mips.
62 // Pointers are 32 bit on some ABIs.
66 // 8 and 16 bit integers only need no have natural alignment, but try to
67 // align them to 32 bits. 64 bit integers have natural alignment.
68 Ret += "-i8:8:32-i16:16:32-i64:64";
70 // 32 bit registers are always available and the stack is at least 64 bit
71 // aligned. On N64 64 bit registers are also available and the stack is
73 if (ABI.IsN64() || ABI.IsN32())
74 Ret += "-n32:64-S128";
81 // On function prologue, the stack is created by decrementing
82 // its pointer. Once decremented, all references are done with positive
83 // offset from the stack/frame pointer, using StackGrowsUp enables
84 // an easier handling.
85 // Using CodeModel::Large enables different CALL behavior.
86 MipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT,
87 StringRef CPU, StringRef FS,
88 const TargetOptions &Options,
89 Reloc::Model RM, CodeModel::Model CM,
90 CodeGenOpt::Level OL, bool isLittle)
91 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
92 CPU, FS, Options, RM, CM, OL),
93 isLittle(isLittle), TLOF(make_unique<MipsTargetObjectFile>()),
94 ABI(MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options.MCOptions)),
95 Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this),
96 NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
98 Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
100 Subtarget = &DefaultSubtarget;
104 MipsTargetMachine::~MipsTargetMachine() {}
106 void MipsebTargetMachine::anchor() { }
108 MipsebTargetMachine::
109 MipsebTargetMachine(const Target &T, StringRef TT,
110 StringRef CPU, StringRef FS, const TargetOptions &Options,
111 Reloc::Model RM, CodeModel::Model CM,
112 CodeGenOpt::Level OL)
113 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
115 void MipselTargetMachine::anchor() { }
117 MipselTargetMachine::
118 MipselTargetMachine(const Target &T, StringRef TT,
119 StringRef CPU, StringRef FS, const TargetOptions &Options,
120 Reloc::Model RM, CodeModel::Model CM,
121 CodeGenOpt::Level OL)
122 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
124 const MipsSubtarget *
125 MipsTargetMachine::getSubtargetImpl(const Function &F) const {
126 Attribute CPUAttr = F.getFnAttribute("target-cpu");
127 Attribute FSAttr = F.getFnAttribute("target-features");
129 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
130 ? CPUAttr.getValueAsString().str()
132 std::string FS = !FSAttr.hasAttribute(Attribute::None)
133 ? FSAttr.getValueAsString().str()
136 !F.getFnAttribute("mips16").hasAttribute(Attribute::None);
137 bool hasNoMips16Attr =
138 !F.getFnAttribute("nomips16").hasAttribute(Attribute::None);
140 // FIXME: This is related to the code below to reset the target options,
141 // we need to know whether or not the soft float flag is set on the
142 // function before we can generate a subtarget. We also need to use
143 // it as a key for the subtarget since that can be the only difference
144 // between two functions.
145 Attribute SFAttr = F.getFnAttribute("use-soft-float");
146 bool softFloat = !SFAttr.hasAttribute(Attribute::None)
147 ? SFAttr.getValueAsString() == "true"
148 : Options.UseSoftFloat;
151 FS += FS.empty() ? "+mips16" : ",+mips16";
152 else if (hasNoMips16Attr)
153 FS += FS.empty() ? "-mips16" : ",-mips16";
155 auto &I = SubtargetMap[CPU + FS + (softFloat ? "use-soft-float=true"
156 : "use-soft-float=false")];
158 // This needs to be done before we create a new subtarget since any
159 // creation will depend on the TM and the code generation flags on the
160 // function that reside in TargetOptions.
161 resetTargetOptions(F);
162 I = llvm::make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle, *this);
167 void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
168 DEBUG(dbgs() << "resetSubtarget\n");
170 Subtarget = const_cast<MipsSubtarget *>(getSubtargetImpl(*MF->getFunction()));
171 MF->setSubtarget(Subtarget);
176 /// Mips Code Generator Pass Configuration Options.
177 class MipsPassConfig : public TargetPassConfig {
179 MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
180 : TargetPassConfig(TM, PM) {
181 // The current implementation of long branch pass requires a scratch
182 // register ($at) to be available before branch instructions. Tail merging
183 // can break this requirement, so disable it when long branch pass is
185 EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
188 MipsTargetMachine &getMipsTargetMachine() const {
189 return getTM<MipsTargetMachine>();
192 const MipsSubtarget &getMipsSubtarget() const {
193 return *getMipsTargetMachine().getSubtargetImpl();
196 void addIRPasses() override;
197 bool addInstSelector() override;
198 void addMachineSSAOptimization() override;
199 void addPreEmitPass() override;
201 void addPreRegAlloc() override;
206 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
207 return new MipsPassConfig(this, PM);
210 void MipsPassConfig::addIRPasses() {
211 TargetPassConfig::addIRPasses();
212 addPass(createAtomicExpandPass(&getMipsTargetMachine()));
213 if (getMipsSubtarget().os16())
214 addPass(createMipsOs16Pass(getMipsTargetMachine()));
215 if (getMipsSubtarget().inMips16HardFloat())
216 addPass(createMips16HardFloatPass(getMipsTargetMachine()));
218 // Install an instruction selector pass using
219 // the ISelDag to gen Mips code.
220 bool MipsPassConfig::addInstSelector() {
221 addPass(createMipsModuleISelDagPass(getMipsTargetMachine()));
222 addPass(createMips16ISelDag(getMipsTargetMachine()));
223 addPass(createMipsSEISelDag(getMipsTargetMachine()));
227 void MipsPassConfig::addMachineSSAOptimization() {
228 addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
229 TargetPassConfig::addMachineSSAOptimization();
232 void MipsPassConfig::addPreRegAlloc() {
233 if (getOptLevel() == CodeGenOpt::None)
234 addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
237 TargetIRAnalysis MipsTargetMachine::getTargetIRAnalysis() {
238 return TargetIRAnalysis([this](Function &F) {
239 if (Subtarget->allowMixed16_32()) {
240 DEBUG(errs() << "No Target Transform Info Pass Added\n");
241 // FIXME: This is no longer necessary as the TTI returned is per-function.
242 return TargetTransformInfo(getDataLayout());
245 DEBUG(errs() << "Target Transform Info Pass Added\n");
246 return TargetTransformInfo(BasicTTIImpl(this, F));
250 // Implemented by targets that want to run passes immediately before
251 // machine code is emitted. return true if -print-machineinstrs should
252 // print out the code after the passes.
253 void MipsPassConfig::addPreEmitPass() {
254 MipsTargetMachine &TM = getMipsTargetMachine();
255 addPass(createMipsDelaySlotFillerPass(TM));
256 addPass(createMipsLongBranchPass(TM));
257 addPass(createMipsConstantIslandPass(TM));