1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
15 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
17 #include "MCTargetDesc/MipsABIInfo.h"
18 #include "MipsFrameLowering.h"
19 #include "MipsISelLowering.h"
20 #include "MipsInstrInfo.h"
21 #include "MipsSelectionDAGInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/MC/MCInstrItineraries.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
28 #define GET_SUBTARGETINFO_HEADER
29 #include "MipsGenSubtargetInfo.inc"
34 class MipsTargetMachine;
36 class MipsSubtarget : public MipsGenSubtargetInfo {
37 virtual void anchor();
41 Mips1, Mips2, Mips32, Mips32r2, Mips32r6, Mips3, Mips4, Mips5, Mips64,
45 // Mips architecture version
46 MipsArchEnum MipsArchVersion;
48 // IsLittle - The target is Little Endian
51 // IsSingleFloat - The target only supports single precision float
52 // point operations. This enable the target to use all 32 32-bit
53 // floating point registers instead of only using even ones.
56 // IsFPXX - MIPS O32 modeless ABI.
59 // NoABICalls - Disable SVR4-style position-independent code.
62 // IsFP64bit - The target processor has 64-bit floating point registers.
65 /// Are odd single-precision registers permitted?
66 /// This corresponds to -modd-spreg and -mno-odd-spreg
69 // IsNan2008 - IEEE 754-2008 NaN encoding.
72 // IsFP64bit - General-purpose registers are 64 bits wide
75 // HasVFPU - Processor has a vector floating point unit.
78 // CPU supports cnMIPS (Cavium Networks Octeon CPU).
81 // isLinux - Target system is Linux. Is false we consider ELFOS for now.
84 // UseSmallSection - Small section is used.
87 /// Features related to the presence of specific instructions.
89 // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
92 // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
95 // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
98 // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
101 // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
104 // InMips16 -- can process Mips16 instructions
108 bool InMips16HardFloat;
110 // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
111 bool PreviousInMips16Mode;
113 // InMicroMips -- can process MicroMips instructions
114 bool InMicroMipsMode;
116 // HasDSP, HasDSPR2 -- supports DSP ASE.
117 bool HasDSP, HasDSPR2;
119 // Allow mixed Mips16 and Mips32 in one source file
120 bool AllowMixed16_32;
122 // Optimize for space by compiling all functions as Mips 16 unless
123 // it needs floating point. Functions needing floating point are
124 // compiled as Mips32
127 // HasMSA -- supports MSA ASE.
130 InstrItineraryData InstrItins;
132 // We can override the determination of whether we are in mips16 mode
133 // as from the command line
134 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
136 const MipsTargetMachine &TM;
140 const DataLayout DL; // Calculates type size & alignment
141 const MipsSelectionDAGInfo TSInfo;
142 std::unique_ptr<const MipsInstrInfo> InstrInfo;
143 std::unique_ptr<const MipsFrameLowering> FrameLowering;
144 std::unique_ptr<const MipsTargetLowering> TLInfo;
147 /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
148 bool enablePostMachineScheduler() const override;
149 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
150 CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
152 /// Only O32 and EABI supported right now.
153 bool isABI_EABI() const;
154 bool isABI_N64() const;
155 bool isABI_N32() const;
156 bool isABI_O32() const;
157 const MipsABIInfo &getABI() const;
158 bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
160 /// This constructor initializes the data members to match that
161 /// of the specified triple.
162 MipsSubtarget(const std::string &TT, const std::string &CPU,
163 const std::string &FS, bool little,
164 const MipsTargetMachine &TM);
166 /// ParseSubtargetFeatures - Parses features string setting specified
167 /// subtarget options. Definition of function is auto generated by tblgen.
168 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
170 bool hasMips1() const { return MipsArchVersion >= Mips1; }
171 bool hasMips2() const { return MipsArchVersion >= Mips2; }
172 bool hasMips3() const { return MipsArchVersion >= Mips3; }
173 bool hasMips4() const { return MipsArchVersion >= Mips4; }
174 bool hasMips5() const { return MipsArchVersion >= Mips5; }
175 bool hasMips4_32() const { return HasMips4_32; }
176 bool hasMips4_32r2() const { return HasMips4_32r2; }
177 bool hasMips32() const {
178 return MipsArchVersion >= Mips32 && MipsArchVersion != Mips3 &&
179 MipsArchVersion != Mips4 && MipsArchVersion != Mips5;
181 bool hasMips32r2() const {
182 return MipsArchVersion == Mips32r2 || MipsArchVersion == Mips32r6 ||
183 MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6;
185 bool hasMips32r6() const {
186 return MipsArchVersion == Mips32r6 || MipsArchVersion == Mips64r6;
188 bool hasMips64() const { return MipsArchVersion >= Mips64; }
189 bool hasMips64r2() const {
190 return MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6;
192 bool hasMips64r6() const { return MipsArchVersion == Mips64r6; }
194 bool hasCnMips() const { return HasCnMips; }
196 bool isLittle() const { return IsLittle; }
197 bool isABICalls() const { return !NoABICalls; }
198 bool isFPXX() const { return IsFPXX; }
199 bool isFP64bit() const { return IsFP64bit; }
200 bool useOddSPReg() const { return UseOddSPReg; }
201 bool noOddSPReg() const { return !UseOddSPReg; }
202 bool isNaN2008() const { return IsNaN2008bit; }
203 bool isGP64bit() const { return IsGP64bit; }
204 bool isGP32bit() const { return !IsGP64bit; }
205 unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
206 bool isSingleFloat() const { return IsSingleFloat; }
207 bool hasVFPU() const { return HasVFPU; }
208 bool inMips16Mode() const { return InMips16Mode; }
209 bool inMips16ModeDefault() const {
212 // Hard float for mips16 means essentially to compile as soft float
213 // but to use a runtime library for soft float that is written with
214 // native mips32 floating point instructions (those runtime routines
215 // run in mips32 hard float mode).
216 bool inMips16HardFloat() const {
217 return inMips16Mode() && InMips16HardFloat;
219 bool inMicroMipsMode() const { return InMicroMipsMode; }
220 bool hasDSP() const { return HasDSP; }
221 bool hasDSPR2() const { return HasDSPR2; }
222 bool hasMSA() const { return HasMSA; }
223 bool useSmallSection() const { return UseSmallSection; }
225 bool hasStandardEncoding() const { return !inMips16Mode(); }
227 bool abiUsesSoftFloat() const;
229 bool enableLongBranchPass() const {
230 return hasStandardEncoding() || allowMixed16_32();
233 /// Features related to the presence of specific instructions.
234 bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
235 bool hasMTHC1() const { return hasMips32r2(); }
237 bool allowMixed16_32() const { return inMips16ModeDefault() |
240 bool os16() const { return Os16; }
242 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
244 // for now constant islands are on for the whole compilation unit but we only
245 // really use them if in addition we are in mips16 mode
246 static bool useConstantIslands();
248 unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
250 // Grab relocation model
251 Reloc::Model getRelocationModel() const;
253 MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
254 const TargetMachine &TM);
256 /// Does the system support unaligned memory access.
258 /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
259 /// specify which component of the system provides it. Hardware, software, and
260 /// hybrid implementations are all valid.
261 bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
263 // Set helper classes
264 void setHelperClassesMips16();
265 void setHelperClassesMipsSE();
267 const MipsSelectionDAGInfo *getSelectionDAGInfo() const override {
270 const DataLayout *getDataLayout() const override { return &DL; }
271 const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
272 const TargetFrameLowering *getFrameLowering() const override {
273 return FrameLowering.get();
275 const MipsRegisterInfo *getRegisterInfo() const override {
276 return &InstrInfo->getRegisterInfo();
278 const MipsTargetLowering *getTargetLowering() const override {
281 const InstrItineraryData *getInstrItineraryData() const override {
285 } // End llvm namespace