1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef MIPSSUBTARGET_H
15 #define MIPSSUBTARGET_H
17 #include "MCTargetDesc/MipsReginfo.h"
18 #include "llvm/MC/MCInstrItineraries.h"
19 #include "llvm/Target/TargetSubtargetInfo.h"
22 #define GET_SUBTARGETINFO_HEADER
23 #include "MipsGenSubtargetInfo.inc"
28 class MipsSubtarget : public MipsGenSubtargetInfo {
29 virtual void anchor();
32 // NOTE: O64 will not be supported.
34 UnknownABI, O32, N32, N64, EABI
40 Mips32, Mips32r2, Mips64, Mips64r2
43 // Mips architecture version
44 MipsArchEnum MipsArchVersion;
46 // Mips supported ABIs
49 // IsLittle - The target is Little Endian
52 // IsSingleFloat - The target only supports single precision float
53 // point operations. This enable the target to use all 32 32-bit
54 // floating point registers instead of only using even ones.
57 // IsFP64bit - The target processor has 64-bit floating point registers.
60 // IsFP64bit - General-purpose registers are 64 bits wide
63 // HasVFPU - Processor has a vector floating point unit.
66 // isLinux - Target system is Linux. Is false we consider ELFOS for now.
69 // UseSmallSection - Small section is used.
72 /// Features related to the presence of specific instructions.
74 // HasSEInReg - SEB and SEH (signext in register) instructions.
77 // HasCondMov - Conditional mov (MOVZ, MOVN) instructions.
80 // HasSwap - Byte and half swap instructions.
83 // HasBitCount - Count leading '1' and '0' bits.
86 // HasFPIdx -- Floating point indexed load/store instructions.
89 // InMips16 -- can process Mips16 instructions
92 // HasDSP, HasDSPR2 -- supports DSP ASE.
93 bool HasDSP, HasDSPR2;
95 // IsAndroid -- target is android
98 InstrItineraryData InstrItins;
100 // The instance to the register info section object
104 virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
105 AntiDepBreakMode& Mode,
106 RegClassVector& CriticalPathRCs) const;
108 /// Only O32 and EABI supported right now.
109 bool isABI_EABI() const { return MipsABI == EABI; }
110 bool isABI_N64() const { return MipsABI == N64; }
111 bool isABI_N32() const { return MipsABI == N32; }
112 bool isABI_O32() const { return MipsABI == O32; }
113 unsigned getTargetABI() const { return MipsABI; }
115 /// This constructor initializes the data members to match that
116 /// of the specified triple.
117 MipsSubtarget(const std::string &TT, const std::string &CPU,
118 const std::string &FS, bool little, Reloc::Model RM);
120 /// ParseSubtargetFeatures - Parses features string setting specified
121 /// subtarget options. Definition of function is auto generated by tblgen.
122 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
124 bool hasMips32() const { return MipsArchVersion >= Mips32; }
125 bool hasMips32r2() const { return MipsArchVersion == Mips32r2 ||
126 MipsArchVersion == Mips64r2; }
127 bool hasMips64() const { return MipsArchVersion >= Mips64; }
128 bool hasMips64r2() const { return MipsArchVersion == Mips64r2; }
130 bool isLittle() const { return IsLittle; }
131 bool isFP64bit() const { return IsFP64bit; }
132 bool isGP64bit() const { return IsGP64bit; }
133 bool isGP32bit() const { return !IsGP64bit; }
134 bool isSingleFloat() const { return IsSingleFloat; }
135 bool isNotSingleFloat() const { return !IsSingleFloat; }
136 bool hasVFPU() const { return HasVFPU; }
137 bool inMips16Mode() const { return InMips16Mode; }
138 bool hasDSP() const { return HasDSP; }
139 bool hasDSPR2() const { return HasDSPR2; }
140 bool isAndroid() const { return IsAndroid; }
141 bool isLinux() const { return IsLinux; }
142 bool useSmallSection() const { return UseSmallSection; }
144 bool hasStandardEncoding() const { return !inMips16Mode(); }
146 /// Features related to the presence of specific instructions.
147 bool hasSEInReg() const { return HasSEInReg; }
148 bool hasCondMov() const { return HasCondMov; }
149 bool hasSwap() const { return HasSwap; }
150 bool hasBitCount() const { return HasBitCount; }
151 bool hasFPIdx() const { return HasFPIdx; }
153 // Grab MipsRegInfo object
154 const MipsReginfo &getMReginfo() const { return MRI; }
156 } // End llvm namespace