1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
15 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
17 #include "MCTargetDesc/MipsABIInfo.h"
18 #include "MipsFrameLowering.h"
19 #include "MipsISelLowering.h"
20 #include "MipsInstrInfo.h"
21 #include "llvm/IR/DataLayout.h"
22 #include "llvm/MC/MCInstrItineraries.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Target/TargetSelectionDAGInfo.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
28 #define GET_SUBTARGETINFO_HEADER
29 #include "MipsGenSubtargetInfo.inc"
34 class MipsTargetMachine;
36 class MipsSubtarget : public MipsGenSubtargetInfo {
37 virtual void anchor();
41 Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
42 Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
45 // Mips architecture version
46 MipsArchEnum MipsArchVersion;
48 // IsLittle - The target is Little Endian
51 // IsSoftFloat - The target does not support any floating point instructions.
54 // IsSingleFloat - The target only supports single precision float
55 // point operations. This enable the target to use all 32 32-bit
56 // floating point registers instead of only using even ones.
59 // IsFPXX - MIPS O32 modeless ABI.
62 // NoABICalls - Disable SVR4-style position-independent code.
65 // IsFP64bit - The target processor has 64-bit floating point registers.
68 /// Are odd single-precision registers permitted?
69 /// This corresponds to -modd-spreg and -mno-odd-spreg
72 // IsNan2008 - IEEE 754-2008 NaN encoding.
75 // IsFP64bit - General-purpose registers are 64 bits wide
78 // HasVFPU - Processor has a vector floating point unit.
81 // CPU supports cnMIPS (Cavium Networks Octeon CPU).
84 // isLinux - Target system is Linux. Is false we consider ELFOS for now.
87 // UseSmallSection - Small section is used.
90 /// Features related to the presence of specific instructions.
92 // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
95 // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
98 // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
101 // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
104 // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
107 // InMips16 -- can process Mips16 instructions
111 bool InMips16HardFloat;
113 // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
114 bool PreviousInMips16Mode;
116 // InMicroMips -- can process MicroMips instructions
117 bool InMicroMipsMode;
119 // HasDSP, HasDSPR2 -- supports DSP ASE.
120 bool HasDSP, HasDSPR2;
122 // Allow mixed Mips16 and Mips32 in one source file
123 bool AllowMixed16_32;
125 // Optimize for space by compiling all functions as Mips 16 unless
126 // it needs floating point. Functions needing floating point are
127 // compiled as Mips32
130 // HasMSA -- supports MSA ASE.
133 // UseTCCInDIV -- Enables the use of trapping in the assembler.
136 // HasEVA -- supports EVA ASE.
139 InstrItineraryData InstrItins;
141 // We can override the determination of whether we are in mips16 mode
142 // as from the command line
143 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
145 const MipsTargetMachine &TM;
149 const TargetSelectionDAGInfo TSInfo;
150 std::unique_ptr<const MipsInstrInfo> InstrInfo;
151 std::unique_ptr<const MipsFrameLowering> FrameLowering;
152 std::unique_ptr<const MipsTargetLowering> TLInfo;
155 /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
156 bool enablePostRAScheduler() const override;
157 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
158 CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
160 /// Only O32 and EABI supported right now.
161 bool isABI_EABI() const;
162 bool isABI_N64() const;
163 bool isABI_N32() const;
164 bool isABI_O32() const;
165 const MipsABIInfo &getABI() const;
166 bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
168 /// This constructor initializes the data members to match that
169 /// of the specified triple.
170 MipsSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
171 bool little, const MipsTargetMachine &TM);
173 /// ParseSubtargetFeatures - Parses features string setting specified
174 /// subtarget options. Definition of function is auto generated by tblgen.
175 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
177 bool hasMips1() const { return MipsArchVersion >= Mips1; }
178 bool hasMips2() const { return MipsArchVersion >= Mips2; }
179 bool hasMips3() const { return MipsArchVersion >= Mips3; }
180 bool hasMips4() const { return MipsArchVersion >= Mips4; }
181 bool hasMips5() const { return MipsArchVersion >= Mips5; }
182 bool hasMips4_32() const { return HasMips4_32; }
183 bool hasMips4_32r2() const { return HasMips4_32r2; }
184 bool hasMips32() const {
185 return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
188 bool hasMips32r2() const {
189 return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
192 bool hasMips32r3() const {
193 return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
196 bool hasMips32r5() const {
197 return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
200 bool hasMips32r6() const {
201 return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
204 bool hasMips64() const { return MipsArchVersion >= Mips64; }
205 bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
206 bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
207 bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
208 bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
210 bool hasCnMips() const { return HasCnMips; }
212 bool isLittle() const { return IsLittle; }
213 bool isABICalls() const { return !NoABICalls; }
214 bool isFPXX() const { return IsFPXX; }
215 bool isFP64bit() const { return IsFP64bit; }
216 bool useOddSPReg() const { return UseOddSPReg; }
217 bool noOddSPReg() const { return !UseOddSPReg; }
218 bool isNaN2008() const { return IsNaN2008bit; }
219 bool isGP64bit() const { return IsGP64bit; }
220 bool isGP32bit() const { return !IsGP64bit; }
221 unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
222 bool isSingleFloat() const { return IsSingleFloat; }
223 bool hasVFPU() const { return HasVFPU; }
224 bool inMips16Mode() const { return InMips16Mode; }
225 bool inMips16ModeDefault() const {
228 // Hard float for mips16 means essentially to compile as soft float
229 // but to use a runtime library for soft float that is written with
230 // native mips32 floating point instructions (those runtime routines
231 // run in mips32 hard float mode).
232 bool inMips16HardFloat() const {
233 return inMips16Mode() && InMips16HardFloat;
235 bool inMicroMipsMode() const { return InMicroMipsMode; }
236 bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); }
237 bool inMicroMips64r6Mode() const { return InMicroMipsMode && hasMips64r6(); }
238 bool hasDSP() const { return HasDSP; }
239 bool hasDSPR2() const { return HasDSPR2; }
240 bool hasMSA() const { return HasMSA; }
241 bool hasEVA() const { return HasEVA; }
242 bool useSmallSection() const { return UseSmallSection; }
244 bool hasStandardEncoding() const { return !inMips16Mode(); }
246 bool useSoftFloat() const { return IsSoftFloat; }
248 bool enableLongBranchPass() const {
249 return hasStandardEncoding() || allowMixed16_32();
252 /// Features related to the presence of specific instructions.
253 bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
254 bool hasMTHC1() const { return hasMips32r2(); }
256 bool allowMixed16_32() const { return inMips16ModeDefault() |
259 bool os16() const { return Os16; }
261 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
263 // for now constant islands are on for the whole compilation unit but we only
264 // really use them if in addition we are in mips16 mode
265 static bool useConstantIslands();
267 unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
269 // Grab relocation model
270 Reloc::Model getRelocationModel() const;
272 MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
273 const TargetMachine &TM);
275 /// Does the system support unaligned memory access.
277 /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
278 /// specify which component of the system provides it. Hardware, software, and
279 /// hybrid implementations are all valid.
280 bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
282 // Set helper classes
283 void setHelperClassesMips16();
284 void setHelperClassesMipsSE();
286 const TargetSelectionDAGInfo *getSelectionDAGInfo() const override {
289 const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
290 const TargetFrameLowering *getFrameLowering() const override {
291 return FrameLowering.get();
293 const MipsRegisterInfo *getRegisterInfo() const override {
294 return &InstrInfo->getRegisterInfo();
296 const MipsTargetLowering *getTargetLowering() const override {
299 const InstrItineraryData *getInstrItineraryData() const override {
303 } // End llvm namespace