1 //===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "MipsMachineFunction.h"
16 #include "MipsRegisterInfo.h"
17 #include "MipsSubtarget.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/IR/Attributes.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Support/raw_ostream.h"
28 #define DEBUG_TYPE "mips-subtarget"
30 #define GET_SUBTARGETINFO_TARGET_DESC
31 #define GET_SUBTARGETINFO_CTOR
32 #include "MipsGenSubtargetInfo.inc"
34 // FIXME: Maybe this should be on by default when Mips16 is specified
36 static cl::opt<bool> Mixed16_32(
39 cl::desc("Allow for a mixture of Mips16 "
40 "and Mips32 code in a single source file"),
43 static cl::opt<bool> Mips_Os16(
46 cl::desc("Compile all functions that don' use "
47 "floating point as Mips 16"),
51 Mips16HardFloat("mips16-hard-float", cl::NotHidden,
52 cl::desc("MIPS: mips16 hard float enable."),
56 Mips16ConstantIslands(
57 "mips16-constant-islands", cl::NotHidden,
58 cl::desc("MIPS: mips16 constant islands enable."),
62 GPOpt("mgpopt", cl::Hidden,
63 cl::desc("MIPS: Enable gp-relative addressing of small data items"));
65 void MipsSubtarget::anchor() { }
67 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
68 const std::string &FS, bool little,
69 const MipsTargetMachine &TM)
70 : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
71 IsLittle(little), IsSingleFloat(false), IsFPXX(false), NoABICalls(false),
72 IsFP64bit(false), UseOddSPReg(true), IsNaN2008bit(false),
73 IsGP64bit(false), HasVFPU(false), HasCnMips(false), HasMips3_32(false),
74 HasMips3_32r2(false), HasMips4_32(false), HasMips4_32r2(false),
75 HasMips5_32r2(false), InMips16Mode(false),
76 InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
77 HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
78 HasMSA(false), TM(TM), TargetTriple(TT), TSInfo(*TM.getDataLayout()),
80 MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
81 FrameLowering(MipsFrameLowering::create(*this)),
82 TLInfo(MipsTargetLowering::create(TM, *this)) {
84 PreviousInMips16Mode = InMips16Mode;
86 if (MipsArchVersion == MipsDefault)
87 MipsArchVersion = Mips32;
89 // Don't even attempt to generate code for MIPS-I and MIPS-V. They have not
90 // been tested and currently exist for the integrated assembler only.
91 if (MipsArchVersion == Mips1)
92 report_fatal_error("Code generation for MIPS-I is not implemented", false);
93 if (MipsArchVersion == Mips5)
94 report_fatal_error("Code generation for MIPS-V is not implemented", false);
96 // Check if Architecture and ABI are compatible.
97 assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) ||
98 (isGP64bit() && (isABI_N32() || isABI_N64()))) &&
99 "Invalid Arch & ABI pair.");
101 if (hasMSA() && !isFP64bit())
102 report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
106 if (!isABI_O32() && !useOddSPReg())
107 report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false);
109 if (IsFPXX && (isABI_N32() || isABI_N64()))
110 report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);
113 StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
118 report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
121 if (NoABICalls && TM.getRelocationModel() == Reloc::PIC_)
122 report_fatal_error("position-independent code requires '-mabicalls'");
124 // Set UseSmallSection.
125 UseSmallSection = GPOpt;
126 if (!NoABICalls && GPOpt) {
127 errs() << "warning: cannot use small-data accesses for '-mabicalls'"
129 UseSmallSection = false;
133 /// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
134 bool MipsSubtarget::enablePostMachineScheduler() const { return true; }
136 void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
137 CriticalPathRCs.clear();
138 CriticalPathRCs.push_back(isGP64bit() ?
139 &Mips::GPR64RegClass : &Mips::GPR32RegClass);
142 CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
143 return CodeGenOpt::Aggressive;
147 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
148 const TargetMachine &TM) {
149 std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU);
151 // Parse features string.
152 ParseSubtargetFeatures(CPUName, FS);
153 // Initialize scheduling itinerary for the specified CPU.
154 InstrItins = getInstrItineraryForCPU(CPUName);
156 if (InMips16Mode && !TM.Options.UseSoftFloat)
157 InMips16HardFloat = true;
162 bool MipsSubtarget::abiUsesSoftFloat() const {
163 return TM.Options.UseSoftFloat && !InMips16HardFloat;
166 bool MipsSubtarget::useConstantIslands() {
167 DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n");
168 return Mips16ConstantIslands;
171 Reloc::Model MipsSubtarget::getRelocationModel() const {
172 return TM.getRelocationModel();
175 bool MipsSubtarget::isABI_EABI() const { return getABI().IsEABI(); }
176 bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); }
177 bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); }
178 bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); }
179 const MipsABIInfo &MipsSubtarget::getABI() const { return TM.getABI(); }