1 //===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "MipsMachineFunction.h"
16 #include "MipsRegisterInfo.h"
17 #include "MipsSubtarget.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/IR/Attributes.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Support/raw_ostream.h"
28 #define DEBUG_TYPE "mips-subtarget"
30 #define GET_SUBTARGETINFO_TARGET_DESC
31 #define GET_SUBTARGETINFO_CTOR
32 #include "MipsGenSubtargetInfo.inc"
34 // FIXME: Maybe this should be on by default when Mips16 is specified
36 static cl::opt<bool> Mixed16_32(
39 cl::desc("Allow for a mixture of Mips16 "
40 "and Mips32 code in a single source file"),
43 static cl::opt<bool> Mips_Os16(
46 cl::desc("Compile all functions that don' use "
47 "floating point as Mips 16"),
51 Mips16HardFloat("mips16-hard-float", cl::NotHidden,
52 cl::desc("MIPS: mips16 hard float enable."),
56 Mips16ConstantIslands(
57 "mips16-constant-islands", cl::NotHidden,
58 cl::desc("MIPS: mips16 constant islands enable."),
62 GPOpt("mgpopt", cl::Hidden,
63 cl::desc("MIPS: Enable gp-relative addressing of small data items"));
65 /// Select the Mips CPU for the given triple and cpu name.
66 /// FIXME: Merge with the copy in MipsMCTargetDesc.cpp
67 static StringRef selectMipsCPU(Triple TT, StringRef CPU) {
68 if (CPU.empty() || CPU == "generic") {
69 if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
77 void MipsSubtarget::anchor() { }
79 static std::string computeDataLayout(const MipsSubtarget &ST) {
82 // There are both little and big endian mips.
90 // Pointers are 32 bit on some ABIs.
94 // 8 and 16 bit integers only need no have natural alignment, but try to
95 // align them to 32 bits. 64 bit integers have natural alignment.
96 Ret += "-i8:8:32-i16:16:32-i64:64";
98 // 32 bit registers are always available and the stack is at least 64 bit
99 // aligned. On N64 64 bit registers are also available and the stack is
101 if (ST.isABI_N64() || ST.isABI_N32())
102 Ret += "-n32:64-S128";
109 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
110 const std::string &FS, bool little,
111 const MipsTargetMachine *_TM)
112 : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
113 ABI(MipsABIInfo::Unknown()), IsLittle(little), IsSingleFloat(false),
114 IsFPXX(false), NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
115 IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
116 IsLinux(true), HasMips3_32(false), HasMips3_32r2(false),
117 HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false),
118 InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
119 InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
120 AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
121 HasMSA(false), TM(_TM), TargetTriple(TT),
122 DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS, TM))),
123 TSInfo(DL), InstrInfo(MipsInstrInfo::create(*this)),
124 FrameLowering(MipsFrameLowering::create(*this)),
125 TLInfo(MipsTargetLowering::create(*TM, *this)) {
127 PreviousInMips16Mode = InMips16Mode;
129 if (MipsArchVersion == MipsDefault)
130 MipsArchVersion = Mips32;
132 // Don't even attempt to generate code for MIPS-I, MIPS-III and MIPS-V.
133 // They have not been tested and currently exist for the integrated
135 if (MipsArchVersion == Mips1)
136 report_fatal_error("Code generation for MIPS-I is not implemented", false);
137 if (MipsArchVersion == Mips3)
138 report_fatal_error("Code generation for MIPS-III is not implemented",
140 if (MipsArchVersion == Mips5)
141 report_fatal_error("Code generation for MIPS-V is not implemented", false);
143 // Assert exactly one ABI was chosen.
144 assert(ABI.IsKnown());
145 assert((((getFeatureBits() & Mips::FeatureO32) != 0) +
146 ((getFeatureBits() & Mips::FeatureEABI) != 0) +
147 ((getFeatureBits() & Mips::FeatureN32) != 0) +
148 ((getFeatureBits() & Mips::FeatureN64) != 0)) == 1);
150 // Check if Architecture and ABI are compatible.
151 assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) ||
152 (isGP64bit() && (isABI_N32() || isABI_N64()))) &&
153 "Invalid Arch & ABI pair.");
155 if (hasMSA() && !isFP64bit())
156 report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
160 if (!isABI_O32() && !useOddSPReg())
161 report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false);
163 if (IsFPXX && (isABI_N32() || isABI_N64()))
164 report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);
167 StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
172 report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
175 // Is the target system Linux ?
176 if (TT.find("linux") == std::string::npos)
179 if (NoABICalls && TM->getRelocationModel() == Reloc::PIC_)
180 report_fatal_error("position-independent code requires '-mabicalls'");
182 // Set UseSmallSection.
183 UseSmallSection = GPOpt;
184 if (!NoABICalls && GPOpt) {
185 errs() << "warning: cannot use small-data accesses for '-mabicalls'"
187 UseSmallSection = false;
191 /// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
192 bool MipsSubtarget::enablePostMachineScheduler() const { return true; }
194 void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
195 CriticalPathRCs.clear();
196 CriticalPathRCs.push_back(isGP64bit() ?
197 &Mips::GPR64RegClass : &Mips::GPR32RegClass);
200 CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
201 return CodeGenOpt::Aggressive;
205 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
206 const TargetMachine *TM) {
207 std::string CPUName = selectMipsCPU(TargetTriple, CPU);
209 // Parse features string.
210 ParseSubtargetFeatures(CPUName, FS);
211 // Initialize scheduling itinerary for the specified CPU.
212 InstrItins = getInstrItineraryForCPU(CPUName);
214 if (InMips16Mode && !TM->Options.UseSoftFloat)
215 InMips16HardFloat = true;
220 bool MipsSubtarget::abiUsesSoftFloat() const {
221 return TM->Options.UseSoftFloat && !InMips16HardFloat;
224 bool MipsSubtarget::useConstantIslands() {
225 DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n");
226 return Mips16ConstantIslands;
229 Reloc::Model MipsSubtarget::getRelocationModel() const {
230 return TM->getRelocationModel();