1 //===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "MipsMachineFunction.h"
16 #include "MipsRegisterInfo.h"
17 #include "MipsSubtarget.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/IR/Attributes.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Support/raw_ostream.h"
28 #define DEBUG_TYPE "mips-subtarget"
30 #define GET_SUBTARGETINFO_TARGET_DESC
31 #define GET_SUBTARGETINFO_CTOR
32 #include "MipsGenSubtargetInfo.inc"
34 // FIXME: Maybe this should be on by default when Mips16 is specified
36 static cl::opt<bool> Mixed16_32(
39 cl::desc("Allow for a mixture of Mips16 "
40 "and Mips32 code in a single source file"),
43 static cl::opt<bool> Mips_Os16(
46 cl::desc("Compile all functions that don' use "
47 "floating point as Mips 16"),
51 Mips16HardFloat("mips16-hard-float", cl::NotHidden,
52 cl::desc("MIPS: mips16 hard float enable."),
56 Mips16ConstantIslands(
57 "mips16-constant-islands", cl::NotHidden,
58 cl::desc("MIPS: mips16 constant islands enable."),
61 /// Select the Mips CPU for the given triple and cpu name.
62 /// FIXME: Merge with the copy in MipsMCTargetDesc.cpp
63 static StringRef selectMipsCPU(Triple TT, StringRef CPU) {
64 if (CPU.empty() || CPU == "generic") {
65 if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
73 void MipsSubtarget::anchor() { }
75 static std::string computeDataLayout(const MipsSubtarget &ST) {
78 // There are both little and big endian mips.
86 // Pointers are 32 bit on some ABIs.
90 // 8 and 16 bit integers only need no have natural alignment, but try to
91 // align them to 32 bits. 64 bit integers have natural alignment.
92 Ret += "-i8:8:32-i16:16:32-i64:64";
94 // 32 bit registers are always available and the stack is at least 64 bit
95 // aligned. On N64 64 bit registers are also available and the stack is
97 if (ST.isABI_N64() || ST.isABI_N32())
98 Ret += "-n32:64-S128";
105 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
106 const std::string &FS, bool little,
107 MipsTargetMachine *_TM)
108 : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32),
109 MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false),
110 IsFPXX(false), IsFP64bit(false), UseOddSPReg(true), IsNaN2008bit(false),
111 IsGP64bit(false), HasVFPU(false), HasCnMips(false), IsLinux(true),
112 HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
113 HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
114 InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
115 HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
116 HasMSA(false), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT),
117 DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS, TM))),
118 TSInfo(DL), JITInfo(), InstrInfo(MipsInstrInfo::create(*TM)),
119 FrameLowering(MipsFrameLowering::create(*TM, *this)),
120 TLInfo(MipsTargetLowering::create(*TM)) {
122 PreviousInMips16Mode = InMips16Mode;
124 // Don't even attempt to generate code for MIPS-I, MIPS-II, MIPS-III, and
125 // MIPS-V. They have not been tested and currently exist for the integrated
127 if (MipsArchVersion == Mips1)
128 report_fatal_error("Code generation for MIPS-I is not implemented", false);
129 if (MipsArchVersion == Mips2)
130 report_fatal_error("Code generation for MIPS-II is not implemented", false);
131 if (MipsArchVersion == Mips3)
132 report_fatal_error("Code generation for MIPS-III is not implemented",
134 if (MipsArchVersion == Mips5)
135 report_fatal_error("Code generation for MIPS-V is not implemented", false);
137 // Assert exactly one ABI was chosen.
138 assert(MipsABI != UnknownABI);
139 assert((((getFeatureBits() & Mips::FeatureO32) != 0) +
140 ((getFeatureBits() & Mips::FeatureEABI) != 0) +
141 ((getFeatureBits() & Mips::FeatureN32) != 0) +
142 ((getFeatureBits() & Mips::FeatureN64) != 0)) == 1);
144 // Check if Architecture and ABI are compatible.
145 assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) ||
146 (isGP64bit() && (isABI_N32() || isABI_N64()))) &&
147 "Invalid Arch & ABI pair.");
149 if (hasMSA() && !isFP64bit())
150 report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
154 if (!isABI_O32() && !useOddSPReg())
155 report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false);
157 if (IsFPXX && (isABI_N32() || isABI_N64()))
158 report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);
161 StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
166 report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
169 // Is the target system Linux ?
170 if (TT.find("linux") == std::string::npos)
173 // Set UseSmallSection.
174 // TODO: Investigate the IsLinux check. I suspect it's really checking for
176 UseSmallSection = !IsLinux && (TM->getRelocationModel() == Reloc::Static);
179 /// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
180 bool MipsSubtarget::enablePostMachineScheduler() const { return true; }
182 void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
183 CriticalPathRCs.clear();
184 CriticalPathRCs.push_back(isGP64bit() ?
185 &Mips::GPR64RegClass : &Mips::GPR32RegClass);
188 CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
189 return CodeGenOpt::Aggressive;
193 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
194 const TargetMachine *TM) {
195 std::string CPUName = selectMipsCPU(TargetTriple, CPU);
197 // Parse features string.
198 ParseSubtargetFeatures(CPUName, FS);
199 // Initialize scheduling itinerary for the specified CPU.
200 InstrItins = getInstrItineraryForCPU(CPUName);
202 if (InMips16Mode && !TM->Options.UseSoftFloat)
203 InMips16HardFloat = true;
208 //FIXME: This logic for reseting the subtarget along with
209 // the helper classes can probably be simplified but there are a lot of
210 // cases so we will defer rewriting this to later.
212 void MipsSubtarget::resetSubtarget(MachineFunction *MF) {
213 bool ChangeToMips16 = false, ChangeToNoMips16 = false;
214 DEBUG(dbgs() << "resetSubtargetFeatures" << "\n");
215 AttributeSet FnAttrs = MF->getFunction()->getAttributes();
216 ChangeToMips16 = FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
218 ChangeToNoMips16 = FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
220 assert (!(ChangeToMips16 & ChangeToNoMips16) &&
221 "mips16 and nomips16 specified on the same function");
222 if (ChangeToMips16) {
223 if (PreviousInMips16Mode)
225 OverrideMode = Mips16Override;
226 PreviousInMips16Mode = true;
227 setHelperClassesMips16();
229 } else if (ChangeToNoMips16) {
230 if (!PreviousInMips16Mode)
232 OverrideMode = NoMips16Override;
233 PreviousInMips16Mode = false;
234 setHelperClassesMipsSE();
237 if (OverrideMode == NoOverride)
239 OverrideMode = NoOverride;
240 DEBUG(dbgs() << "back to default" << "\n");
241 if (inMips16Mode() && !PreviousInMips16Mode) {
242 setHelperClassesMips16();
243 PreviousInMips16Mode = true;
244 } else if (!inMips16Mode() && PreviousInMips16Mode) {
245 setHelperClassesMipsSE();
246 PreviousInMips16Mode = false;
252 void MipsSubtarget::setHelperClassesMips16() {
253 InstrInfoSE.swap(InstrInfo);
254 FrameLoweringSE.swap(FrameLowering);
255 TLInfoSE.swap(TLInfo);
257 InstrInfo.reset(MipsInstrInfo::create(*TM));
258 FrameLowering.reset(MipsFrameLowering::create(*TM, *this));
259 TLInfo.reset(MipsTargetLowering::create(*TM));
261 InstrInfo16.swap(InstrInfo);
262 FrameLowering16.swap(FrameLowering);
263 TLInfo16.swap(TLInfo);
265 assert(TLInfo && "null target lowering 16");
266 assert(InstrInfo && "null instr info 16");
267 assert(FrameLowering && "null frame lowering 16");
270 void MipsSubtarget::setHelperClassesMipsSE() {
271 InstrInfo16.swap(InstrInfo);
272 FrameLowering16.swap(FrameLowering);
273 TLInfo16.swap(TLInfo);
275 InstrInfo.reset(MipsInstrInfo::create(*TM));
276 FrameLowering.reset(MipsFrameLowering::create(*TM, *this));
277 TLInfo.reset(MipsTargetLowering::create(*TM));
279 InstrInfoSE.swap(InstrInfo);
280 FrameLoweringSE.swap(FrameLowering);
281 TLInfoSE.swap(TLInfo);
283 assert(TLInfo && "null target lowering in SE");
284 assert(InstrInfo && "null instr info SE");
285 assert(FrameLowering && "null frame lowering SE");
288 bool MipsSubtarget::abiUsesSoftFloat() const {
289 return TM->Options.UseSoftFloat && !InMips16HardFloat;
292 bool MipsSubtarget::useConstantIslands() {
293 DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n");
294 return Mips16ConstantIslands;
297 Reloc::Model MipsSubtarget::getRelocationModel() const {
298 return TM->getRelocationModel();