1 //===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsSEInstrInfo.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsMachineFunction.h"
17 #include "MipsTargetMachine.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/TargetRegistry.h"
27 MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI)
28 : MipsInstrInfo(STI, STI.getRelocationModel() == Reloc::PIC_ ? Mips::B
30 RI(STI), IsN64(STI.isABI_N64()) {}
32 const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
36 /// isLoadFromStackSlot - If the specified machine instruction is a direct
37 /// load from a stack slot, return the virtual or physical register number of
38 /// the destination along with the FrameIndex of the loaded stack slot. If
39 /// not, return 0. This predicate must return 0 if the instruction has
40 /// any side effects other than loading from the stack slot.
41 unsigned MipsSEInstrInfo::
42 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
44 unsigned Opc = MI->getOpcode();
46 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
47 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
48 if ((MI->getOperand(1).isFI()) && // is a stack slot
49 (MI->getOperand(2).isImm()) && // the imm is zero
50 (isZeroImm(MI->getOperand(2)))) {
51 FrameIndex = MI->getOperand(1).getIndex();
52 return MI->getOperand(0).getReg();
59 /// isStoreToStackSlot - If the specified machine instruction is a direct
60 /// store to a stack slot, return the virtual or physical register number of
61 /// the source reg along with the FrameIndex of the loaded stack slot. If
62 /// not, return 0. This predicate must return 0 if the instruction has
63 /// any side effects other than storing to the stack slot.
64 unsigned MipsSEInstrInfo::
65 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
67 unsigned Opc = MI->getOpcode();
69 if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
70 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
71 if ((MI->getOperand(1).isFI()) && // is a stack slot
72 (MI->getOperand(2).isImm()) && // the imm is zero
73 (isZeroImm(MI->getOperand(2)))) {
74 FrameIndex = MI->getOperand(1).getIndex();
75 return MI->getOperand(0).getReg();
81 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
82 MachineBasicBlock::iterator I, DebugLoc DL,
83 unsigned DestReg, unsigned SrcReg,
85 unsigned Opc = 0, ZeroReg = 0;
86 bool isMicroMips = Subtarget.inMicroMipsMode();
88 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
89 if (Mips::GPR32RegClass.contains(SrcReg)) {
91 Opc = Mips::MOVE16_MM;
93 Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
94 } else if (Mips::CCRRegClass.contains(SrcReg))
96 else if (Mips::FGR32RegClass.contains(SrcReg))
98 else if (Mips::HI32RegClass.contains(SrcReg)) {
99 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
101 } else if (Mips::LO32RegClass.contains(SrcReg)) {
102 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
104 } else if (Mips::HI32DSPRegClass.contains(SrcReg))
105 Opc = Mips::MFHI_DSP;
106 else if (Mips::LO32DSPRegClass.contains(SrcReg))
107 Opc = Mips::MFLO_DSP;
108 else if (Mips::DSPCCRegClass.contains(SrcReg)) {
109 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
110 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
113 else if (Mips::MSACtrlRegClass.contains(SrcReg))
116 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
117 if (Mips::CCRRegClass.contains(DestReg))
119 else if (Mips::FGR32RegClass.contains(DestReg))
121 else if (Mips::HI32RegClass.contains(DestReg))
122 Opc = Mips::MTHI, DestReg = 0;
123 else if (Mips::LO32RegClass.contains(DestReg))
124 Opc = Mips::MTLO, DestReg = 0;
125 else if (Mips::HI32DSPRegClass.contains(DestReg))
126 Opc = Mips::MTHI_DSP;
127 else if (Mips::LO32DSPRegClass.contains(DestReg))
128 Opc = Mips::MTLO_DSP;
129 else if (Mips::DSPCCRegClass.contains(DestReg)) {
130 BuildMI(MBB, I, DL, get(Mips::WRDSP))
131 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
132 .addReg(DestReg, RegState::ImplicitDefine);
135 else if (Mips::MSACtrlRegClass.contains(DestReg))
138 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
140 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
141 Opc = Mips::FMOV_D32;
142 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
143 Opc = Mips::FMOV_D64;
144 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
145 if (Mips::GPR64RegClass.contains(SrcReg))
146 Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
147 else if (Mips::HI64RegClass.contains(SrcReg))
148 Opc = Mips::MFHI64, SrcReg = 0;
149 else if (Mips::LO64RegClass.contains(SrcReg))
150 Opc = Mips::MFLO64, SrcReg = 0;
151 else if (Mips::FGR64RegClass.contains(SrcReg))
154 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
155 if (Mips::HI64RegClass.contains(DestReg))
156 Opc = Mips::MTHI64, DestReg = 0;
157 else if (Mips::LO64RegClass.contains(DestReg))
158 Opc = Mips::MTLO64, DestReg = 0;
159 else if (Mips::FGR64RegClass.contains(DestReg))
162 else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
163 if (Mips::MSA128BRegClass.contains(SrcReg))
167 assert(Opc && "Cannot copy registers");
169 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
172 MIB.addReg(DestReg, RegState::Define);
175 MIB.addReg(SrcReg, getKillRegState(KillSrc));
181 void MipsSEInstrInfo::
182 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
183 unsigned SrcReg, bool isKill, int FI,
184 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
185 int64_t Offset) const {
187 if (I != MBB.end()) DL = I->getDebugLoc();
188 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
192 if (Mips::GPR32RegClass.hasSubClassEq(RC))
194 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
196 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
197 Opc = Mips::STORE_ACC64;
198 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
199 Opc = Mips::STORE_ACC64DSP;
200 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
201 Opc = Mips::STORE_ACC128;
202 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
203 Opc = Mips::STORE_CCOND_DSP;
204 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
206 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
208 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
210 else if (RC->hasType(MVT::v16i8))
212 else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16))
214 else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
216 else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
219 assert(Opc && "Register class not handled!");
220 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
221 .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
224 void MipsSEInstrInfo::
225 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
226 unsigned DestReg, int FI, const TargetRegisterClass *RC,
227 const TargetRegisterInfo *TRI, int64_t Offset) const {
229 if (I != MBB.end()) DL = I->getDebugLoc();
230 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
233 if (Mips::GPR32RegClass.hasSubClassEq(RC))
235 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
237 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
238 Opc = Mips::LOAD_ACC64;
239 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
240 Opc = Mips::LOAD_ACC64DSP;
241 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
242 Opc = Mips::LOAD_ACC128;
243 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
244 Opc = Mips::LOAD_CCOND_DSP;
245 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
247 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
249 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
251 else if (RC->hasType(MVT::v16i8))
253 else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16))
255 else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
257 else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
260 assert(Opc && "Register class not handled!");
261 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
265 bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
266 MachineBasicBlock &MBB = *MI->getParent();
267 bool isMicroMips = Subtarget.inMicroMipsMode();
270 switch(MI->getDesc().getOpcode()) {
274 expandRetRA(MBB, MI);
276 case Mips::PseudoMFHI:
277 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
278 expandPseudoMFHiLo(MBB, MI, Opc);
280 case Mips::PseudoMFLO:
281 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
282 expandPseudoMFHiLo(MBB, MI, Opc);
284 case Mips::PseudoMFHI64:
285 expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);
287 case Mips::PseudoMFLO64:
288 expandPseudoMFHiLo(MBB, MI, Mips::MFLO64);
290 case Mips::PseudoMTLOHI:
291 expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false);
293 case Mips::PseudoMTLOHI64:
294 expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false);
296 case Mips::PseudoMTLOHI_DSP:
297 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true);
299 case Mips::PseudoCVT_S_W:
300 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
302 case Mips::PseudoCVT_D32_W:
303 expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false);
305 case Mips::PseudoCVT_S_L:
306 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
308 case Mips::PseudoCVT_D64_W:
309 expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true);
311 case Mips::PseudoCVT_D64_L:
312 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
314 case Mips::BuildPairF64:
315 expandBuildPairF64(MBB, MI, false);
317 case Mips::BuildPairF64_64:
318 expandBuildPairF64(MBB, MI, true);
320 case Mips::ExtractElementF64:
321 expandExtractElementF64(MBB, MI, false);
323 case Mips::ExtractElementF64_64:
324 expandExtractElementF64(MBB, MI, true);
326 case Mips::MIPSeh_return32:
327 case Mips::MIPSeh_return64:
328 expandEhReturn(MBB, MI);
336 /// getOppositeBranchOpc - Return the inverse of the specified
337 /// opcode, e.g. turning BEQ to BNE.
338 unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
340 default: llvm_unreachable("Illegal opcode!");
341 case Mips::BEQ: return Mips::BNE;
342 case Mips::BNE: return Mips::BEQ;
343 case Mips::BGTZ: return Mips::BLEZ;
344 case Mips::BGEZ: return Mips::BLTZ;
345 case Mips::BLTZ: return Mips::BGEZ;
346 case Mips::BLEZ: return Mips::BGTZ;
347 case Mips::BEQ64: return Mips::BNE64;
348 case Mips::BNE64: return Mips::BEQ64;
349 case Mips::BGTZ64: return Mips::BLEZ64;
350 case Mips::BGEZ64: return Mips::BLTZ64;
351 case Mips::BLTZ64: return Mips::BGEZ64;
352 case Mips::BLEZ64: return Mips::BGTZ64;
353 case Mips::BC1T: return Mips::BC1F;
354 case Mips::BC1F: return Mips::BC1T;
355 case Mips::BEQZC_MM: return Mips::BNEZC_MM;
356 case Mips::BNEZC_MM: return Mips::BEQZC_MM;
360 /// Adjust SP by Amount bytes.
361 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
362 MachineBasicBlock &MBB,
363 MachineBasicBlock::iterator I) const {
364 const MipsSubtarget &STI = Subtarget;
365 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
366 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
367 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
369 if (isInt<16>(Amount))// addi sp, sp, amount
370 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
371 else { // Expand immediate that doesn't fit in 16-bit.
372 unsigned Reg = loadImmediate(Amount, MBB, I, DL, nullptr);
373 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill);
377 /// This function generates the sequence of instructions needed to get the
378 /// result of adding register REG and immediate IMM.
380 MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
381 MachineBasicBlock::iterator II, DebugLoc DL,
382 unsigned *NewImm) const {
383 MipsAnalyzeImmediate AnalyzeImm;
384 const MipsSubtarget &STI = Subtarget;
385 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
386 unsigned Size = STI.isABI_N64() ? 64 : 32;
387 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
388 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
389 const TargetRegisterClass *RC = STI.isABI_N64() ?
390 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
391 bool LastInstrIsADDiu = NewImm;
393 const MipsAnalyzeImmediate::InstSeq &Seq =
394 AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
395 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
397 assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
399 // The first instruction can be a LUi, which is different from other
400 // instructions (ADDiu, ORI and SLL) in that it does not have a register
402 unsigned Reg = RegInfo.createVirtualRegister(RC);
404 if (Inst->Opc == LUi)
405 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
407 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
408 .addImm(SignExtend64<16>(Inst->ImmOpnd));
410 // Build the remaining instructions in Seq.
411 for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
412 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
413 .addImm(SignExtend64<16>(Inst->ImmOpnd));
415 if (LastInstrIsADDiu)
416 *NewImm = Inst->ImmOpnd;
421 unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
422 return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ ||
423 Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ ||
424 Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 ||
425 Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
426 Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B ||
427 Opc == Mips::J || Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM) ?
431 void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
432 MachineBasicBlock::iterator I) const {
433 if (Subtarget.isGP64bit())
434 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
435 .addReg(Mips::RA_64);
437 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn)).addReg(Mips::RA);
440 std::pair<bool, bool>
441 MipsSEInstrInfo::compareOpndSize(unsigned Opc,
442 const MachineFunction &MF) const {
443 const MCInstrDesc &Desc = get(Opc);
444 assert(Desc.NumOperands == 2 && "Unary instruction expected.");
445 const MipsRegisterInfo *RI = &getRegisterInfo();
446 unsigned DstRegSize = getRegClass(Desc, 0, RI, MF)->getSize();
447 unsigned SrcRegSize = getRegClass(Desc, 1, RI, MF)->getSize();
449 return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
452 void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB,
453 MachineBasicBlock::iterator I,
454 unsigned NewOpc) const {
455 BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
458 void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB,
459 MachineBasicBlock::iterator I,
462 bool HasExplicitDef) const {
464 // lo_hi pseudomtlohi $gpr0, $gpr1
465 // to these two instructions:
469 DebugLoc DL = I->getDebugLoc();
470 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
471 MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc));
472 MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc));
473 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
474 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
476 // Add lo/hi registers if the mtlo/hi instructions created have explicit
478 if (HasExplicitDef) {
479 unsigned DstReg = I->getOperand(0).getReg();
480 unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
481 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
482 LoInst.addReg(DstLo, RegState::Define);
483 HiInst.addReg(DstHi, RegState::Define);
487 void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
488 MachineBasicBlock::iterator I,
489 unsigned CvtOpc, unsigned MovOpc,
491 const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
492 const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
493 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
494 unsigned KillSrc = getKillRegState(Src.isKill());
495 DebugLoc DL = I->getDebugLoc();
496 bool DstIsLarger, SrcIsLarger;
498 std::tie(DstIsLarger, SrcIsLarger) =
499 compareOpndSize(CvtOpc, *MBB.getParent());
502 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
505 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
507 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
508 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
511 void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
512 MachineBasicBlock::iterator I,
514 unsigned DstReg = I->getOperand(0).getReg();
515 unsigned SrcReg = I->getOperand(1).getReg();
516 unsigned N = I->getOperand(2).getImm();
517 DebugLoc dl = I->getDebugLoc();
519 assert(N < 2 && "Invalid immediate");
520 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
521 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
523 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
524 // in MipsSEFrameLowering.cpp.
525 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
527 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
528 // in MipsSEFrameLowering.cpp.
529 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg()));
531 if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) {
532 // FIXME: Strictly speaking MFHC1 only reads the top 32-bits however, we
533 // claim to read the whole 64-bits as part of a white lie used to
534 // temporarily work around a widespread bug in the -mfp64 support.
535 // The problem is that none of the 32-bit fpu ops mention the fact
536 // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
537 // requires a major overhaul of the FPU implementation which can't
538 // be done right now due to time constraints.
539 // MFHC1 is one of two instructions that are affected since they are
540 // the only instructions that don't read the lower 32-bits.
541 // We therefore pretend that it reads the bottom 32-bits to
542 // artificially create a dependency and prevent the scheduler
543 // changing the behaviour of the code.
544 BuildMI(MBB, I, dl, get(FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32), DstReg)
547 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
550 void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
551 MachineBasicBlock::iterator I,
553 unsigned DstReg = I->getOperand(0).getReg();
554 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
555 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
556 DebugLoc dl = I->getDebugLoc();
557 const TargetRegisterInfo &TRI = getRegisterInfo();
559 // When mthc1 is available, use:
563 // Otherwise, for O32 FPXX ABI:
564 // spill + reload via ldc1
565 // This case is handled by the frame lowering code.
567 // Otherwise, for FP32:
571 // The case where dmtc1 is available doesn't need to be handled here
572 // because it never creates a BuildPairF64 node.
574 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
575 // in MipsSEFrameLowering.cpp.
576 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
578 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
579 // in MipsSEFrameLowering.cpp.
580 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg()));
582 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
585 if (Subtarget.hasMTHC1()) {
586 // FIXME: The .addReg(DstReg) is a white lie used to temporarily work
587 // around a widespread bug in the -mfp64 support.
588 // The problem is that none of the 32-bit fpu ops mention the fact
589 // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
590 // requires a major overhaul of the FPU implementation which can't
591 // be done right now due to time constraints.
592 // MTHC1 is one of two instructions that are affected since they are
593 // the only instructions that don't read the lower 32-bits.
594 // We therefore pretend that it reads the bottom 32-bits to
595 // artificially create a dependency and prevent the scheduler
596 // changing the behaviour of the code.
597 BuildMI(MBB, I, dl, get(FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32), DstReg)
600 } else if (Subtarget.isABI_FPXX())
601 llvm_unreachable("BuildPairF64 not expanded in frame lowering code!");
603 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
607 void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
608 MachineBasicBlock::iterator I) const {
609 // This pseudo instruction is generated as part of the lowering of
610 // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
611 // indirect jump to TargetReg
612 unsigned ADDU = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu;
613 unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP;
614 unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA;
615 unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9;
616 unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
617 unsigned OffsetReg = I->getOperand(0).getReg();
618 unsigned TargetReg = I->getOperand(1).getReg();
620 // addu $ra, $v0, $zero
621 // addu $sp, $sp, $v1
622 // jr $ra (via RetRA)
623 const TargetMachine &TM = MBB.getParent()->getTarget();
624 if (TM.getRelocationModel() == Reloc::PIC_)
625 BuildMI(MBB, I, I->getDebugLoc(),
626 TM.getSubtargetImpl()->getInstrInfo()->get(ADDU), T9)
629 BuildMI(MBB, I, I->getDebugLoc(),
630 TM.getSubtargetImpl()->getInstrInfo()->get(ADDU), RA)
633 BuildMI(MBB, I, I->getDebugLoc(),
634 TM.getSubtargetImpl()->getInstrInfo()->get(ADDU), SP)
640 const MipsInstrInfo *llvm::createMipsSEInstrInfo(const MipsSubtarget &STI) {
641 return new MipsSEInstrInfo(STI);