1 //===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsSEInstrInfo.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsMachineFunction.h"
17 #include "MipsTargetMachine.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/TargetRegistry.h"
27 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
28 cl::desc("Expand double precision loads and "
29 "stores to their single precision "
32 MipsSEInstrInfo::MipsSEInstrInfo(MipsTargetMachine &tm)
34 tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J),
35 RI(*tm.getSubtargetImpl()),
36 IsN64(tm.getSubtarget<MipsSubtarget>().isABI_N64()) {}
38 const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
42 /// isLoadFromStackSlot - If the specified machine instruction is a direct
43 /// load from a stack slot, return the virtual or physical register number of
44 /// the destination along with the FrameIndex of the loaded stack slot. If
45 /// not, return 0. This predicate must return 0 if the instruction has
46 /// any side effects other than loading from the stack slot.
47 unsigned MipsSEInstrInfo::
48 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
50 unsigned Opc = MI->getOpcode();
52 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
53 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
54 if ((MI->getOperand(1).isFI()) && // is a stack slot
55 (MI->getOperand(2).isImm()) && // the imm is zero
56 (isZeroImm(MI->getOperand(2)))) {
57 FrameIndex = MI->getOperand(1).getIndex();
58 return MI->getOperand(0).getReg();
65 /// isStoreToStackSlot - If the specified machine instruction is a direct
66 /// store to a stack slot, return the virtual or physical register number of
67 /// the source reg along with the FrameIndex of the loaded stack slot. If
68 /// not, return 0. This predicate must return 0 if the instruction has
69 /// any side effects other than storing to the stack slot.
70 unsigned MipsSEInstrInfo::
71 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
73 unsigned Opc = MI->getOpcode();
75 if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
76 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
77 if ((MI->getOperand(1).isFI()) && // is a stack slot
78 (MI->getOperand(2).isImm()) && // the imm is zero
79 (isZeroImm(MI->getOperand(2)))) {
80 FrameIndex = MI->getOperand(1).getIndex();
81 return MI->getOperand(0).getReg();
87 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
88 MachineBasicBlock::iterator I, DebugLoc DL,
89 unsigned DestReg, unsigned SrcReg,
91 unsigned Opc = 0, ZeroReg = 0;
93 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
94 if (Mips::GPR32RegClass.contains(SrcReg))
95 Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
96 else if (Mips::CCRRegClass.contains(SrcReg))
98 else if (Mips::FGR32RegClass.contains(SrcReg))
100 else if (Mips::HI32RegClass.contains(SrcReg))
101 Opc = Mips::MFHI, SrcReg = 0;
102 else if (Mips::LO32RegClass.contains(SrcReg))
103 Opc = Mips::MFLO, SrcReg = 0;
104 else if (Mips::HI32DSPRegClass.contains(SrcReg))
105 Opc = Mips::MFHI_DSP;
106 else if (Mips::LO32DSPRegClass.contains(SrcReg))
107 Opc = Mips::MFLO_DSP;
108 else if (Mips::DSPCCRegClass.contains(SrcReg)) {
109 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
110 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
114 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
115 if (Mips::CCRRegClass.contains(DestReg))
117 else if (Mips::FGR32RegClass.contains(DestReg))
119 else if (Mips::HI32RegClass.contains(DestReg))
120 Opc = Mips::MTHI, DestReg = 0;
121 else if (Mips::LO32RegClass.contains(DestReg))
122 Opc = Mips::MTLO, DestReg = 0;
123 else if (Mips::HI32DSPRegClass.contains(DestReg))
124 Opc = Mips::MTHI_DSP;
125 else if (Mips::LO32DSPRegClass.contains(DestReg))
126 Opc = Mips::MTLO_DSP;
127 else if (Mips::DSPCCRegClass.contains(DestReg)) {
128 BuildMI(MBB, I, DL, get(Mips::WRDSP))
129 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
130 .addReg(DestReg, RegState::ImplicitDefine);
134 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
136 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
137 Opc = Mips::FMOV_D32;
138 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
139 Opc = Mips::FMOV_D64;
140 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
141 if (Mips::GPR64RegClass.contains(SrcReg))
142 Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
143 else if (Mips::HI64RegClass.contains(SrcReg))
144 Opc = Mips::MFHI64, SrcReg = 0;
145 else if (Mips::LO64RegClass.contains(SrcReg))
146 Opc = Mips::MFLO64, SrcReg = 0;
147 else if (Mips::FGR64RegClass.contains(SrcReg))
150 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
151 if (Mips::HI64RegClass.contains(DestReg))
152 Opc = Mips::MTHI64, DestReg = 0;
153 else if (Mips::LO64RegClass.contains(DestReg))
154 Opc = Mips::MTLO64, DestReg = 0;
155 else if (Mips::FGR64RegClass.contains(DestReg))
159 assert(Opc && "Cannot copy registers");
161 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
164 MIB.addReg(DestReg, RegState::Define);
167 MIB.addReg(SrcReg, getKillRegState(KillSrc));
173 void MipsSEInstrInfo::
174 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
175 unsigned SrcReg, bool isKill, int FI,
176 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
177 int64_t Offset) const {
179 if (I != MBB.end()) DL = I->getDebugLoc();
180 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
184 if (Mips::GPR32RegClass.hasSubClassEq(RC))
186 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
188 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
189 Opc = Mips::STORE_ACC64;
190 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
191 Opc = Mips::STORE_ACC64DSP;
192 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
193 Opc = Mips::STORE_ACC128;
194 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
195 Opc = Mips::STORE_CCOND_DSP;
196 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
198 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
200 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
203 assert(Opc && "Register class not handled!");
204 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
205 .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
208 void MipsSEInstrInfo::
209 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
210 unsigned DestReg, int FI, const TargetRegisterClass *RC,
211 const TargetRegisterInfo *TRI, int64_t Offset) const {
213 if (I != MBB.end()) DL = I->getDebugLoc();
214 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
217 if (Mips::GPR32RegClass.hasSubClassEq(RC))
219 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
221 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
222 Opc = Mips::LOAD_ACC64;
223 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
224 Opc = Mips::LOAD_ACC64DSP;
225 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
226 Opc = Mips::LOAD_ACC128;
227 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
228 Opc = Mips::LOAD_CCOND_DSP;
229 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
231 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
233 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
236 assert(Opc && "Register class not handled!");
237 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
241 bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
242 MachineBasicBlock &MBB = *MI->getParent();
244 switch(MI->getDesc().getOpcode()) {
248 expandRetRA(MBB, MI, Mips::RET);
250 case Mips::PseudoCVT_S_W:
251 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
253 case Mips::PseudoCVT_D32_W:
254 expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false);
256 case Mips::PseudoCVT_S_L:
257 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
259 case Mips::PseudoCVT_D64_W:
260 expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true);
262 case Mips::PseudoCVT_D64_L:
263 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
265 case Mips::BuildPairF64:
266 expandBuildPairF64(MBB, MI, false);
268 case Mips::BuildPairF64_64:
269 expandBuildPairF64(MBB, MI, true);
271 case Mips::ExtractElementF64:
272 expandExtractElementF64(MBB, MI, false);
274 case Mips::ExtractElementF64_64:
275 expandExtractElementF64(MBB, MI, true);
277 case Mips::PseudoLDC1:
278 expandDPLoadStore(MBB, MI, Mips::LDC1, Mips::LWC1);
280 case Mips::PseudoSDC1:
281 expandDPLoadStore(MBB, MI, Mips::SDC1, Mips::SWC1);
283 case Mips::MIPSeh_return32:
284 case Mips::MIPSeh_return64:
285 expandEhReturn(MBB, MI);
293 /// getOppositeBranchOpc - Return the inverse of the specified
294 /// opcode, e.g. turning BEQ to BNE.
295 unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
297 default: llvm_unreachable("Illegal opcode!");
298 case Mips::BEQ: return Mips::BNE;
299 case Mips::BNE: return Mips::BEQ;
300 case Mips::BGTZ: return Mips::BLEZ;
301 case Mips::BGEZ: return Mips::BLTZ;
302 case Mips::BLTZ: return Mips::BGEZ;
303 case Mips::BLEZ: return Mips::BGTZ;
304 case Mips::BEQ64: return Mips::BNE64;
305 case Mips::BNE64: return Mips::BEQ64;
306 case Mips::BGTZ64: return Mips::BLEZ64;
307 case Mips::BGEZ64: return Mips::BLTZ64;
308 case Mips::BLTZ64: return Mips::BGEZ64;
309 case Mips::BLEZ64: return Mips::BGTZ64;
310 case Mips::BC1T: return Mips::BC1F;
311 case Mips::BC1F: return Mips::BC1T;
315 /// Adjust SP by Amount bytes.
316 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
317 MachineBasicBlock &MBB,
318 MachineBasicBlock::iterator I) const {
319 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
320 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
321 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
322 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
324 if (isInt<16>(Amount))// addi sp, sp, amount
325 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
326 else { // Expand immediate that doesn't fit in 16-bit.
327 unsigned Reg = loadImmediate(Amount, MBB, I, DL, 0);
328 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill);
332 /// This function generates the sequence of instructions needed to get the
333 /// result of adding register REG and immediate IMM.
335 MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
336 MachineBasicBlock::iterator II, DebugLoc DL,
337 unsigned *NewImm) const {
338 MipsAnalyzeImmediate AnalyzeImm;
339 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
340 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
341 unsigned Size = STI.isABI_N64() ? 64 : 32;
342 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
343 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
344 const TargetRegisterClass *RC = STI.isABI_N64() ?
345 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
346 bool LastInstrIsADDiu = NewImm;
348 const MipsAnalyzeImmediate::InstSeq &Seq =
349 AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
350 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
352 assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
354 // The first instruction can be a LUi, which is different from other
355 // instructions (ADDiu, ORI and SLL) in that it does not have a register
357 unsigned Reg = RegInfo.createVirtualRegister(RC);
359 if (Inst->Opc == LUi)
360 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
362 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
363 .addImm(SignExtend64<16>(Inst->ImmOpnd));
365 // Build the remaining instructions in Seq.
366 for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
367 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
368 .addImm(SignExtend64<16>(Inst->ImmOpnd));
370 if (LastInstrIsADDiu)
371 *NewImm = Inst->ImmOpnd;
376 unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
377 return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ ||
378 Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ ||
379 Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 ||
380 Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
381 Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B ||
386 void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
387 MachineBasicBlock::iterator I,
388 unsigned Opc) const {
389 BuildMI(MBB, I, I->getDebugLoc(), get(Opc)).addReg(Mips::RA);
392 std::pair<bool, bool>
393 MipsSEInstrInfo::compareOpndSize(unsigned Opc,
394 const MachineFunction &MF) const {
395 const MCInstrDesc &Desc = get(Opc);
396 assert(Desc.NumOperands == 2 && "Unary instruction expected.");
397 const MipsRegisterInfo *RI = &getRegisterInfo();
398 unsigned DstRegSize = getRegClass(Desc, 0, RI, MF)->getSize();
399 unsigned SrcRegSize = getRegClass(Desc, 1, RI, MF)->getSize();
401 return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
404 void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
405 MachineBasicBlock::iterator I,
406 unsigned CvtOpc, unsigned MovOpc,
408 const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
409 const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
410 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
411 unsigned KillSrc = getKillRegState(Src.isKill());
412 DebugLoc DL = I->getDebugLoc();
413 bool DstIsLarger, SrcIsLarger;
415 tie(DstIsLarger, SrcIsLarger) = compareOpndSize(CvtOpc, *MBB.getParent());
418 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
421 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
423 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
424 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
427 void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
428 MachineBasicBlock::iterator I,
430 unsigned DstReg = I->getOperand(0).getReg();
431 unsigned SrcReg = I->getOperand(1).getReg();
432 unsigned N = I->getOperand(2).getImm();
433 DebugLoc dl = I->getDebugLoc();
435 assert(N < 2 && "Invalid immediate");
436 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
437 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
439 if (SubIdx == Mips::sub_hi && FP64)
440 BuildMI(MBB, I, dl, get(Mips::MFHC1), DstReg).addReg(SubReg);
442 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
445 void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
446 MachineBasicBlock::iterator I,
448 unsigned DstReg = I->getOperand(0).getReg();
449 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
450 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
451 DebugLoc dl = I->getDebugLoc();
452 const TargetRegisterInfo &TRI = getRegisterInfo();
456 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
460 BuildMI(MBB, I, dl, get(Mips::MTHC1), TRI.getSubReg(DstReg, Mips::sub_hi))
463 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
467 /// Add 4 to the displacement of operand MO.
468 static void fixDisp(MachineOperand &MO) {
469 switch (MO.getType()) {
471 llvm_unreachable("Unhandled operand type.");
472 case MachineOperand::MO_Immediate:
473 MO.setImm(MO.getImm() + 4);
475 case MachineOperand::MO_GlobalAddress:
476 case MachineOperand::MO_ConstantPoolIndex:
477 case MachineOperand::MO_BlockAddress:
478 case MachineOperand::MO_TargetIndex:
479 case MachineOperand::MO_ExternalSymbol:
480 MO.setOffset(MO.getOffset() + 4);
485 void MipsSEInstrInfo::expandDPLoadStore(MachineBasicBlock &MBB,
486 MachineBasicBlock::iterator I,
487 unsigned OpcD, unsigned OpcS) const {
488 // If NoDPLoadStore is false, just change the opcode.
489 if (!NoDPLoadStore) {
490 genInstrWithNewOpc(OpcD, I);
494 // Expand a double precision FP load or store to two single precision
497 const TargetRegisterInfo &TRI = getRegisterInfo();
498 const MachineOperand &ValReg = I->getOperand(0);
499 unsigned LoReg = TRI.getSubReg(ValReg.getReg(), Mips::sub_lo);
500 unsigned HiReg = TRI.getSubReg(ValReg.getReg(), Mips::sub_hi);
502 if (!TM.getSubtarget<MipsSubtarget>().isLittle())
503 std::swap(LoReg, HiReg);
505 // Create an instruction which loads from or stores to the lower memory
507 MachineInstrBuilder MIB = genInstrWithNewOpc(OpcS, I);
508 MIB->getOperand(0).setReg(LoReg);
510 // Create an instruction which loads from or stores to the higher memory
512 MIB = genInstrWithNewOpc(OpcS, I);
513 MIB->getOperand(0).setReg(HiReg);
514 fixDisp(MIB->getOperand(2));
517 void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
518 MachineBasicBlock::iterator I) const {
519 // This pseudo instruction is generated as part of the lowering of
520 // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
521 // indirect jump to TargetReg
522 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
523 unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
524 unsigned JR = STI.isABI_N64() ? Mips::JR64 : Mips::JR;
525 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
526 unsigned RA = STI.isABI_N64() ? Mips::RA_64 : Mips::RA;
527 unsigned T9 = STI.isABI_N64() ? Mips::T9_64 : Mips::T9;
528 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
529 unsigned OffsetReg = I->getOperand(0).getReg();
530 unsigned TargetReg = I->getOperand(1).getReg();
532 // addu $ra, $v0, $zero
533 // addu $sp, $sp, $v1
535 if (TM.getRelocationModel() == Reloc::PIC_)
536 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), T9)
537 .addReg(TargetReg).addReg(ZERO);
538 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), RA)
539 .addReg(TargetReg).addReg(ZERO);
540 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), SP)
541 .addReg(SP).addReg(OffsetReg);
542 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(JR)).addReg(RA);
545 const MipsInstrInfo *llvm::createMipsSEInstrInfo(MipsTargetMachine &TM) {
546 return new MipsSEInstrInfo(TM);