1 //===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsTargetLowering specialized for mips32/64.
12 //===----------------------------------------------------------------------===//
13 #define DEBUG_TYPE "mips-isel"
14 #include "MipsSEISelLowering.h"
15 #include "MipsRegisterInfo.h"
16 #include "MipsTargetMachine.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/IR/Intrinsics.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Target/TargetInstrInfo.h"
27 EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
28 cl::desc("MIPS: Enable tail calls."), cl::init(false));
30 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
31 cl::desc("Expand double precision loads and "
32 "stores to their single precision "
35 MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
36 : MipsTargetLowering(TM) {
37 // Set up the register classes
38 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
41 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
43 if (Subtarget->hasDSP() || Subtarget->hasMSA()) {
44 // Expand all truncating stores and extending loads.
45 unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
46 unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
48 for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
49 for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
50 setTruncStoreAction((MVT::SimpleValueType)VT0,
51 (MVT::SimpleValueType)VT1, Expand);
53 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
54 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
55 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
59 if (Subtarget->hasDSP()) {
60 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
62 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
63 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
65 // Expand all builtin opcodes.
66 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
67 setOperationAction(Opc, VecTys[i], Expand);
69 setOperationAction(ISD::ADD, VecTys[i], Legal);
70 setOperationAction(ISD::SUB, VecTys[i], Legal);
71 setOperationAction(ISD::LOAD, VecTys[i], Legal);
72 setOperationAction(ISD::STORE, VecTys[i], Legal);
73 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
76 setTargetDAGCombine(ISD::SHL);
77 setTargetDAGCombine(ISD::SRA);
78 setTargetDAGCombine(ISD::SRL);
79 setTargetDAGCombine(ISD::SETCC);
80 setTargetDAGCombine(ISD::VSELECT);
83 if (Subtarget->hasDSPR2())
84 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
86 if (Subtarget->hasMSA()) {
87 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
88 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
89 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
90 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
91 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
92 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
93 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
95 setTargetDAGCombine(ISD::AND);
96 setTargetDAGCombine(ISD::OR);
97 setTargetDAGCombine(ISD::SRA);
98 setTargetDAGCombine(ISD::VSELECT);
99 setTargetDAGCombine(ISD::XOR);
102 if (!Subtarget->mipsSEUsesSoftFloat()) {
103 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
105 // When dealing with single precision only, use libcalls
106 if (!Subtarget->isSingleFloat()) {
107 if (Subtarget->isFP64bit())
108 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
110 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
114 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
115 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
116 setOperationAction(ISD::MULHS, MVT::i32, Custom);
117 setOperationAction(ISD::MULHU, MVT::i32, Custom);
120 setOperationAction(ISD::MULHS, MVT::i64, Custom);
121 setOperationAction(ISD::MULHU, MVT::i64, Custom);
122 setOperationAction(ISD::MUL, MVT::i64, Custom);
125 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
126 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
128 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
129 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
130 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
131 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
132 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
133 setOperationAction(ISD::LOAD, MVT::i32, Custom);
134 setOperationAction(ISD::STORE, MVT::i32, Custom);
136 setTargetDAGCombine(ISD::ADDE);
137 setTargetDAGCombine(ISD::SUBE);
138 setTargetDAGCombine(ISD::MUL);
140 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
141 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
142 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
145 setOperationAction(ISD::LOAD, MVT::f64, Custom);
146 setOperationAction(ISD::STORE, MVT::f64, Custom);
149 computeRegisterProperties();
152 const MipsTargetLowering *
153 llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
154 return new MipsSETargetLowering(TM);
157 // Enable MSA support for the given integer type and Register class.
158 void MipsSETargetLowering::
159 addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
160 addRegisterClass(Ty, RC);
162 // Expand all builtin opcodes.
163 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
164 setOperationAction(Opc, Ty, Expand);
166 setOperationAction(ISD::BITCAST, Ty, Legal);
167 setOperationAction(ISD::LOAD, Ty, Legal);
168 setOperationAction(ISD::STORE, Ty, Legal);
169 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
170 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
171 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
173 setOperationAction(ISD::ADD, Ty, Legal);
174 setOperationAction(ISD::AND, Ty, Legal);
175 setOperationAction(ISD::CTLZ, Ty, Legal);
176 setOperationAction(ISD::CTPOP, Ty, Legal);
177 setOperationAction(ISD::MUL, Ty, Legal);
178 setOperationAction(ISD::OR, Ty, Legal);
179 setOperationAction(ISD::SDIV, Ty, Legal);
180 setOperationAction(ISD::SREM, Ty, Legal);
181 setOperationAction(ISD::SHL, Ty, Legal);
182 setOperationAction(ISD::SRA, Ty, Legal);
183 setOperationAction(ISD::SRL, Ty, Legal);
184 setOperationAction(ISD::SUB, Ty, Legal);
185 setOperationAction(ISD::UDIV, Ty, Legal);
186 setOperationAction(ISD::UREM, Ty, Legal);
187 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom);
188 setOperationAction(ISD::VSELECT, Ty, Legal);
189 setOperationAction(ISD::XOR, Ty, Legal);
191 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
192 setOperationAction(ISD::FP_TO_SINT, Ty, Legal);
193 setOperationAction(ISD::FP_TO_UINT, Ty, Legal);
194 setOperationAction(ISD::SINT_TO_FP, Ty, Legal);
195 setOperationAction(ISD::UINT_TO_FP, Ty, Legal);
198 setOperationAction(ISD::SETCC, Ty, Legal);
199 setCondCodeAction(ISD::SETNE, Ty, Expand);
200 setCondCodeAction(ISD::SETGE, Ty, Expand);
201 setCondCodeAction(ISD::SETGT, Ty, Expand);
202 setCondCodeAction(ISD::SETUGE, Ty, Expand);
203 setCondCodeAction(ISD::SETUGT, Ty, Expand);
206 // Enable MSA support for the given floating-point type and Register class.
207 void MipsSETargetLowering::
208 addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
209 addRegisterClass(Ty, RC);
211 // Expand all builtin opcodes.
212 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
213 setOperationAction(Opc, Ty, Expand);
215 setOperationAction(ISD::LOAD, Ty, Legal);
216 setOperationAction(ISD::STORE, Ty, Legal);
217 setOperationAction(ISD::BITCAST, Ty, Legal);
218 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
219 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
220 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
222 if (Ty != MVT::v8f16) {
223 setOperationAction(ISD::FABS, Ty, Legal);
224 setOperationAction(ISD::FADD, Ty, Legal);
225 setOperationAction(ISD::FDIV, Ty, Legal);
226 setOperationAction(ISD::FEXP2, Ty, Legal);
227 setOperationAction(ISD::FLOG2, Ty, Legal);
228 setOperationAction(ISD::FMA, Ty, Legal);
229 setOperationAction(ISD::FMUL, Ty, Legal);
230 setOperationAction(ISD::FRINT, Ty, Legal);
231 setOperationAction(ISD::FSQRT, Ty, Legal);
232 setOperationAction(ISD::FSUB, Ty, Legal);
233 setOperationAction(ISD::VSELECT, Ty, Legal);
235 setOperationAction(ISD::SETCC, Ty, Legal);
236 setCondCodeAction(ISD::SETOGE, Ty, Expand);
237 setCondCodeAction(ISD::SETOGT, Ty, Expand);
238 setCondCodeAction(ISD::SETUGE, Ty, Expand);
239 setCondCodeAction(ISD::SETUGT, Ty, Expand);
240 setCondCodeAction(ISD::SETGE, Ty, Expand);
241 setCondCodeAction(ISD::SETGT, Ty, Expand);
246 MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
247 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
260 SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
261 SelectionDAG &DAG) const {
262 switch(Op.getOpcode()) {
263 case ISD::LOAD: return lowerLOAD(Op, DAG);
264 case ISD::STORE: return lowerSTORE(Op, DAG);
265 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
266 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
267 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
268 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
269 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
270 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
271 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
273 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
274 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
275 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
276 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
277 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
278 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG);
281 return MipsTargetLowering::LowerOperation(Op, DAG);
285 // Transforms a subgraph in CurDAG if the following pattern is found:
286 // (addc multLo, Lo0), (adde multHi, Hi0),
288 // multHi/Lo: product of multiplication
289 // Lo0: initial value of Lo register
290 // Hi0: initial value of Hi register
291 // Return true if pattern matching was successful.
292 static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
293 // ADDENode's second operand must be a flag output of an ADDC node in order
294 // for the matching to be successful.
295 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
297 if (ADDCNode->getOpcode() != ISD::ADDC)
300 SDValue MultHi = ADDENode->getOperand(0);
301 SDValue MultLo = ADDCNode->getOperand(0);
302 SDNode *MultNode = MultHi.getNode();
303 unsigned MultOpc = MultHi.getOpcode();
305 // MultHi and MultLo must be generated by the same node,
306 if (MultLo.getNode() != MultNode)
309 // and it must be a multiplication.
310 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
313 // MultLo amd MultHi must be the first and second output of MultNode
315 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
318 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
319 // of the values of MultNode, in which case MultNode will be removed in later
321 // If there exist users other than ADDENode or ADDCNode, this function returns
322 // here, which will result in MultNode being mapped to a single MULT
323 // instruction node rather than a pair of MULT and MADD instructions being
325 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
330 // Initialize accumulator.
331 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
332 ADDCNode->getOperand(1),
333 ADDENode->getOperand(1));
335 // create MipsMAdd(u) node
336 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
338 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
339 MultNode->getOperand(0),// Factor 0
340 MultNode->getOperand(1),// Factor 1
343 // replace uses of adde and addc here
344 if (!SDValue(ADDCNode, 0).use_empty()) {
345 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
346 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
348 if (!SDValue(ADDENode, 0).use_empty()) {
349 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
350 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
357 // Transforms a subgraph in CurDAG if the following pattern is found:
358 // (addc Lo0, multLo), (sube Hi0, multHi),
360 // multHi/Lo: product of multiplication
361 // Lo0: initial value of Lo register
362 // Hi0: initial value of Hi register
363 // Return true if pattern matching was successful.
364 static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
365 // SUBENode's second operand must be a flag output of an SUBC node in order
366 // for the matching to be successful.
367 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
369 if (SUBCNode->getOpcode() != ISD::SUBC)
372 SDValue MultHi = SUBENode->getOperand(1);
373 SDValue MultLo = SUBCNode->getOperand(1);
374 SDNode *MultNode = MultHi.getNode();
375 unsigned MultOpc = MultHi.getOpcode();
377 // MultHi and MultLo must be generated by the same node,
378 if (MultLo.getNode() != MultNode)
381 // and it must be a multiplication.
382 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
385 // MultLo amd MultHi must be the first and second output of MultNode
387 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
390 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
391 // of the values of MultNode, in which case MultNode will be removed in later
393 // If there exist users other than SUBENode or SUBCNode, this function returns
394 // here, which will result in MultNode being mapped to a single MULT
395 // instruction node rather than a pair of MULT and MSUB instructions being
397 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
402 // Initialize accumulator.
403 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
404 SUBCNode->getOperand(0),
405 SUBENode->getOperand(0));
407 // create MipsSub(u) node
408 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
410 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
411 MultNode->getOperand(0),// Factor 0
412 MultNode->getOperand(1),// Factor 1
415 // replace uses of sube and subc here
416 if (!SDValue(SUBCNode, 0).use_empty()) {
417 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub);
418 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
420 if (!SDValue(SUBENode, 0).use_empty()) {
421 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MSub);
422 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
428 static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
429 TargetLowering::DAGCombinerInfo &DCI,
430 const MipsSubtarget *Subtarget) {
431 if (DCI.isBeforeLegalize())
434 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
436 return SDValue(N, 0);
441 // Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
443 // Performs the following transformations:
444 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
445 // sign/zero-extension is completely overwritten by the new one performed by
447 // - Removes redundant zero extensions performed by an ISD::AND.
448 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
449 TargetLowering::DAGCombinerInfo &DCI,
450 const MipsSubtarget *Subtarget) {
451 if (!Subtarget->hasMSA())
454 SDValue Op0 = N->getOperand(0);
455 SDValue Op1 = N->getOperand(1);
456 unsigned Op0Opcode = Op0->getOpcode();
458 // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
459 // where $d + 1 == 2^n and n == 32
460 // or $d + 1 == 2^n and n <= 32 and ZExt
461 // -> (MipsVExtractZExt $a, $b, $c)
462 if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
463 Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
464 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
469 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
471 if (Log2IfPositive <= 0)
472 return SDValue(); // Mask+1 is not a power of 2
474 SDValue Op0Op2 = Op0->getOperand(2);
475 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
476 unsigned ExtendTySize = ExtendTy.getSizeInBits();
477 unsigned Log2 = Log2IfPositive;
479 if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
480 Log2 == ExtendTySize) {
481 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
482 DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT,
483 Op0->getVTList(), Ops, Op0->getNumOperands());
491 // Determine if the specified node is a constant vector splat.
493 // Returns true and sets Imm if:
494 // * N is a ISD::BUILD_VECTOR representing a constant splat
496 // This function is quite similar to MipsSEDAGToDAGISel::selectVSplat. The
497 // differences are that it assumes the MSA has already been checked and the
498 // arbitrary requirement for a maximum of 32-bit integers isn't applied (and
499 // must not be in order for binsri.d to be selectable).
500 static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) {
501 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N.getNode());
506 APInt SplatValue, SplatUndef;
507 unsigned SplatBitSize;
510 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
519 // Perform combines where ISD::OR is the root node.
521 // Performs the following transformations:
522 // - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
523 // where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
525 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
526 TargetLowering::DAGCombinerInfo &DCI,
527 const MipsSubtarget *Subtarget) {
528 if (!Subtarget->hasMSA())
531 EVT Ty = N->getValueType(0);
533 if (!Ty.is128BitVector())
536 SDValue Op0 = N->getOperand(0);
537 SDValue Op1 = N->getOperand(1);
539 if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
540 SDValue Op0Op0 = Op0->getOperand(0);
541 SDValue Op0Op1 = Op0->getOperand(1);
542 SDValue Op1Op0 = Op1->getOperand(0);
543 SDValue Op1Op1 = Op1->getOperand(1);
544 bool IsLittleEndian = !Subtarget->isLittle();
546 SDValue IfSet, IfClr, Cond;
549 // If Op0Op0 is an appropriate mask, try to find it's inverse in either
550 // Op1Op0, or Op1Op1. Keep track of the Cond, IfSet, and IfClr nodes, while
552 // IfClr will be set if we find a valid match.
553 if (isVSplat(Op0Op0, Mask, IsLittleEndian)) {
557 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) && Mask == ~InvMask)
559 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) && Mask == ~InvMask)
563 // If IfClr is not yet set, and Op0Op1 is an appropriate mask, try the same
564 // thing again using this mask.
565 // IfClr will be set if we find a valid match.
566 if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) {
570 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) && Mask == ~InvMask)
572 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) && Mask == ~InvMask)
576 // At this point, IfClr will be set if we have a valid match.
577 if (!IfClr.getNode())
580 assert(Cond.getNode() && IfSet.getNode());
582 // Fold degenerate cases.
583 if (Mask.isAllOnesValue())
588 // Transform the DAG into an equivalent VSELECT.
589 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfClr, IfSet);
595 static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
596 TargetLowering::DAGCombinerInfo &DCI,
597 const MipsSubtarget *Subtarget) {
598 if (DCI.isBeforeLegalize())
601 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
603 return SDValue(N, 0);
608 static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
609 EVT ShiftTy, SelectionDAG &DAG) {
610 // Clear the upper (64 - VT.sizeInBits) bits.
611 C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
615 return DAG.getConstant(0, VT);
621 // If c is power of 2, return (shl x, log2(c)).
622 if (isPowerOf2_64(C))
623 return DAG.getNode(ISD::SHL, DL, VT, X,
624 DAG.getConstant(Log2_64(C), ShiftTy));
626 unsigned Log2Ceil = Log2_64_Ceil(C);
627 uint64_t Floor = 1LL << Log2_64(C);
628 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
630 // If |c - floor_c| <= |c - ceil_c|,
631 // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
632 // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
633 if (C - Floor <= Ceil - C) {
634 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
635 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
636 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
639 // If |c - floor_c| > |c - ceil_c|,
640 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
641 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
642 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
643 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
646 static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
647 const TargetLowering::DAGCombinerInfo &DCI,
648 const MipsSETargetLowering *TL) {
649 EVT VT = N->getValueType(0);
651 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
653 return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N),
654 VT, TL->getScalarShiftAmountTy(VT), DAG);
656 return SDValue(N, 0);
659 static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
661 const MipsSubtarget *Subtarget) {
662 // See if this is a vector splat immediate node.
663 APInt SplatValue, SplatUndef;
664 unsigned SplatBitSize;
666 unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
667 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
670 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
671 EltSize, !Subtarget->isLittle()) ||
672 (SplatBitSize != EltSize) ||
673 (SplatValue.getZExtValue() >= EltSize))
676 return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
677 DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
680 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
681 TargetLowering::DAGCombinerInfo &DCI,
682 const MipsSubtarget *Subtarget) {
683 EVT Ty = N->getValueType(0);
685 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
688 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
691 // Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
692 // constant splats into MipsISD::SHRA_DSP for DSPr2.
694 // Performs the following transformations:
695 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
696 // sign/zero-extension is completely overwritten by the new one performed by
697 // the ISD::SRA and ISD::SHL nodes.
698 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
701 // See performDSPShiftCombine for more information about the transformation
703 static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
704 TargetLowering::DAGCombinerInfo &DCI,
705 const MipsSubtarget *Subtarget) {
706 EVT Ty = N->getValueType(0);
708 if (Subtarget->hasMSA()) {
709 SDValue Op0 = N->getOperand(0);
710 SDValue Op1 = N->getOperand(1);
712 // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
713 // where $d + sizeof($c) == 32
714 // or $d + sizeof($c) <= 32 and SExt
715 // -> (MipsVExtractSExt $a, $b, $c)
716 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
717 SDValue Op0Op0 = Op0->getOperand(0);
718 ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
723 if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
724 Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT)
727 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
728 unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
730 if (TotalBits == 32 ||
731 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
733 SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
734 Op0Op0->getOperand(2) };
735 DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT,
736 Op0Op0->getVTList(), Ops, Op0Op0->getNumOperands());
742 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
745 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
749 static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
750 TargetLowering::DAGCombinerInfo &DCI,
751 const MipsSubtarget *Subtarget) {
752 EVT Ty = N->getValueType(0);
754 if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
757 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
760 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
761 bool IsV216 = (Ty == MVT::v2i16);
765 case ISD::SETNE: return true;
769 case ISD::SETGE: return IsV216;
773 case ISD::SETUGE: return !IsV216;
774 default: return false;
778 static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
779 EVT Ty = N->getValueType(0);
781 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
784 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
787 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
788 N->getOperand(1), N->getOperand(2));
791 static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
792 EVT Ty = N->getValueType(0);
794 if (Ty.is128BitVector() && Ty.isInteger()) {
795 // Try the following combines:
796 // (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b)
797 // (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b)
798 // (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b)
799 // (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b)
800 // (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b)
801 // (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b)
802 // (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b)
803 // (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b)
804 // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but
805 // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the
807 SDValue Op0 = N->getOperand(0);
809 if (Op0->getOpcode() != ISD::SETCC)
812 ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get();
815 if (CondCode == ISD::SETLT || CondCode == ISD::SETLE)
817 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE)
822 SDValue Op1 = N->getOperand(1);
823 SDValue Op2 = N->getOperand(2);
824 SDValue Op0Op0 = Op0->getOperand(0);
825 SDValue Op0Op1 = Op0->getOperand(1);
827 if (Op1 == Op0Op0 && Op2 == Op0Op1)
828 return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N),
830 else if (Op1 == Op0Op1 && Op2 == Op0Op0)
831 return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N),
833 } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) {
834 SDValue SetCC = N->getOperand(0);
836 if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
839 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
840 SetCC.getOperand(0), SetCC.getOperand(1),
841 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
847 static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
848 const MipsSubtarget *Subtarget) {
849 EVT Ty = N->getValueType(0);
851 if (Subtarget->hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
852 // Try the following combines:
853 // (xor (or $a, $b), (build_vector allones))
854 // (xor (or $a, $b), (bitcast (build_vector allones)))
855 SDValue Op0 = N->getOperand(0);
856 SDValue Op1 = N->getOperand(1);
859 if (ISD::isBuildVectorAllOnes(Op0.getNode()))
861 else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
866 if (NotOp->getOpcode() == ISD::OR)
867 return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
868 NotOp->getOperand(1));
875 MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
876 SelectionDAG &DAG = DCI.DAG;
879 switch (N->getOpcode()) {
881 return performADDECombine(N, DAG, DCI, Subtarget);
883 Val = performANDCombine(N, DAG, DCI, Subtarget);
886 Val = performORCombine(N, DAG, DCI, Subtarget);
889 return performSUBECombine(N, DAG, DCI, Subtarget);
891 return performMULCombine(N, DAG, DCI, this);
893 return performSHLCombine(N, DAG, DCI, Subtarget);
895 return performSRACombine(N, DAG, DCI, Subtarget);
897 return performSRLCombine(N, DAG, DCI, Subtarget);
899 return performVSELECTCombine(N, DAG);
901 Val = performXORCombine(N, DAG, Subtarget);
904 Val = performSETCCCombine(N, DAG);
909 DEBUG(dbgs() << "\nMipsSE DAG Combine:\n";
910 N->printrWithDepth(dbgs(), &DAG);
912 Val.getNode()->printrWithDepth(dbgs(), &DAG);
917 return MipsTargetLowering::PerformDAGCombine(N, DCI);
921 MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
922 MachineBasicBlock *BB) const {
923 switch (MI->getOpcode()) {
925 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
926 case Mips::BPOSGE32_PSEUDO:
927 return emitBPOSGE32(MI, BB);
928 case Mips::SNZ_B_PSEUDO:
929 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
930 case Mips::SNZ_H_PSEUDO:
931 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
932 case Mips::SNZ_W_PSEUDO:
933 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
934 case Mips::SNZ_D_PSEUDO:
935 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
936 case Mips::SNZ_V_PSEUDO:
937 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
938 case Mips::SZ_B_PSEUDO:
939 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
940 case Mips::SZ_H_PSEUDO:
941 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
942 case Mips::SZ_W_PSEUDO:
943 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
944 case Mips::SZ_D_PSEUDO:
945 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
946 case Mips::SZ_V_PSEUDO:
947 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
948 case Mips::COPY_FW_PSEUDO:
949 return emitCOPY_FW(MI, BB);
950 case Mips::COPY_FD_PSEUDO:
951 return emitCOPY_FD(MI, BB);
952 case Mips::INSERT_FW_PSEUDO:
953 return emitINSERT_FW(MI, BB);
954 case Mips::INSERT_FD_PSEUDO:
955 return emitINSERT_FD(MI, BB);
956 case Mips::FILL_FW_PSEUDO:
957 return emitFILL_FW(MI, BB);
958 case Mips::FILL_FD_PSEUDO:
959 return emitFILL_FD(MI, BB);
960 case Mips::FEXP2_W_1_PSEUDO:
961 return emitFEXP2_W_1(MI, BB);
962 case Mips::FEXP2_D_1_PSEUDO:
963 return emitFEXP2_D_1(MI, BB);
967 bool MipsSETargetLowering::
968 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
969 unsigned NextStackOffset,
970 const MipsFunctionInfo& FI) const {
971 if (!EnableMipsTailCalls)
974 // Return false if either the callee or caller has a byval argument.
975 if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
978 // Return true if the callee's argument area is no larger than the
980 return NextStackOffset <= FI.getIncomingArgSize();
983 void MipsSETargetLowering::
984 getOpndList(SmallVectorImpl<SDValue> &Ops,
985 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
986 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
987 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
988 // T9 should contain the address of the callee function if
989 // -reloction-model=pic or it is an indirect call.
990 if (IsPICCall || !GlobalOrExternal) {
991 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
992 RegsToPass.push_front(std::make_pair(T9Reg, Callee));
994 Ops.push_back(Callee);
996 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
997 InternalLinkage, CLI, Callee, Chain);
1000 SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1001 LoadSDNode &Nd = *cast<LoadSDNode>(Op);
1003 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1004 return MipsTargetLowering::lowerLOAD(Op, DAG);
1006 // Replace a double precision load with two i32 loads and a buildpair64.
1008 SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1009 EVT PtrVT = Ptr.getValueType();
1011 // i32 load from lower address.
1012 SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
1013 MachinePointerInfo(), Nd.isVolatile(),
1014 Nd.isNonTemporal(), Nd.isInvariant(),
1017 // i32 load from higher address.
1018 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
1019 SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
1020 MachinePointerInfo(), Nd.isVolatile(),
1021 Nd.isNonTemporal(), Nd.isInvariant(),
1022 std::min(Nd.getAlignment(), 4U));
1024 if (!Subtarget->isLittle())
1027 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
1028 SDValue Ops[2] = {BP, Hi.getValue(1)};
1029 return DAG.getMergeValues(Ops, 2, DL);
1032 SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1033 StoreSDNode &Nd = *cast<StoreSDNode>(Op);
1035 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1036 return MipsTargetLowering::lowerSTORE(Op, DAG);
1038 // Replace a double precision store with two extractelement64s and i32 stores.
1040 SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1041 EVT PtrVT = Ptr.getValueType();
1042 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1043 Val, DAG.getConstant(0, MVT::i32));
1044 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1045 Val, DAG.getConstant(1, MVT::i32));
1047 if (!Subtarget->isLittle())
1050 // i32 store to lower address.
1051 Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
1052 Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
1055 // i32 store to higher address.
1056 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
1057 return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
1058 Nd.isVolatile(), Nd.isNonTemporal(),
1059 std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo());
1062 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
1063 bool HasLo, bool HasHi,
1064 SelectionDAG &DAG) const {
1065 EVT Ty = Op.getOperand(0).getValueType();
1067 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
1068 Op.getOperand(0), Op.getOperand(1));
1072 Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult);
1074 Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult);
1076 if (!HasLo || !HasHi)
1077 return HasLo ? Lo : Hi;
1079 SDValue Vals[] = { Lo, Hi };
1080 return DAG.getMergeValues(Vals, 2, DL);
1084 static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
1085 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1086 DAG.getConstant(0, MVT::i32));
1087 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1088 DAG.getConstant(1, MVT::i32));
1089 return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
1092 static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
1093 SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op);
1094 SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op);
1095 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
1098 // This function expands mips intrinsic nodes which have 64-bit input operands
1099 // or output values.
1101 // out64 = intrinsic-node in64
1103 // lo = copy (extract-element (in64, 0))
1104 // hi = copy (extract-element (in64, 1))
1105 // mips-specific-node
1108 // out64 = merge-values (v0, v1)
1110 static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1112 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
1113 SmallVector<SDValue, 3> Ops;
1116 // See if Op has a chain input.
1118 Ops.push_back(Op->getOperand(OpNo++));
1120 // The next operand is the intrinsic opcode.
1121 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
1123 // See if the next operand has type i64.
1124 SDValue Opnd = Op->getOperand(++OpNo), In64;
1126 if (Opnd.getValueType() == MVT::i64)
1127 In64 = initAccumulator(Opnd, DL, DAG);
1129 Ops.push_back(Opnd);
1131 // Push the remaining operands.
1132 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
1133 Ops.push_back(Op->getOperand(OpNo));
1135 // Add In64 to the end of the list.
1137 Ops.push_back(In64);
1140 SmallVector<EVT, 2> ResTys;
1142 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1144 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
1147 SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size());
1148 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
1153 assert(Val->getValueType(1) == MVT::Other);
1154 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
1155 return DAG.getMergeValues(Vals, 2, DL);
1158 // Lower an MSA copy intrinsic into the specified SelectionDAG node
1159 static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1161 SDValue Vec = Op->getOperand(1);
1162 SDValue Idx = Op->getOperand(2);
1163 EVT ResTy = Op->getValueType(0);
1164 EVT EltTy = Vec->getValueType(0).getVectorElementType();
1166 SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1167 DAG.getValueType(EltTy));
1173 lowerMSASplatImm(SDLoc DL, EVT ResTy, SDValue ImmOp, SelectionDAG &DAG) {
1174 EVT ViaVecTy = ResTy;
1175 SmallVector<SDValue, 16> Ops;
1178 if (ViaVecTy == MVT::v2i64) {
1179 ImmHiOp = DAG.getNode(ISD::SRA, DL, MVT::i32, ImmOp,
1180 DAG.getConstant(31, MVT::i32));
1181 for (unsigned i = 0; i < ViaVecTy.getVectorNumElements(); ++i) {
1182 Ops.push_back(ImmHiOp);
1183 Ops.push_back(ImmOp);
1185 ViaVecTy = MVT::v4i32;
1187 for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i)
1188 Ops.push_back(ImmOp);
1191 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, &Ops[0],
1194 if (ResTy != ViaVecTy)
1195 Result = DAG.getNode(ISD::BITCAST, DL, ResTy, Result);
1201 lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) {
1202 return lowerMSASplatImm(SDLoc(Op), Op->getValueType(0),
1203 Op->getOperand(ImmOp), DAG);
1206 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1207 SelectionDAG &DAG) const {
1210 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
1213 case Intrinsic::mips_shilo:
1214 return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1215 case Intrinsic::mips_dpau_h_qbl:
1216 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1217 case Intrinsic::mips_dpau_h_qbr:
1218 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1219 case Intrinsic::mips_dpsu_h_qbl:
1220 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1221 case Intrinsic::mips_dpsu_h_qbr:
1222 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1223 case Intrinsic::mips_dpa_w_ph:
1224 return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1225 case Intrinsic::mips_dps_w_ph:
1226 return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1227 case Intrinsic::mips_dpax_w_ph:
1228 return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1229 case Intrinsic::mips_dpsx_w_ph:
1230 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1231 case Intrinsic::mips_mulsa_w_ph:
1232 return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1233 case Intrinsic::mips_mult:
1234 return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1235 case Intrinsic::mips_multu:
1236 return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1237 case Intrinsic::mips_madd:
1238 return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1239 case Intrinsic::mips_maddu:
1240 return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1241 case Intrinsic::mips_msub:
1242 return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1243 case Intrinsic::mips_msubu:
1244 return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
1245 case Intrinsic::mips_addv_b:
1246 case Intrinsic::mips_addv_h:
1247 case Intrinsic::mips_addv_w:
1248 case Intrinsic::mips_addv_d:
1249 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1251 case Intrinsic::mips_addvi_b:
1252 case Intrinsic::mips_addvi_h:
1253 case Intrinsic::mips_addvi_w:
1254 case Intrinsic::mips_addvi_d:
1255 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1256 lowerMSASplatImm(Op, 2, DAG));
1257 case Intrinsic::mips_and_v:
1258 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1260 case Intrinsic::mips_andi_b:
1261 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1262 lowerMSASplatImm(Op, 2, DAG));
1263 case Intrinsic::mips_binsli_b:
1264 case Intrinsic::mips_binsli_h:
1265 case Intrinsic::mips_binsli_w:
1266 case Intrinsic::mips_binsli_d: {
1267 EVT VecTy = Op->getValueType(0);
1268 EVT EltTy = VecTy.getVectorElementType();
1269 APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(),
1270 Op->getConstantOperandVal(3));
1271 return DAG.getNode(ISD::VSELECT, DL, VecTy,
1272 DAG.getConstant(Mask, VecTy, true), Op->getOperand(1),
1275 case Intrinsic::mips_binsri_b:
1276 case Intrinsic::mips_binsri_h:
1277 case Intrinsic::mips_binsri_w:
1278 case Intrinsic::mips_binsri_d: {
1279 EVT VecTy = Op->getValueType(0);
1280 EVT EltTy = VecTy.getVectorElementType();
1281 APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(),
1282 Op->getConstantOperandVal(3));
1283 return DAG.getNode(ISD::VSELECT, DL, VecTy,
1284 DAG.getConstant(Mask, VecTy, true), Op->getOperand(1),
1287 case Intrinsic::mips_bnz_b:
1288 case Intrinsic::mips_bnz_h:
1289 case Intrinsic::mips_bnz_w:
1290 case Intrinsic::mips_bnz_d:
1291 return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),
1293 case Intrinsic::mips_bnz_v:
1294 return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),
1296 case Intrinsic::mips_bsel_v:
1297 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1298 Op->getOperand(1), Op->getOperand(2),
1300 case Intrinsic::mips_bseli_b:
1301 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1302 Op->getOperand(1), Op->getOperand(2),
1303 lowerMSASplatImm(Op, 3, DAG));
1304 case Intrinsic::mips_bz_b:
1305 case Intrinsic::mips_bz_h:
1306 case Intrinsic::mips_bz_w:
1307 case Intrinsic::mips_bz_d:
1308 return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),
1310 case Intrinsic::mips_bz_v:
1311 return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),
1313 case Intrinsic::mips_ceq_b:
1314 case Intrinsic::mips_ceq_h:
1315 case Intrinsic::mips_ceq_w:
1316 case Intrinsic::mips_ceq_d:
1317 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1318 Op->getOperand(2), ISD::SETEQ);
1319 case Intrinsic::mips_ceqi_b:
1320 case Intrinsic::mips_ceqi_h:
1321 case Intrinsic::mips_ceqi_w:
1322 case Intrinsic::mips_ceqi_d:
1323 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1324 lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ);
1325 case Intrinsic::mips_cle_s_b:
1326 case Intrinsic::mips_cle_s_h:
1327 case Intrinsic::mips_cle_s_w:
1328 case Intrinsic::mips_cle_s_d:
1329 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1330 Op->getOperand(2), ISD::SETLE);
1331 case Intrinsic::mips_clei_s_b:
1332 case Intrinsic::mips_clei_s_h:
1333 case Intrinsic::mips_clei_s_w:
1334 case Intrinsic::mips_clei_s_d:
1335 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1336 lowerMSASplatImm(Op, 2, DAG), ISD::SETLE);
1337 case Intrinsic::mips_cle_u_b:
1338 case Intrinsic::mips_cle_u_h:
1339 case Intrinsic::mips_cle_u_w:
1340 case Intrinsic::mips_cle_u_d:
1341 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1342 Op->getOperand(2), ISD::SETULE);
1343 case Intrinsic::mips_clei_u_b:
1344 case Intrinsic::mips_clei_u_h:
1345 case Intrinsic::mips_clei_u_w:
1346 case Intrinsic::mips_clei_u_d:
1347 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1348 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1349 case Intrinsic::mips_clt_s_b:
1350 case Intrinsic::mips_clt_s_h:
1351 case Intrinsic::mips_clt_s_w:
1352 case Intrinsic::mips_clt_s_d:
1353 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1354 Op->getOperand(2), ISD::SETLT);
1355 case Intrinsic::mips_clti_s_b:
1356 case Intrinsic::mips_clti_s_h:
1357 case Intrinsic::mips_clti_s_w:
1358 case Intrinsic::mips_clti_s_d:
1359 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1360 lowerMSASplatImm(Op, 2, DAG), ISD::SETLT);
1361 case Intrinsic::mips_clt_u_b:
1362 case Intrinsic::mips_clt_u_h:
1363 case Intrinsic::mips_clt_u_w:
1364 case Intrinsic::mips_clt_u_d:
1365 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1366 Op->getOperand(2), ISD::SETULT);
1367 case Intrinsic::mips_clti_u_b:
1368 case Intrinsic::mips_clti_u_h:
1369 case Intrinsic::mips_clti_u_w:
1370 case Intrinsic::mips_clti_u_d:
1371 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1372 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
1373 case Intrinsic::mips_copy_s_b:
1374 case Intrinsic::mips_copy_s_h:
1375 case Intrinsic::mips_copy_s_w:
1376 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1377 case Intrinsic::mips_copy_s_d:
1378 // Don't lower directly into VEXTRACT_SEXT_ELT since i64 might be illegal.
1379 // Instead lower to the generic EXTRACT_VECTOR_ELT node and let the type
1380 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1381 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1382 Op->getOperand(1), Op->getOperand(2));
1383 case Intrinsic::mips_copy_u_b:
1384 case Intrinsic::mips_copy_u_h:
1385 case Intrinsic::mips_copy_u_w:
1386 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1387 case Intrinsic::mips_copy_u_d:
1388 // Don't lower directly into VEXTRACT_ZEXT_ELT since i64 might be illegal.
1389 // Instead lower to the generic EXTRACT_VECTOR_ELT node and let the type
1390 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1392 // Note: When i64 is illegal, this results in copy_s.w instructions instead
1393 // of copy_u.w instructions. This makes no difference to the behaviour
1394 // since i64 is only illegal when the register file is 32-bit.
1395 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1396 Op->getOperand(1), Op->getOperand(2));
1397 case Intrinsic::mips_div_s_b:
1398 case Intrinsic::mips_div_s_h:
1399 case Intrinsic::mips_div_s_w:
1400 case Intrinsic::mips_div_s_d:
1401 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1403 case Intrinsic::mips_div_u_b:
1404 case Intrinsic::mips_div_u_h:
1405 case Intrinsic::mips_div_u_w:
1406 case Intrinsic::mips_div_u_d:
1407 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1409 case Intrinsic::mips_fadd_w:
1410 case Intrinsic::mips_fadd_d:
1411 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1413 // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1414 case Intrinsic::mips_fceq_w:
1415 case Intrinsic::mips_fceq_d:
1416 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1417 Op->getOperand(2), ISD::SETOEQ);
1418 case Intrinsic::mips_fcle_w:
1419 case Intrinsic::mips_fcle_d:
1420 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1421 Op->getOperand(2), ISD::SETOLE);
1422 case Intrinsic::mips_fclt_w:
1423 case Intrinsic::mips_fclt_d:
1424 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1425 Op->getOperand(2), ISD::SETOLT);
1426 case Intrinsic::mips_fcne_w:
1427 case Intrinsic::mips_fcne_d:
1428 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1429 Op->getOperand(2), ISD::SETONE);
1430 case Intrinsic::mips_fcor_w:
1431 case Intrinsic::mips_fcor_d:
1432 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1433 Op->getOperand(2), ISD::SETO);
1434 case Intrinsic::mips_fcueq_w:
1435 case Intrinsic::mips_fcueq_d:
1436 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1437 Op->getOperand(2), ISD::SETUEQ);
1438 case Intrinsic::mips_fcule_w:
1439 case Intrinsic::mips_fcule_d:
1440 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1441 Op->getOperand(2), ISD::SETULE);
1442 case Intrinsic::mips_fcult_w:
1443 case Intrinsic::mips_fcult_d:
1444 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1445 Op->getOperand(2), ISD::SETULT);
1446 case Intrinsic::mips_fcun_w:
1447 case Intrinsic::mips_fcun_d:
1448 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1449 Op->getOperand(2), ISD::SETUO);
1450 case Intrinsic::mips_fcune_w:
1451 case Intrinsic::mips_fcune_d:
1452 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1453 Op->getOperand(2), ISD::SETUNE);
1454 case Intrinsic::mips_fdiv_w:
1455 case Intrinsic::mips_fdiv_d:
1456 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1458 case Intrinsic::mips_ffint_u_w:
1459 case Intrinsic::mips_ffint_u_d:
1460 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
1462 case Intrinsic::mips_ffint_s_w:
1463 case Intrinsic::mips_ffint_s_d:
1464 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
1466 case Intrinsic::mips_fill_b:
1467 case Intrinsic::mips_fill_h:
1468 case Intrinsic::mips_fill_w:
1469 case Intrinsic::mips_fill_d: {
1470 SmallVector<SDValue, 16> Ops;
1471 EVT ResTy = Op->getValueType(0);
1473 for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i)
1474 Ops.push_back(Op->getOperand(1));
1476 // If ResTy is v2i64 then the type legalizer will break this node down into
1477 // an equivalent v4i32.
1478 return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, &Ops[0], Ops.size());
1480 case Intrinsic::mips_fexp2_w:
1481 case Intrinsic::mips_fexp2_d: {
1482 EVT ResTy = Op->getValueType(0);
1484 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1485 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
1487 case Intrinsic::mips_flog2_w:
1488 case Intrinsic::mips_flog2_d:
1489 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
1490 case Intrinsic::mips_fmadd_w:
1491 case Intrinsic::mips_fmadd_d:
1492 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
1493 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1494 case Intrinsic::mips_fmul_w:
1495 case Intrinsic::mips_fmul_d:
1496 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1498 case Intrinsic::mips_fmsub_w:
1499 case Intrinsic::mips_fmsub_d: {
1500 EVT ResTy = Op->getValueType(0);
1501 return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1),
1502 DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy,
1503 Op->getOperand(2), Op->getOperand(3)));
1505 case Intrinsic::mips_frint_w:
1506 case Intrinsic::mips_frint_d:
1507 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
1508 case Intrinsic::mips_fsqrt_w:
1509 case Intrinsic::mips_fsqrt_d:
1510 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
1511 case Intrinsic::mips_fsub_w:
1512 case Intrinsic::mips_fsub_d:
1513 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1515 case Intrinsic::mips_ftrunc_u_w:
1516 case Intrinsic::mips_ftrunc_u_d:
1517 return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
1519 case Intrinsic::mips_ftrunc_s_w:
1520 case Intrinsic::mips_ftrunc_s_d:
1521 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
1523 case Intrinsic::mips_ilvev_b:
1524 case Intrinsic::mips_ilvev_h:
1525 case Intrinsic::mips_ilvev_w:
1526 case Intrinsic::mips_ilvev_d:
1527 return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),
1528 Op->getOperand(1), Op->getOperand(2));
1529 case Intrinsic::mips_ilvl_b:
1530 case Intrinsic::mips_ilvl_h:
1531 case Intrinsic::mips_ilvl_w:
1532 case Intrinsic::mips_ilvl_d:
1533 return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),
1534 Op->getOperand(1), Op->getOperand(2));
1535 case Intrinsic::mips_ilvod_b:
1536 case Intrinsic::mips_ilvod_h:
1537 case Intrinsic::mips_ilvod_w:
1538 case Intrinsic::mips_ilvod_d:
1539 return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),
1540 Op->getOperand(1), Op->getOperand(2));
1541 case Intrinsic::mips_ilvr_b:
1542 case Intrinsic::mips_ilvr_h:
1543 case Intrinsic::mips_ilvr_w:
1544 case Intrinsic::mips_ilvr_d:
1545 return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),
1546 Op->getOperand(1), Op->getOperand(2));
1547 case Intrinsic::mips_insert_b:
1548 case Intrinsic::mips_insert_h:
1549 case Intrinsic::mips_insert_w:
1550 case Intrinsic::mips_insert_d:
1551 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1552 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
1553 case Intrinsic::mips_ldi_b:
1554 case Intrinsic::mips_ldi_h:
1555 case Intrinsic::mips_ldi_w:
1556 case Intrinsic::mips_ldi_d:
1557 return lowerMSASplatImm(Op, 1, DAG);
1558 case Intrinsic::mips_lsa: {
1559 EVT ResTy = Op->getValueType(0);
1560 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1561 DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
1562 Op->getOperand(2), Op->getOperand(3)));
1564 case Intrinsic::mips_maddv_b:
1565 case Intrinsic::mips_maddv_h:
1566 case Intrinsic::mips_maddv_w:
1567 case Intrinsic::mips_maddv_d: {
1568 EVT ResTy = Op->getValueType(0);
1569 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1570 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1571 Op->getOperand(2), Op->getOperand(3)));
1573 case Intrinsic::mips_max_s_b:
1574 case Intrinsic::mips_max_s_h:
1575 case Intrinsic::mips_max_s_w:
1576 case Intrinsic::mips_max_s_d:
1577 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1578 Op->getOperand(1), Op->getOperand(2));
1579 case Intrinsic::mips_max_u_b:
1580 case Intrinsic::mips_max_u_h:
1581 case Intrinsic::mips_max_u_w:
1582 case Intrinsic::mips_max_u_d:
1583 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1584 Op->getOperand(1), Op->getOperand(2));
1585 case Intrinsic::mips_maxi_s_b:
1586 case Intrinsic::mips_maxi_s_h:
1587 case Intrinsic::mips_maxi_s_w:
1588 case Intrinsic::mips_maxi_s_d:
1589 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1590 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1591 case Intrinsic::mips_maxi_u_b:
1592 case Intrinsic::mips_maxi_u_h:
1593 case Intrinsic::mips_maxi_u_w:
1594 case Intrinsic::mips_maxi_u_d:
1595 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1596 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1597 case Intrinsic::mips_min_s_b:
1598 case Intrinsic::mips_min_s_h:
1599 case Intrinsic::mips_min_s_w:
1600 case Intrinsic::mips_min_s_d:
1601 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1602 Op->getOperand(1), Op->getOperand(2));
1603 case Intrinsic::mips_min_u_b:
1604 case Intrinsic::mips_min_u_h:
1605 case Intrinsic::mips_min_u_w:
1606 case Intrinsic::mips_min_u_d:
1607 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1608 Op->getOperand(1), Op->getOperand(2));
1609 case Intrinsic::mips_mini_s_b:
1610 case Intrinsic::mips_mini_s_h:
1611 case Intrinsic::mips_mini_s_w:
1612 case Intrinsic::mips_mini_s_d:
1613 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1614 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1615 case Intrinsic::mips_mini_u_b:
1616 case Intrinsic::mips_mini_u_h:
1617 case Intrinsic::mips_mini_u_w:
1618 case Intrinsic::mips_mini_u_d:
1619 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1620 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1621 case Intrinsic::mips_mod_s_b:
1622 case Intrinsic::mips_mod_s_h:
1623 case Intrinsic::mips_mod_s_w:
1624 case Intrinsic::mips_mod_s_d:
1625 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
1627 case Intrinsic::mips_mod_u_b:
1628 case Intrinsic::mips_mod_u_h:
1629 case Intrinsic::mips_mod_u_w:
1630 case Intrinsic::mips_mod_u_d:
1631 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
1633 case Intrinsic::mips_mulv_b:
1634 case Intrinsic::mips_mulv_h:
1635 case Intrinsic::mips_mulv_w:
1636 case Intrinsic::mips_mulv_d:
1637 return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
1639 case Intrinsic::mips_msubv_b:
1640 case Intrinsic::mips_msubv_h:
1641 case Intrinsic::mips_msubv_w:
1642 case Intrinsic::mips_msubv_d: {
1643 EVT ResTy = Op->getValueType(0);
1644 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
1645 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1646 Op->getOperand(2), Op->getOperand(3)));
1648 case Intrinsic::mips_nlzc_b:
1649 case Intrinsic::mips_nlzc_h:
1650 case Intrinsic::mips_nlzc_w:
1651 case Intrinsic::mips_nlzc_d:
1652 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
1653 case Intrinsic::mips_nor_v: {
1654 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1655 Op->getOperand(1), Op->getOperand(2));
1656 return DAG.getNOT(DL, Res, Res->getValueType(0));
1658 case Intrinsic::mips_nori_b: {
1659 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1661 lowerMSASplatImm(Op, 2, DAG));
1662 return DAG.getNOT(DL, Res, Res->getValueType(0));
1664 case Intrinsic::mips_or_v:
1665 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
1667 case Intrinsic::mips_ori_b:
1668 return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1669 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1670 case Intrinsic::mips_pckev_b:
1671 case Intrinsic::mips_pckev_h:
1672 case Intrinsic::mips_pckev_w:
1673 case Intrinsic::mips_pckev_d:
1674 return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),
1675 Op->getOperand(1), Op->getOperand(2));
1676 case Intrinsic::mips_pckod_b:
1677 case Intrinsic::mips_pckod_h:
1678 case Intrinsic::mips_pckod_w:
1679 case Intrinsic::mips_pckod_d:
1680 return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),
1681 Op->getOperand(1), Op->getOperand(2));
1682 case Intrinsic::mips_pcnt_b:
1683 case Intrinsic::mips_pcnt_h:
1684 case Intrinsic::mips_pcnt_w:
1685 case Intrinsic::mips_pcnt_d:
1686 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
1687 case Intrinsic::mips_shf_b:
1688 case Intrinsic::mips_shf_h:
1689 case Intrinsic::mips_shf_w:
1690 return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),
1691 Op->getOperand(2), Op->getOperand(1));
1692 case Intrinsic::mips_sll_b:
1693 case Intrinsic::mips_sll_h:
1694 case Intrinsic::mips_sll_w:
1695 case Intrinsic::mips_sll_d:
1696 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
1698 case Intrinsic::mips_slli_b:
1699 case Intrinsic::mips_slli_h:
1700 case Intrinsic::mips_slli_w:
1701 case Intrinsic::mips_slli_d:
1702 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
1703 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1704 case Intrinsic::mips_splat_b:
1705 case Intrinsic::mips_splat_h:
1706 case Intrinsic::mips_splat_w:
1707 case Intrinsic::mips_splat_d:
1708 // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle
1709 // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because
1710 // EXTRACT_VECTOR_ELT can't extract i64's on MIPS32.
1711 // Instead we lower to MipsISD::VSHF and match from there.
1712 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
1713 lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
1715 case Intrinsic::mips_splati_b:
1716 case Intrinsic::mips_splati_h:
1717 case Intrinsic::mips_splati_w:
1718 case Intrinsic::mips_splati_d:
1719 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
1720 lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
1722 case Intrinsic::mips_sra_b:
1723 case Intrinsic::mips_sra_h:
1724 case Intrinsic::mips_sra_w:
1725 case Intrinsic::mips_sra_d:
1726 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
1728 case Intrinsic::mips_srai_b:
1729 case Intrinsic::mips_srai_h:
1730 case Intrinsic::mips_srai_w:
1731 case Intrinsic::mips_srai_d:
1732 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
1733 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1734 case Intrinsic::mips_srl_b:
1735 case Intrinsic::mips_srl_h:
1736 case Intrinsic::mips_srl_w:
1737 case Intrinsic::mips_srl_d:
1738 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
1740 case Intrinsic::mips_srli_b:
1741 case Intrinsic::mips_srli_h:
1742 case Intrinsic::mips_srli_w:
1743 case Intrinsic::mips_srli_d:
1744 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
1745 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1746 case Intrinsic::mips_subv_b:
1747 case Intrinsic::mips_subv_h:
1748 case Intrinsic::mips_subv_w:
1749 case Intrinsic::mips_subv_d:
1750 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
1752 case Intrinsic::mips_subvi_b:
1753 case Intrinsic::mips_subvi_h:
1754 case Intrinsic::mips_subvi_w:
1755 case Intrinsic::mips_subvi_d:
1756 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
1757 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1758 case Intrinsic::mips_vshf_b:
1759 case Intrinsic::mips_vshf_h:
1760 case Intrinsic::mips_vshf_w:
1761 case Intrinsic::mips_vshf_d:
1762 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
1763 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1764 case Intrinsic::mips_xor_v:
1765 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
1767 case Intrinsic::mips_xori_b:
1768 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
1769 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1773 static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
1775 SDValue ChainIn = Op->getOperand(0);
1776 SDValue Address = Op->getOperand(2);
1777 SDValue Offset = Op->getOperand(3);
1778 EVT ResTy = Op->getValueType(0);
1779 EVT PtrTy = Address->getValueType(0);
1781 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
1783 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
1787 SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
1788 SelectionDAG &DAG) const {
1789 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1793 case Intrinsic::mips_extp:
1794 return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
1795 case Intrinsic::mips_extpdp:
1796 return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
1797 case Intrinsic::mips_extr_w:
1798 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
1799 case Intrinsic::mips_extr_r_w:
1800 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
1801 case Intrinsic::mips_extr_rs_w:
1802 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
1803 case Intrinsic::mips_extr_s_h:
1804 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
1805 case Intrinsic::mips_mthlip:
1806 return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
1807 case Intrinsic::mips_mulsaq_s_w_ph:
1808 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
1809 case Intrinsic::mips_maq_s_w_phl:
1810 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
1811 case Intrinsic::mips_maq_s_w_phr:
1812 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
1813 case Intrinsic::mips_maq_sa_w_phl:
1814 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
1815 case Intrinsic::mips_maq_sa_w_phr:
1816 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
1817 case Intrinsic::mips_dpaq_s_w_ph:
1818 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
1819 case Intrinsic::mips_dpsq_s_w_ph:
1820 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
1821 case Intrinsic::mips_dpaq_sa_l_w:
1822 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
1823 case Intrinsic::mips_dpsq_sa_l_w:
1824 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
1825 case Intrinsic::mips_dpaqx_s_w_ph:
1826 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
1827 case Intrinsic::mips_dpaqx_sa_w_ph:
1828 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
1829 case Intrinsic::mips_dpsqx_s_w_ph:
1830 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
1831 case Intrinsic::mips_dpsqx_sa_w_ph:
1832 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
1833 case Intrinsic::mips_ld_b:
1834 case Intrinsic::mips_ld_h:
1835 case Intrinsic::mips_ld_w:
1836 case Intrinsic::mips_ld_d:
1837 return lowerMSALoadIntr(Op, DAG, Intr);
1841 static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
1843 SDValue ChainIn = Op->getOperand(0);
1844 SDValue Value = Op->getOperand(2);
1845 SDValue Address = Op->getOperand(3);
1846 SDValue Offset = Op->getOperand(4);
1847 EVT PtrTy = Address->getValueType(0);
1849 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
1851 return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
1855 SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
1856 SelectionDAG &DAG) const {
1857 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1861 case Intrinsic::mips_st_b:
1862 case Intrinsic::mips_st_h:
1863 case Intrinsic::mips_st_w:
1864 case Intrinsic::mips_st_d:
1865 return lowerMSAStoreIntr(Op, DAG, Intr);
1869 /// \brief Check if the given BuildVectorSDNode is a splat.
1870 /// This method currently relies on DAG nodes being reused when equivalent,
1871 /// so it's possible for this to return false even when isConstantSplat returns
1873 static bool isSplatVector(const BuildVectorSDNode *N) {
1874 unsigned int nOps = N->getNumOperands();
1875 assert(nOps > 1 && "isSplat has 0 or 1 sized build vector");
1877 SDValue Operand0 = N->getOperand(0);
1879 for (unsigned int i = 1; i < nOps; ++i) {
1880 if (N->getOperand(i) != Operand0)
1887 // Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
1889 // The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
1890 // choose to sign-extend but we could have equally chosen zero-extend. The
1891 // DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
1892 // result into this node later (possibly changing it to a zero-extend in the
1894 SDValue MipsSETargetLowering::
1895 lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
1897 EVT ResTy = Op->getValueType(0);
1898 SDValue Op0 = Op->getOperand(0);
1899 EVT VecTy = Op0->getValueType(0);
1901 if (!VecTy.is128BitVector())
1904 if (ResTy.isInteger()) {
1905 SDValue Op1 = Op->getOperand(1);
1906 EVT EltTy = VecTy.getVectorElementType();
1907 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
1908 DAG.getValueType(EltTy));
1914 static bool isConstantOrUndef(const SDValue Op) {
1915 if (Op->getOpcode() == ISD::UNDEF)
1917 if (dyn_cast<ConstantSDNode>(Op))
1919 if (dyn_cast<ConstantFPSDNode>(Op))
1924 static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) {
1925 for (unsigned i = 0; i < Op->getNumOperands(); ++i)
1926 if (isConstantOrUndef(Op->getOperand(i)))
1931 // Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
1934 // Lowers according to the following rules:
1935 // - Constant splats are legal as-is as long as the SplatBitSize is a power of
1936 // 2 less than or equal to 64 and the value fits into a signed 10-bit
1938 // - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
1939 // is a power of 2 less than or equal to 64 and the value does not fit into a
1940 // signed 10-bit immediate
1941 // - Non-constant splats are legal as-is.
1942 // - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
1943 // - All others are illegal and must be expanded.
1944 SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
1945 SelectionDAG &DAG) const {
1946 BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
1947 EVT ResTy = Op->getValueType(0);
1949 APInt SplatValue, SplatUndef;
1950 unsigned SplatBitSize;
1953 if (!Subtarget->hasMSA() || !ResTy.is128BitVector())
1956 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
1958 !Subtarget->isLittle()) && SplatBitSize <= 64) {
1959 // We can only cope with 8, 16, 32, or 64-bit elements
1960 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
1964 // If the value fits into a simm10 then we can use ldi.[bhwd]
1965 if (SplatValue.isSignedIntN(10))
1970 switch (SplatBitSize) {
1974 ViaVecTy = MVT::v16i8;
1977 ViaVecTy = MVT::v8i16;
1980 ViaVecTy = MVT::v4i32;
1983 // There's no fill.d to fall back on for 64-bit values
1987 SmallVector<SDValue, 16> Ops;
1988 SDValue Constant = DAG.getConstant(SplatValue.sextOrSelf(32), MVT::i32);
1990 for (unsigned i = 0; i < ViaVecTy.getVectorNumElements(); ++i)
1991 Ops.push_back(Constant);
1993 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Node), ViaVecTy,
1994 &Ops[0], Ops.size());
1996 if (ViaVecTy != ResTy)
1997 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
2000 } else if (isSplatVector(Node))
2002 else if (!isConstantOrUndefBUILD_VECTOR(Node)) {
2003 // Use INSERT_VECTOR_ELT operations rather than expand to stores.
2004 // The resulting code is the same length as the expansion, but it doesn't
2005 // use memory operations
2006 EVT ResTy = Node->getValueType(0);
2008 assert(ResTy.isVector());
2010 unsigned NumElts = ResTy.getVectorNumElements();
2011 SDValue Vector = DAG.getUNDEF(ResTy);
2012 for (unsigned i = 0; i < NumElts; ++i) {
2013 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
2014 Node->getOperand(i),
2015 DAG.getConstant(i, MVT::i32));
2023 // Lower VECTOR_SHUFFLE into SHF (if possible).
2025 // SHF splits the vector into blocks of four elements, then shuffles these
2026 // elements according to a <4 x i2> constant (encoded as an integer immediate).
2028 // It is therefore possible to lower into SHF when the mask takes the form:
2029 // <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...>
2030 // When undef's appear they are treated as if they were whatever value is
2031 // necessary in order to fit the above form.
2034 // %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
2035 // <8 x i32> <i32 3, i32 2, i32 1, i32 0,
2036 // i32 7, i32 6, i32 5, i32 4>
2038 // (SHF_H $w0, $w1, 27)
2039 // where the 27 comes from:
2040 // 3 + (2 << 2) + (1 << 4) + (0 << 6)
2041 static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy,
2042 SmallVector<int, 16> Indices,
2043 SelectionDAG &DAG) {
2044 int SHFIndices[4] = { -1, -1, -1, -1 };
2046 if (Indices.size() < 4)
2049 for (unsigned i = 0; i < 4; ++i) {
2050 for (unsigned j = i; j < Indices.size(); j += 4) {
2051 int Idx = Indices[j];
2053 // Convert from vector index to 4-element subvector index
2054 // If an index refers to an element outside of the subvector then give up
2057 if (Idx < 0 || Idx >= 4)
2061 // If the mask has an undef, replace it with the current index.
2062 // Note that it might still be undef if the current index is also undef
2063 if (SHFIndices[i] == -1)
2064 SHFIndices[i] = Idx;
2066 // Check that non-undef values are the same as in the mask. If they
2067 // aren't then give up
2068 if (!(Idx == -1 || Idx == SHFIndices[i]))
2073 // Calculate the immediate. Replace any remaining undefs with zero
2075 for (int i = 3; i >= 0; --i) {
2076 int Idx = SHFIndices[i];
2085 return DAG.getNode(MipsISD::SHF, SDLoc(Op), ResTy,
2086 DAG.getConstant(Imm, MVT::i32), Op->getOperand(0));
2089 // Lower VECTOR_SHUFFLE into ILVEV (if possible).
2091 // ILVEV interleaves the even elements from each vector.
2093 // It is possible to lower into ILVEV when the mask takes the form:
2094 // <0, n, 2, n+2, 4, n+4, ...>
2095 // where n is the number of elements in the vector.
2097 // When undef's appear in the mask they are treated as if they were whatever
2098 // value is necessary in order to fit the above form.
2099 static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy,
2100 SmallVector<int, 16> Indices,
2101 SelectionDAG &DAG) {
2102 assert ((Indices.size() % 2) == 0);
2104 int WtIdx = ResTy.getVectorNumElements();
2106 for (unsigned i = 0; i < Indices.size(); i += 2) {
2107 if (Indices[i] != -1 && Indices[i] != WsIdx)
2109 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2115 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Op->getOperand(0),
2119 // Lower VECTOR_SHUFFLE into ILVOD (if possible).
2121 // ILVOD interleaves the odd elements from each vector.
2123 // It is possible to lower into ILVOD when the mask takes the form:
2124 // <1, n+1, 3, n+3, 5, n+5, ...>
2125 // where n is the number of elements in the vector.
2127 // When undef's appear in the mask they are treated as if they were whatever
2128 // value is necessary in order to fit the above form.
2129 static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy,
2130 SmallVector<int, 16> Indices,
2131 SelectionDAG &DAG) {
2132 assert ((Indices.size() % 2) == 0);
2134 int WtIdx = ResTy.getVectorNumElements() + 1;
2136 for (unsigned i = 0; i < Indices.size(); i += 2) {
2137 if (Indices[i] != -1 && Indices[i] != WsIdx)
2139 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2145 return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Op->getOperand(0),
2149 // Lower VECTOR_SHUFFLE into ILVL (if possible).
2151 // ILVL interleaves consecutive elements from the left half of each vector.
2153 // It is possible to lower into ILVL when the mask takes the form:
2154 // <0, n, 1, n+1, 2, n+2, ...>
2155 // where n is the number of elements in the vector.
2157 // When undef's appear in the mask they are treated as if they were whatever
2158 // value is necessary in order to fit the above form.
2159 static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy,
2160 SmallVector<int, 16> Indices,
2161 SelectionDAG &DAG) {
2162 assert ((Indices.size() % 2) == 0);
2164 int WtIdx = ResTy.getVectorNumElements();
2166 for (unsigned i = 0; i < Indices.size(); i += 2) {
2167 if (Indices[i] != -1 && Indices[i] != WsIdx)
2169 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2175 return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Op->getOperand(0),
2179 // Lower VECTOR_SHUFFLE into ILVR (if possible).
2181 // ILVR interleaves consecutive elements from the right half of each vector.
2183 // It is possible to lower into ILVR when the mask takes the form:
2184 // <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>
2185 // where n is the number of elements in the vector and x is half n.
2187 // When undef's appear in the mask they are treated as if they were whatever
2188 // value is necessary in order to fit the above form.
2189 static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy,
2190 SmallVector<int, 16> Indices,
2191 SelectionDAG &DAG) {
2192 assert ((Indices.size() % 2) == 0);
2193 unsigned NumElts = ResTy.getVectorNumElements();
2194 int WsIdx = NumElts / 2;
2195 int WtIdx = NumElts + NumElts / 2;
2197 for (unsigned i = 0; i < Indices.size(); i += 2) {
2198 if (Indices[i] != -1 && Indices[i] != WsIdx)
2200 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2206 return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Op->getOperand(0),
2210 // Lower VECTOR_SHUFFLE into PCKEV (if possible).
2212 // PCKEV copies the even elements of each vector into the result vector.
2214 // It is possible to lower into PCKEV when the mask takes the form:
2215 // <0, 2, 4, ..., n, n+2, n+4, ...>
2216 // where n is the number of elements in the vector.
2218 // When undef's appear in the mask they are treated as if they were whatever
2219 // value is necessary in order to fit the above form.
2220 static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy,
2221 SmallVector<int, 16> Indices,
2222 SelectionDAG &DAG) {
2223 assert ((Indices.size() % 2) == 0);
2226 for (unsigned i = 0; i < Indices.size(); ++i) {
2227 if (Indices[i] != -1 && Indices[i] != Idx)
2232 return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Op->getOperand(0),
2236 // Lower VECTOR_SHUFFLE into PCKOD (if possible).
2238 // PCKOD copies the odd elements of each vector into the result vector.
2240 // It is possible to lower into PCKOD when the mask takes the form:
2241 // <1, 3, 5, ..., n+1, n+3, n+5, ...>
2242 // where n is the number of elements in the vector.
2244 // When undef's appear in the mask they are treated as if they were whatever
2245 // value is necessary in order to fit the above form.
2246 static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy,
2247 SmallVector<int, 16> Indices,
2248 SelectionDAG &DAG) {
2249 assert ((Indices.size() % 2) == 0);
2252 for (unsigned i = 0; i < Indices.size(); ++i) {
2253 if (Indices[i] != -1 && Indices[i] != Idx)
2258 return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Op->getOperand(0),
2262 // Lower VECTOR_SHUFFLE into VSHF.
2264 // This mostly consists of converting the shuffle indices in Indices into a
2265 // BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is
2266 // also code to eliminate unused operands of the VECTOR_SHUFFLE. For example,
2267 // if the type is v8i16 and all the indices are less than 8 then the second
2268 // operand is unused and can be replaced with anything. We choose to replace it
2269 // with the used operand since this reduces the number of instructions overall.
2270 static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
2271 SmallVector<int, 16> Indices,
2272 SelectionDAG &DAG) {
2273 SmallVector<SDValue, 16> Ops;
2276 EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2277 EVT MaskEltTy = MaskVecTy.getVectorElementType();
2278 bool Using1stVec = false;
2279 bool Using2ndVec = false;
2281 int ResTyNumElts = ResTy.getVectorNumElements();
2283 for (int i = 0; i < ResTyNumElts; ++i) {
2284 // Idx == -1 means UNDEF
2285 int Idx = Indices[i];
2287 if (0 <= Idx && Idx < ResTyNumElts)
2289 if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
2293 for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
2295 Ops.push_back(DAG.getTargetConstant(*I, MaskEltTy));
2297 SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, &Ops[0],
2300 if (Using1stVec && Using2ndVec) {
2301 Op0 = Op->getOperand(0);
2302 Op1 = Op->getOperand(1);
2303 } else if (Using1stVec)
2304 Op0 = Op1 = Op->getOperand(0);
2305 else if (Using2ndVec)
2306 Op0 = Op1 = Op->getOperand(1);
2308 llvm_unreachable("shuffle vector mask references neither vector operand?");
2310 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op0, Op1);
2313 // Lower VECTOR_SHUFFLE into one of a number of instructions depending on the
2314 // indices in the shuffle.
2315 SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
2316 SelectionDAG &DAG) const {
2317 ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
2318 EVT ResTy = Op->getValueType(0);
2320 if (!ResTy.is128BitVector())
2323 int ResTyNumElts = ResTy.getVectorNumElements();
2324 SmallVector<int, 16> Indices;
2326 for (int i = 0; i < ResTyNumElts; ++i)
2327 Indices.push_back(Node->getMaskElt(i));
2329 SDValue Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG);
2330 if (Result.getNode())
2332 Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG);
2333 if (Result.getNode())
2335 Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG);
2336 if (Result.getNode())
2338 Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG);
2339 if (Result.getNode())
2341 Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG);
2342 if (Result.getNode())
2344 Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG);
2345 if (Result.getNode())
2347 Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG);
2348 if (Result.getNode())
2350 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2353 MachineBasicBlock * MipsSETargetLowering::
2354 emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
2356 // bposge32_pseudo $vr0
2366 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
2368 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2369 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2370 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2371 DebugLoc DL = MI->getDebugLoc();
2372 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2373 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
2374 MachineFunction *F = BB->getParent();
2375 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2376 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2377 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
2380 F->insert(It, Sink);
2382 // Transfer the remainder of BB and its successor edges to Sink.
2383 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
2385 Sink->transferSuccessorsAndUpdatePHIs(BB);
2388 BB->addSuccessor(FBB);
2389 BB->addSuccessor(TBB);
2390 FBB->addSuccessor(Sink);
2391 TBB->addSuccessor(Sink);
2393 // Insert the real bposge32 instruction to $BB.
2394 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
2397 unsigned VR2 = RegInfo.createVirtualRegister(RC);
2398 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
2399 .addReg(Mips::ZERO).addImm(0);
2400 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2403 unsigned VR1 = RegInfo.createVirtualRegister(RC);
2404 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
2405 .addReg(Mips::ZERO).addImm(1);
2407 // Insert phi function to $Sink.
2408 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2409 MI->getOperand(0).getReg())
2410 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
2412 MI->eraseFromParent(); // The pseudo instruction is gone now.
2416 MachineBasicBlock * MipsSETargetLowering::
2417 emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
2418 unsigned BranchOp) const{
2420 // vany_nonzero $rd, $ws
2431 // $rd = phi($rd1, $fbb, $rd2, $tbb)
2433 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2434 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2435 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2436 DebugLoc DL = MI->getDebugLoc();
2437 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2438 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
2439 MachineFunction *F = BB->getParent();
2440 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2441 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2442 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
2445 F->insert(It, Sink);
2447 // Transfer the remainder of BB and its successor edges to Sink.
2448 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
2450 Sink->transferSuccessorsAndUpdatePHIs(BB);
2453 BB->addSuccessor(FBB);
2454 BB->addSuccessor(TBB);
2455 FBB->addSuccessor(Sink);
2456 TBB->addSuccessor(Sink);
2458 // Insert the real bnz.b instruction to $BB.
2459 BuildMI(BB, DL, TII->get(BranchOp))
2460 .addReg(MI->getOperand(1).getReg())
2464 unsigned RD1 = RegInfo.createVirtualRegister(RC);
2465 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
2466 .addReg(Mips::ZERO).addImm(0);
2467 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2470 unsigned RD2 = RegInfo.createVirtualRegister(RC);
2471 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
2472 .addReg(Mips::ZERO).addImm(1);
2474 // Insert phi function to $Sink.
2475 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2476 MI->getOperand(0).getReg())
2477 .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
2479 MI->eraseFromParent(); // The pseudo instruction is gone now.
2483 // Emit the COPY_FW pseudo instruction.
2485 // copy_fw_pseudo $fd, $ws, n
2487 // copy_u_w $rt, $ws, $n
2490 // When n is zero, the equivalent operation can be performed with (potentially)
2491 // zero instructions due to register overlaps. This optimization is never valid
2492 // for lane 1 because it would require FR=0 mode which isn't supported by MSA.
2493 MachineBasicBlock * MipsSETargetLowering::
2494 emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{
2495 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2496 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2497 DebugLoc DL = MI->getDebugLoc();
2498 unsigned Fd = MI->getOperand(0).getReg();
2499 unsigned Ws = MI->getOperand(1).getReg();
2500 unsigned Lane = MI->getOperand(2).getImm();
2503 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_lo);
2505 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2507 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(1);
2508 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
2511 MI->eraseFromParent(); // The pseudo instruction is gone now.
2515 // Emit the COPY_FD pseudo instruction.
2517 // copy_fd_pseudo $fd, $ws, n
2519 // splati.d $wt, $ws, $n
2520 // copy $fd, $wt:sub_64
2522 // When n is zero, the equivalent operation can be performed with (potentially)
2523 // zero instructions due to register overlaps. This optimization is always
2524 // valid because FR=1 mode which is the only supported mode in MSA.
2525 MachineBasicBlock * MipsSETargetLowering::
2526 emitCOPY_FD(MachineInstr *MI, MachineBasicBlock *BB) const{
2527 assert(Subtarget->isFP64bit());
2529 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2530 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2531 unsigned Fd = MI->getOperand(0).getReg();
2532 unsigned Ws = MI->getOperand(1).getReg();
2533 unsigned Lane = MI->getOperand(2).getImm() * 2;
2534 DebugLoc DL = MI->getDebugLoc();
2537 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
2539 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2541 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
2542 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
2545 MI->eraseFromParent(); // The pseudo instruction is gone now.
2549 // Emit the INSERT_FW pseudo instruction.
2551 // insert_fw_pseudo $wd, $wd_in, $n, $fs
2553 // subreg_to_reg $wt:sub_lo, $fs
2554 // insve_w $wd[$n], $wd_in, $wt[0]
2556 MipsSETargetLowering::emitINSERT_FW(MachineInstr *MI,
2557 MachineBasicBlock *BB) const {
2558 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2559 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2560 DebugLoc DL = MI->getDebugLoc();
2561 unsigned Wd = MI->getOperand(0).getReg();
2562 unsigned Wd_in = MI->getOperand(1).getReg();
2563 unsigned Lane = MI->getOperand(2).getImm();
2564 unsigned Fs = MI->getOperand(3).getReg();
2565 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2567 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
2570 .addImm(Mips::sub_lo);
2571 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
2576 MI->eraseFromParent(); // The pseudo instruction is gone now.
2580 // Emit the INSERT_FD pseudo instruction.
2582 // insert_fd_pseudo $wd, $fs, n
2584 // subreg_to_reg $wt:sub_64, $fs
2585 // insve_d $wd[$n], $wd_in, $wt[0]
2587 MipsSETargetLowering::emitINSERT_FD(MachineInstr *MI,
2588 MachineBasicBlock *BB) const {
2589 assert(Subtarget->isFP64bit());
2591 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2592 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2593 DebugLoc DL = MI->getDebugLoc();
2594 unsigned Wd = MI->getOperand(0).getReg();
2595 unsigned Wd_in = MI->getOperand(1).getReg();
2596 unsigned Lane = MI->getOperand(2).getImm();
2597 unsigned Fs = MI->getOperand(3).getReg();
2598 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2600 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
2603 .addImm(Mips::sub_64);
2604 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
2609 MI->eraseFromParent(); // The pseudo instruction is gone now.
2613 // Emit the FILL_FW pseudo instruction.
2615 // fill_fw_pseudo $wd, $fs
2617 // implicit_def $wt1
2618 // insert_subreg $wt2:subreg_lo, $wt1, $fs
2619 // splati.w $wd, $wt2[0]
2621 MipsSETargetLowering::emitFILL_FW(MachineInstr *MI,
2622 MachineBasicBlock *BB) const {
2623 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2624 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2625 DebugLoc DL = MI->getDebugLoc();
2626 unsigned Wd = MI->getOperand(0).getReg();
2627 unsigned Fs = MI->getOperand(1).getReg();
2628 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2629 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2631 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
2632 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
2635 .addImm(Mips::sub_lo);
2636 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0);
2638 MI->eraseFromParent(); // The pseudo instruction is gone now.
2642 // Emit the FILL_FD pseudo instruction.
2644 // fill_fd_pseudo $wd, $fs
2646 // implicit_def $wt1
2647 // insert_subreg $wt2:subreg_64, $wt1, $fs
2648 // splati.d $wd, $wt2[0]
2650 MipsSETargetLowering::emitFILL_FD(MachineInstr *MI,
2651 MachineBasicBlock *BB) const {
2652 assert(Subtarget->isFP64bit());
2654 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2655 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2656 DebugLoc DL = MI->getDebugLoc();
2657 unsigned Wd = MI->getOperand(0).getReg();
2658 unsigned Fs = MI->getOperand(1).getReg();
2659 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2660 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2662 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
2663 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
2666 .addImm(Mips::sub_64);
2667 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0);
2669 MI->eraseFromParent(); // The pseudo instruction is gone now.
2673 // Emit the FEXP2_W_1 pseudo instructions.
2675 // fexp2_w_1_pseudo $wd, $wt
2678 // fexp2.w $wd, $ws, $wt
2680 MipsSETargetLowering::emitFEXP2_W_1(MachineInstr *MI,
2681 MachineBasicBlock *BB) const {
2682 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2683 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2684 const TargetRegisterClass *RC = &Mips::MSA128WRegClass;
2685 unsigned Ws1 = RegInfo.createVirtualRegister(RC);
2686 unsigned Ws2 = RegInfo.createVirtualRegister(RC);
2687 DebugLoc DL = MI->getDebugLoc();
2689 // Splat 1.0 into a vector
2690 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1);
2691 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1);
2693 // Emit 1.0 * fexp2(Wt)
2694 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI->getOperand(0).getReg())
2696 .addReg(MI->getOperand(1).getReg());
2698 MI->eraseFromParent(); // The pseudo instruction is gone now.
2702 // Emit the FEXP2_D_1 pseudo instructions.
2704 // fexp2_d_1_pseudo $wd, $wt
2707 // fexp2.d $wd, $ws, $wt
2709 MipsSETargetLowering::emitFEXP2_D_1(MachineInstr *MI,
2710 MachineBasicBlock *BB) const {
2711 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2712 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2713 const TargetRegisterClass *RC = &Mips::MSA128DRegClass;
2714 unsigned Ws1 = RegInfo.createVirtualRegister(RC);
2715 unsigned Ws2 = RegInfo.createVirtualRegister(RC);
2716 DebugLoc DL = MI->getDebugLoc();
2718 // Splat 1.0 into a vector
2719 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1);
2720 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1);
2722 // Emit 1.0 * fexp2(Wt)
2723 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI->getOperand(0).getReg())
2725 .addReg(MI->getOperand(1).getReg());
2727 MI->eraseFromParent(); // The pseudo instruction is gone now.