1 //===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsTargetLowering specialized for mips32/64.
12 //===----------------------------------------------------------------------===//
13 #include "MipsSEISelLowering.h"
14 #include "MipsRegisterInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/IR/Intrinsics.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Target/TargetInstrInfo.h"
25 EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
26 cl::desc("MIPS: Enable tail calls."), cl::init(false));
28 MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
29 : MipsTargetLowering(TM) {
30 // Set up the register classes
32 clearRegisterClasses();
34 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
37 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
39 if (Subtarget->hasDSP()) {
40 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
42 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
43 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
45 // Expand all builtin opcodes.
46 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
47 setOperationAction(Opc, VecTys[i], Expand);
49 setOperationAction(ISD::ADD, VecTys[i], Legal);
50 setOperationAction(ISD::SUB, VecTys[i], Legal);
51 setOperationAction(ISD::LOAD, VecTys[i], Legal);
52 setOperationAction(ISD::STORE, VecTys[i], Legal);
53 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
56 // Expand all truncating stores and extending loads.
57 unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
58 unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
60 for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
61 for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
62 setTruncStoreAction((MVT::SimpleValueType)VT0,
63 (MVT::SimpleValueType)VT1, Expand);
65 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
66 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
67 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
70 setTargetDAGCombine(ISD::SHL);
71 setTargetDAGCombine(ISD::SRA);
72 setTargetDAGCombine(ISD::SRL);
73 setTargetDAGCombine(ISD::SETCC);
74 setTargetDAGCombine(ISD::VSELECT);
77 if (Subtarget->hasDSPR2())
78 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
80 if (Subtarget->hasMSA()) {
81 addMSAType(MVT::v16i8);
82 addMSAType(MVT::v8i16);
83 addMSAType(MVT::v4i32);
84 addMSAType(MVT::v2i64);
85 addMSAType(MVT::v8f16);
86 addMSAType(MVT::v4f32);
87 addMSAType(MVT::v2f64);
90 if (!TM.Options.UseSoftFloat) {
91 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
93 // When dealing with single precision only, use libcalls
94 if (!Subtarget->isSingleFloat()) {
95 if (Subtarget->isFP64bit())
96 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
98 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
102 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
103 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
104 setOperationAction(ISD::MULHS, MVT::i32, Custom);
105 setOperationAction(ISD::MULHU, MVT::i32, Custom);
108 setOperationAction(ISD::MULHS, MVT::i64, Custom);
109 setOperationAction(ISD::MULHU, MVT::i64, Custom);
110 setOperationAction(ISD::MUL, MVT::i64, Custom);
113 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
114 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
116 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
117 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
118 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
119 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
120 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
121 setOperationAction(ISD::LOAD, MVT::i32, Custom);
122 setOperationAction(ISD::STORE, MVT::i32, Custom);
124 setTargetDAGCombine(ISD::ADDE);
125 setTargetDAGCombine(ISD::SUBE);
126 setTargetDAGCombine(ISD::MUL);
128 computeRegisterProperties();
131 const MipsTargetLowering *
132 llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
133 return new MipsSETargetLowering(TM);
137 MipsSETargetLowering::addMSAType(MVT::SimpleValueType Ty) {
138 addRegisterClass(Ty, &Mips::MSA128RegClass);
140 // Expand all builtin opcodes.
141 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
142 setOperationAction(Opc, Ty, Expand);
144 setOperationAction(ISD::LOAD, Ty, Legal);
145 setOperationAction(ISD::STORE, Ty, Legal);
146 setOperationAction(ISD::BITCAST, Ty, Legal);
150 MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
151 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
164 SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
165 SelectionDAG &DAG) const {
166 switch(Op.getOpcode()) {
167 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
168 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
169 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
170 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
171 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
172 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
173 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
175 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
176 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
179 return MipsTargetLowering::LowerOperation(Op, DAG);
183 // Transforms a subgraph in CurDAG if the following pattern is found:
184 // (addc multLo, Lo0), (adde multHi, Hi0),
186 // multHi/Lo: product of multiplication
187 // Lo0: initial value of Lo register
188 // Hi0: initial value of Hi register
189 // Return true if pattern matching was successful.
190 static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
191 // ADDENode's second operand must be a flag output of an ADDC node in order
192 // for the matching to be successful.
193 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
195 if (ADDCNode->getOpcode() != ISD::ADDC)
198 SDValue MultHi = ADDENode->getOperand(0);
199 SDValue MultLo = ADDCNode->getOperand(0);
200 SDNode *MultNode = MultHi.getNode();
201 unsigned MultOpc = MultHi.getOpcode();
203 // MultHi and MultLo must be generated by the same node,
204 if (MultLo.getNode() != MultNode)
207 // and it must be a multiplication.
208 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
211 // MultLo amd MultHi must be the first and second output of MultNode
213 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
216 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
217 // of the values of MultNode, in which case MultNode will be removed in later
219 // If there exist users other than ADDENode or ADDCNode, this function returns
220 // here, which will result in MultNode being mapped to a single MULT
221 // instruction node rather than a pair of MULT and MADD instructions being
223 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
228 // Initialize accumulator.
229 SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
230 ADDCNode->getOperand(1),
231 ADDENode->getOperand(1));
233 // create MipsMAdd(u) node
234 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
236 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
237 MultNode->getOperand(0),// Factor 0
238 MultNode->getOperand(1),// Factor 1
241 // replace uses of adde and addc here
242 if (!SDValue(ADDCNode, 0).use_empty()) {
243 SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
244 SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
246 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
248 if (!SDValue(ADDENode, 0).use_empty()) {
249 SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
250 SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
252 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
259 // Transforms a subgraph in CurDAG if the following pattern is found:
260 // (addc Lo0, multLo), (sube Hi0, multHi),
262 // multHi/Lo: product of multiplication
263 // Lo0: initial value of Lo register
264 // Hi0: initial value of Hi register
265 // Return true if pattern matching was successful.
266 static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
267 // SUBENode's second operand must be a flag output of an SUBC node in order
268 // for the matching to be successful.
269 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
271 if (SUBCNode->getOpcode() != ISD::SUBC)
274 SDValue MultHi = SUBENode->getOperand(1);
275 SDValue MultLo = SUBCNode->getOperand(1);
276 SDNode *MultNode = MultHi.getNode();
277 unsigned MultOpc = MultHi.getOpcode();
279 // MultHi and MultLo must be generated by the same node,
280 if (MultLo.getNode() != MultNode)
283 // and it must be a multiplication.
284 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
287 // MultLo amd MultHi must be the first and second output of MultNode
289 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
292 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
293 // of the values of MultNode, in which case MultNode will be removed in later
295 // If there exist users other than SUBENode or SUBCNode, this function returns
296 // here, which will result in MultNode being mapped to a single MULT
297 // instruction node rather than a pair of MULT and MSUB instructions being
299 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
304 // Initialize accumulator.
305 SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
306 SUBCNode->getOperand(0),
307 SUBENode->getOperand(0));
309 // create MipsSub(u) node
310 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
312 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
313 MultNode->getOperand(0),// Factor 0
314 MultNode->getOperand(1),// Factor 1
317 // replace uses of sube and subc here
318 if (!SDValue(SUBCNode, 0).use_empty()) {
319 SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
320 SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
322 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
324 if (!SDValue(SUBENode, 0).use_empty()) {
325 SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
326 SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
328 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
334 static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
335 TargetLowering::DAGCombinerInfo &DCI,
336 const MipsSubtarget *Subtarget) {
337 if (DCI.isBeforeLegalize())
340 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
342 return SDValue(N, 0);
347 static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
348 TargetLowering::DAGCombinerInfo &DCI,
349 const MipsSubtarget *Subtarget) {
350 if (DCI.isBeforeLegalize())
353 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
355 return SDValue(N, 0);
360 static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
361 EVT ShiftTy, SelectionDAG &DAG) {
362 // Clear the upper (64 - VT.sizeInBits) bits.
363 C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
367 return DAG.getConstant(0, VT);
373 // If c is power of 2, return (shl x, log2(c)).
374 if (isPowerOf2_64(C))
375 return DAG.getNode(ISD::SHL, DL, VT, X,
376 DAG.getConstant(Log2_64(C), ShiftTy));
378 unsigned Log2Ceil = Log2_64_Ceil(C);
379 uint64_t Floor = 1LL << Log2_64(C);
380 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
382 // If |c - floor_c| <= |c - ceil_c|,
383 // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
384 // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
385 if (C - Floor <= Ceil - C) {
386 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
387 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
388 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
391 // If |c - floor_c| > |c - ceil_c|,
392 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
393 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
394 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
395 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
398 static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
399 const TargetLowering::DAGCombinerInfo &DCI,
400 const MipsSETargetLowering *TL) {
401 EVT VT = N->getValueType(0);
403 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
405 return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N),
406 VT, TL->getScalarShiftAmountTy(VT), DAG);
408 return SDValue(N, 0);
411 static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
413 const MipsSubtarget *Subtarget) {
414 // See if this is a vector splat immediate node.
415 APInt SplatValue, SplatUndef;
416 unsigned SplatBitSize;
418 unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
419 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
422 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
423 EltSize, !Subtarget->isLittle()) ||
424 (SplatBitSize != EltSize) ||
425 (SplatValue.getZExtValue() >= EltSize))
428 return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
429 DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
432 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
433 TargetLowering::DAGCombinerInfo &DCI,
434 const MipsSubtarget *Subtarget) {
435 EVT Ty = N->getValueType(0);
437 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
440 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
443 static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
444 TargetLowering::DAGCombinerInfo &DCI,
445 const MipsSubtarget *Subtarget) {
446 EVT Ty = N->getValueType(0);
448 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
451 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
455 static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
456 TargetLowering::DAGCombinerInfo &DCI,
457 const MipsSubtarget *Subtarget) {
458 EVT Ty = N->getValueType(0);
460 if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
463 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
466 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
467 bool IsV216 = (Ty == MVT::v2i16);
471 case ISD::SETNE: return true;
475 case ISD::SETGE: return IsV216;
479 case ISD::SETUGE: return !IsV216;
480 default: return false;
484 static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
485 EVT Ty = N->getValueType(0);
487 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
490 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
493 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
494 N->getOperand(1), N->getOperand(2));
497 static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
498 EVT Ty = N->getValueType(0);
500 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
503 SDValue SetCC = N->getOperand(0);
505 if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
508 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
509 SetCC.getOperand(0), SetCC.getOperand(1), N->getOperand(1),
510 N->getOperand(2), SetCC.getOperand(2));
514 MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
515 SelectionDAG &DAG = DCI.DAG;
518 switch (N->getOpcode()) {
520 return performADDECombine(N, DAG, DCI, Subtarget);
522 return performSUBECombine(N, DAG, DCI, Subtarget);
524 return performMULCombine(N, DAG, DCI, this);
526 return performSHLCombine(N, DAG, DCI, Subtarget);
528 return performSRACombine(N, DAG, DCI, Subtarget);
530 return performSRLCombine(N, DAG, DCI, Subtarget);
532 return performVSELECTCombine(N, DAG);
534 Val = performSETCCCombine(N, DAG);
542 return MipsTargetLowering::PerformDAGCombine(N, DCI);
546 MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
547 MachineBasicBlock *BB) const {
548 switch (MI->getOpcode()) {
550 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
551 case Mips::BPOSGE32_PSEUDO:
552 return emitBPOSGE32(MI, BB);
556 bool MipsSETargetLowering::
557 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
558 unsigned NextStackOffset,
559 const MipsFunctionInfo& FI) const {
560 if (!EnableMipsTailCalls)
563 // Return false if either the callee or caller has a byval argument.
564 if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
567 // Return true if the callee's argument area is no larger than the
569 return NextStackOffset <= FI.getIncomingArgSize();
572 void MipsSETargetLowering::
573 getOpndList(SmallVectorImpl<SDValue> &Ops,
574 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
575 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
576 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
577 // T9 should contain the address of the callee function if
578 // -reloction-model=pic or it is an indirect call.
579 if (IsPICCall || !GlobalOrExternal) {
580 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
581 RegsToPass.push_front(std::make_pair(T9Reg, Callee));
583 Ops.push_back(Callee);
585 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
586 InternalLinkage, CLI, Callee, Chain);
589 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
590 bool HasLo, bool HasHi,
591 SelectionDAG &DAG) const {
592 EVT Ty = Op.getOperand(0).getValueType();
594 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
595 Op.getOperand(0), Op.getOperand(1));
599 Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
600 DAG.getConstant(Mips::sub_lo, MVT::i32));
602 Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
603 DAG.getConstant(Mips::sub_hi, MVT::i32));
605 if (!HasLo || !HasHi)
606 return HasLo ? Lo : Hi;
608 SDValue Vals[] = { Lo, Hi };
609 return DAG.getMergeValues(Vals, 2, DL);
613 static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
614 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
615 DAG.getConstant(0, MVT::i32));
616 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
617 DAG.getConstant(1, MVT::i32));
618 return DAG.getNode(MipsISD::InsertLOHI, DL, MVT::Untyped, InLo, InHi);
621 static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
622 SDValue Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
623 DAG.getConstant(Mips::sub_lo, MVT::i32));
624 SDValue Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
625 DAG.getConstant(Mips::sub_hi, MVT::i32));
626 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
629 // This function expands mips intrinsic nodes which have 64-bit input operands
632 // out64 = intrinsic-node in64
634 // lo = copy (extract-element (in64, 0))
635 // hi = copy (extract-element (in64, 1))
636 // mips-specific-node
639 // out64 = merge-values (v0, v1)
641 static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
643 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
644 SmallVector<SDValue, 3> Ops;
647 // See if Op has a chain input.
649 Ops.push_back(Op->getOperand(OpNo++));
651 // The next operand is the intrinsic opcode.
652 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
654 // See if the next operand has type i64.
655 SDValue Opnd = Op->getOperand(++OpNo), In64;
657 if (Opnd.getValueType() == MVT::i64)
658 In64 = initAccumulator(Opnd, DL, DAG);
662 // Push the remaining operands.
663 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
664 Ops.push_back(Op->getOperand(OpNo));
666 // Add In64 to the end of the list.
671 SmallVector<EVT, 2> ResTys;
673 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
675 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
678 SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size());
679 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
684 assert(Val->getValueType(1) == MVT::Other);
685 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
686 return DAG.getMergeValues(Vals, 2, DL);
689 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
690 SelectionDAG &DAG) const {
691 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
694 case Intrinsic::mips_shilo:
695 return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
696 case Intrinsic::mips_dpau_h_qbl:
697 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
698 case Intrinsic::mips_dpau_h_qbr:
699 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
700 case Intrinsic::mips_dpsu_h_qbl:
701 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
702 case Intrinsic::mips_dpsu_h_qbr:
703 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
704 case Intrinsic::mips_dpa_w_ph:
705 return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
706 case Intrinsic::mips_dps_w_ph:
707 return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
708 case Intrinsic::mips_dpax_w_ph:
709 return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
710 case Intrinsic::mips_dpsx_w_ph:
711 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
712 case Intrinsic::mips_mulsa_w_ph:
713 return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
714 case Intrinsic::mips_mult:
715 return lowerDSPIntr(Op, DAG, MipsISD::Mult);
716 case Intrinsic::mips_multu:
717 return lowerDSPIntr(Op, DAG, MipsISD::Multu);
718 case Intrinsic::mips_madd:
719 return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
720 case Intrinsic::mips_maddu:
721 return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
722 case Intrinsic::mips_msub:
723 return lowerDSPIntr(Op, DAG, MipsISD::MSub);
724 case Intrinsic::mips_msubu:
725 return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
729 SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
730 SelectionDAG &DAG) const {
731 switch (cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue()) {
734 case Intrinsic::mips_extp:
735 return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
736 case Intrinsic::mips_extpdp:
737 return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
738 case Intrinsic::mips_extr_w:
739 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
740 case Intrinsic::mips_extr_r_w:
741 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
742 case Intrinsic::mips_extr_rs_w:
743 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
744 case Intrinsic::mips_extr_s_h:
745 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
746 case Intrinsic::mips_mthlip:
747 return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
748 case Intrinsic::mips_mulsaq_s_w_ph:
749 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
750 case Intrinsic::mips_maq_s_w_phl:
751 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
752 case Intrinsic::mips_maq_s_w_phr:
753 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
754 case Intrinsic::mips_maq_sa_w_phl:
755 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
756 case Intrinsic::mips_maq_sa_w_phr:
757 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
758 case Intrinsic::mips_dpaq_s_w_ph:
759 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
760 case Intrinsic::mips_dpsq_s_w_ph:
761 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
762 case Intrinsic::mips_dpaq_sa_l_w:
763 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
764 case Intrinsic::mips_dpsq_sa_l_w:
765 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
766 case Intrinsic::mips_dpaqx_s_w_ph:
767 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
768 case Intrinsic::mips_dpaqx_sa_w_ph:
769 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
770 case Intrinsic::mips_dpsqx_s_w_ph:
771 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
772 case Intrinsic::mips_dpsqx_sa_w_ph:
773 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
777 MachineBasicBlock * MipsSETargetLowering::
778 emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
780 // bposge32_pseudo $vr0
790 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
792 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
793 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
794 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
795 DebugLoc DL = MI->getDebugLoc();
796 const BasicBlock *LLVM_BB = BB->getBasicBlock();
797 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
798 MachineFunction *F = BB->getParent();
799 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
800 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
801 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
806 // Transfer the remainder of BB and its successor edges to Sink.
807 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
809 Sink->transferSuccessorsAndUpdatePHIs(BB);
812 BB->addSuccessor(FBB);
813 BB->addSuccessor(TBB);
814 FBB->addSuccessor(Sink);
815 TBB->addSuccessor(Sink);
817 // Insert the real bposge32 instruction to $BB.
818 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
821 unsigned VR2 = RegInfo.createVirtualRegister(RC);
822 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
823 .addReg(Mips::ZERO).addImm(0);
824 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
827 unsigned VR1 = RegInfo.createVirtualRegister(RC);
828 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
829 .addReg(Mips::ZERO).addImm(1);
831 // Insert phi function to $Sink.
832 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
833 MI->getOperand(0).getReg())
834 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
836 MI->eraseFromParent(); // The pseudo instruction is gone now.