1 //===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsTargetLowering specialized for mips32/64.
12 //===----------------------------------------------------------------------===//
13 #include "MipsSEISelLowering.h"
14 #include "MipsRegisterInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/IR/Intrinsics.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/Target/TargetInstrInfo.h"
26 #define DEBUG_TYPE "mips-isel"
29 EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
30 cl::desc("MIPS: Enable tail calls."), cl::init(false));
32 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
33 cl::desc("Expand double precision loads and "
34 "stores to their single precision "
37 MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
38 : MipsTargetLowering(TM) {
39 // Set up the register classes
40 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
43 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
45 if (Subtarget->hasDSP() || Subtarget->hasMSA()) {
46 // Expand all truncating stores and extending loads.
47 unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
48 unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
50 for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
51 for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
52 setTruncStoreAction((MVT::SimpleValueType)VT0,
53 (MVT::SimpleValueType)VT1, Expand);
55 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
56 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
57 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
61 if (Subtarget->hasDSP()) {
62 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
64 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
65 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
67 // Expand all builtin opcodes.
68 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
69 setOperationAction(Opc, VecTys[i], Expand);
71 setOperationAction(ISD::ADD, VecTys[i], Legal);
72 setOperationAction(ISD::SUB, VecTys[i], Legal);
73 setOperationAction(ISD::LOAD, VecTys[i], Legal);
74 setOperationAction(ISD::STORE, VecTys[i], Legal);
75 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
78 setTargetDAGCombine(ISD::SHL);
79 setTargetDAGCombine(ISD::SRA);
80 setTargetDAGCombine(ISD::SRL);
81 setTargetDAGCombine(ISD::SETCC);
82 setTargetDAGCombine(ISD::VSELECT);
85 if (Subtarget->hasDSPR2())
86 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
88 if (Subtarget->hasMSA()) {
89 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
90 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
91 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
92 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
93 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
94 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
95 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
97 setTargetDAGCombine(ISD::AND);
98 setTargetDAGCombine(ISD::OR);
99 setTargetDAGCombine(ISD::SRA);
100 setTargetDAGCombine(ISD::VSELECT);
101 setTargetDAGCombine(ISD::XOR);
104 if (!Subtarget->mipsSEUsesSoftFloat()) {
105 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
107 // When dealing with single precision only, use libcalls
108 if (!Subtarget->isSingleFloat()) {
109 if (Subtarget->isFP64bit())
110 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
112 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
116 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
117 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
118 setOperationAction(ISD::MULHS, MVT::i32, Custom);
119 setOperationAction(ISD::MULHU, MVT::i32, Custom);
121 if (Subtarget->hasCnMips())
122 setOperationAction(ISD::MUL, MVT::i64, Legal);
123 else if (isGP64bit())
124 setOperationAction(ISD::MUL, MVT::i64, Custom);
127 setOperationAction(ISD::MULHS, MVT::i64, Custom);
128 setOperationAction(ISD::MULHU, MVT::i64, Custom);
131 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
132 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
134 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
135 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
136 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
137 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
138 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
139 setOperationAction(ISD::LOAD, MVT::i32, Custom);
140 setOperationAction(ISD::STORE, MVT::i32, Custom);
142 setTargetDAGCombine(ISD::ADDE);
143 setTargetDAGCombine(ISD::SUBE);
144 setTargetDAGCombine(ISD::MUL);
146 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
147 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
148 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
151 setOperationAction(ISD::LOAD, MVT::f64, Custom);
152 setOperationAction(ISD::STORE, MVT::f64, Custom);
155 computeRegisterProperties();
158 const MipsTargetLowering *
159 llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
160 return new MipsSETargetLowering(TM);
163 // Enable MSA support for the given integer type and Register class.
164 void MipsSETargetLowering::
165 addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
166 addRegisterClass(Ty, RC);
168 // Expand all builtin opcodes.
169 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
170 setOperationAction(Opc, Ty, Expand);
172 setOperationAction(ISD::BITCAST, Ty, Legal);
173 setOperationAction(ISD::LOAD, Ty, Legal);
174 setOperationAction(ISD::STORE, Ty, Legal);
175 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
176 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
177 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
179 setOperationAction(ISD::ADD, Ty, Legal);
180 setOperationAction(ISD::AND, Ty, Legal);
181 setOperationAction(ISD::CTLZ, Ty, Legal);
182 setOperationAction(ISD::CTPOP, Ty, Legal);
183 setOperationAction(ISD::MUL, Ty, Legal);
184 setOperationAction(ISD::OR, Ty, Legal);
185 setOperationAction(ISD::SDIV, Ty, Legal);
186 setOperationAction(ISD::SREM, Ty, Legal);
187 setOperationAction(ISD::SHL, Ty, Legal);
188 setOperationAction(ISD::SRA, Ty, Legal);
189 setOperationAction(ISD::SRL, Ty, Legal);
190 setOperationAction(ISD::SUB, Ty, Legal);
191 setOperationAction(ISD::UDIV, Ty, Legal);
192 setOperationAction(ISD::UREM, Ty, Legal);
193 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom);
194 setOperationAction(ISD::VSELECT, Ty, Legal);
195 setOperationAction(ISD::XOR, Ty, Legal);
197 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
198 setOperationAction(ISD::FP_TO_SINT, Ty, Legal);
199 setOperationAction(ISD::FP_TO_UINT, Ty, Legal);
200 setOperationAction(ISD::SINT_TO_FP, Ty, Legal);
201 setOperationAction(ISD::UINT_TO_FP, Ty, Legal);
204 setOperationAction(ISD::SETCC, Ty, Legal);
205 setCondCodeAction(ISD::SETNE, Ty, Expand);
206 setCondCodeAction(ISD::SETGE, Ty, Expand);
207 setCondCodeAction(ISD::SETGT, Ty, Expand);
208 setCondCodeAction(ISD::SETUGE, Ty, Expand);
209 setCondCodeAction(ISD::SETUGT, Ty, Expand);
212 // Enable MSA support for the given floating-point type and Register class.
213 void MipsSETargetLowering::
214 addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
215 addRegisterClass(Ty, RC);
217 // Expand all builtin opcodes.
218 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
219 setOperationAction(Opc, Ty, Expand);
221 setOperationAction(ISD::LOAD, Ty, Legal);
222 setOperationAction(ISD::STORE, Ty, Legal);
223 setOperationAction(ISD::BITCAST, Ty, Legal);
224 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
225 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
226 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
228 if (Ty != MVT::v8f16) {
229 setOperationAction(ISD::FABS, Ty, Legal);
230 setOperationAction(ISD::FADD, Ty, Legal);
231 setOperationAction(ISD::FDIV, Ty, Legal);
232 setOperationAction(ISD::FEXP2, Ty, Legal);
233 setOperationAction(ISD::FLOG2, Ty, Legal);
234 setOperationAction(ISD::FMA, Ty, Legal);
235 setOperationAction(ISD::FMUL, Ty, Legal);
236 setOperationAction(ISD::FRINT, Ty, Legal);
237 setOperationAction(ISD::FSQRT, Ty, Legal);
238 setOperationAction(ISD::FSUB, Ty, Legal);
239 setOperationAction(ISD::VSELECT, Ty, Legal);
241 setOperationAction(ISD::SETCC, Ty, Legal);
242 setCondCodeAction(ISD::SETOGE, Ty, Expand);
243 setCondCodeAction(ISD::SETOGT, Ty, Expand);
244 setCondCodeAction(ISD::SETUGE, Ty, Expand);
245 setCondCodeAction(ISD::SETUGT, Ty, Expand);
246 setCondCodeAction(ISD::SETGE, Ty, Expand);
247 setCondCodeAction(ISD::SETGT, Ty, Expand);
252 MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
255 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
268 SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
269 SelectionDAG &DAG) const {
270 switch(Op.getOpcode()) {
271 case ISD::LOAD: return lowerLOAD(Op, DAG);
272 case ISD::STORE: return lowerSTORE(Op, DAG);
273 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
274 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
275 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
276 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
277 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
278 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
279 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
281 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
282 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
283 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
284 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
285 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
286 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG);
289 return MipsTargetLowering::LowerOperation(Op, DAG);
293 // Transforms a subgraph in CurDAG if the following pattern is found:
294 // (addc multLo, Lo0), (adde multHi, Hi0),
296 // multHi/Lo: product of multiplication
297 // Lo0: initial value of Lo register
298 // Hi0: initial value of Hi register
299 // Return true if pattern matching was successful.
300 static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
301 // ADDENode's second operand must be a flag output of an ADDC node in order
302 // for the matching to be successful.
303 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
305 if (ADDCNode->getOpcode() != ISD::ADDC)
308 SDValue MultHi = ADDENode->getOperand(0);
309 SDValue MultLo = ADDCNode->getOperand(0);
310 SDNode *MultNode = MultHi.getNode();
311 unsigned MultOpc = MultHi.getOpcode();
313 // MultHi and MultLo must be generated by the same node,
314 if (MultLo.getNode() != MultNode)
317 // and it must be a multiplication.
318 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
321 // MultLo amd MultHi must be the first and second output of MultNode
323 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
326 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
327 // of the values of MultNode, in which case MultNode will be removed in later
329 // If there exist users other than ADDENode or ADDCNode, this function returns
330 // here, which will result in MultNode being mapped to a single MULT
331 // instruction node rather than a pair of MULT and MADD instructions being
333 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
338 // Initialize accumulator.
339 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
340 ADDCNode->getOperand(1),
341 ADDENode->getOperand(1));
343 // create MipsMAdd(u) node
344 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
346 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
347 MultNode->getOperand(0),// Factor 0
348 MultNode->getOperand(1),// Factor 1
351 // replace uses of adde and addc here
352 if (!SDValue(ADDCNode, 0).use_empty()) {
353 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
354 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
356 if (!SDValue(ADDENode, 0).use_empty()) {
357 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
358 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
365 // Transforms a subgraph in CurDAG if the following pattern is found:
366 // (addc Lo0, multLo), (sube Hi0, multHi),
368 // multHi/Lo: product of multiplication
369 // Lo0: initial value of Lo register
370 // Hi0: initial value of Hi register
371 // Return true if pattern matching was successful.
372 static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
373 // SUBENode's second operand must be a flag output of an SUBC node in order
374 // for the matching to be successful.
375 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
377 if (SUBCNode->getOpcode() != ISD::SUBC)
380 SDValue MultHi = SUBENode->getOperand(1);
381 SDValue MultLo = SUBCNode->getOperand(1);
382 SDNode *MultNode = MultHi.getNode();
383 unsigned MultOpc = MultHi.getOpcode();
385 // MultHi and MultLo must be generated by the same node,
386 if (MultLo.getNode() != MultNode)
389 // and it must be a multiplication.
390 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
393 // MultLo amd MultHi must be the first and second output of MultNode
395 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
398 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
399 // of the values of MultNode, in which case MultNode will be removed in later
401 // If there exist users other than SUBENode or SUBCNode, this function returns
402 // here, which will result in MultNode being mapped to a single MULT
403 // instruction node rather than a pair of MULT and MSUB instructions being
405 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
410 // Initialize accumulator.
411 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
412 SUBCNode->getOperand(0),
413 SUBENode->getOperand(0));
415 // create MipsSub(u) node
416 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
418 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
419 MultNode->getOperand(0),// Factor 0
420 MultNode->getOperand(1),// Factor 1
423 // replace uses of sube and subc here
424 if (!SDValue(SUBCNode, 0).use_empty()) {
425 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub);
426 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
428 if (!SDValue(SUBENode, 0).use_empty()) {
429 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MSub);
430 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
436 static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
437 TargetLowering::DAGCombinerInfo &DCI,
438 const MipsSubtarget *Subtarget) {
439 if (DCI.isBeforeLegalize())
442 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
444 return SDValue(N, 0);
449 // Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
451 // Performs the following transformations:
452 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
453 // sign/zero-extension is completely overwritten by the new one performed by
455 // - Removes redundant zero extensions performed by an ISD::AND.
456 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
457 TargetLowering::DAGCombinerInfo &DCI,
458 const MipsSubtarget *Subtarget) {
459 if (!Subtarget->hasMSA())
462 SDValue Op0 = N->getOperand(0);
463 SDValue Op1 = N->getOperand(1);
464 unsigned Op0Opcode = Op0->getOpcode();
466 // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
467 // where $d + 1 == 2^n and n == 32
468 // or $d + 1 == 2^n and n <= 32 and ZExt
469 // -> (MipsVExtractZExt $a, $b, $c)
470 if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
471 Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
472 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
477 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
479 if (Log2IfPositive <= 0)
480 return SDValue(); // Mask+1 is not a power of 2
482 SDValue Op0Op2 = Op0->getOperand(2);
483 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
484 unsigned ExtendTySize = ExtendTy.getSizeInBits();
485 unsigned Log2 = Log2IfPositive;
487 if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
488 Log2 == ExtendTySize) {
489 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
490 DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT,
492 makeArrayRef(Ops, Op0->getNumOperands()));
500 // Determine if the specified node is a constant vector splat.
502 // Returns true and sets Imm if:
503 // * N is a ISD::BUILD_VECTOR representing a constant splat
505 // This function is quite similar to MipsSEDAGToDAGISel::selectVSplat. The
506 // differences are that it assumes the MSA has already been checked and the
507 // arbitrary requirement for a maximum of 32-bit integers isn't applied (and
508 // must not be in order for binsri.d to be selectable).
509 static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) {
510 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N.getNode());
515 APInt SplatValue, SplatUndef;
516 unsigned SplatBitSize;
519 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
528 // Test whether the given node is an all-ones build_vector.
529 static bool isVectorAllOnes(SDValue N) {
530 // Look through bitcasts. Endianness doesn't matter because we are looking
531 // for an all-ones value.
532 if (N->getOpcode() == ISD::BITCAST)
533 N = N->getOperand(0);
535 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
540 APInt SplatValue, SplatUndef;
541 unsigned SplatBitSize;
544 // Endianness doesn't matter in this context because we are looking for
545 // an all-ones value.
546 if (BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs))
547 return SplatValue.isAllOnesValue();
552 // Test whether N is the bitwise inverse of OfNode.
553 static bool isBitwiseInverse(SDValue N, SDValue OfNode) {
554 if (N->getOpcode() != ISD::XOR)
557 if (isVectorAllOnes(N->getOperand(0)))
558 return N->getOperand(1) == OfNode;
560 if (isVectorAllOnes(N->getOperand(1)))
561 return N->getOperand(0) == OfNode;
566 // Perform combines where ISD::OR is the root node.
568 // Performs the following transformations:
569 // - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
570 // where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
572 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
573 TargetLowering::DAGCombinerInfo &DCI,
574 const MipsSubtarget *Subtarget) {
575 if (!Subtarget->hasMSA())
578 EVT Ty = N->getValueType(0);
580 if (!Ty.is128BitVector())
583 SDValue Op0 = N->getOperand(0);
584 SDValue Op1 = N->getOperand(1);
586 if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
587 SDValue Op0Op0 = Op0->getOperand(0);
588 SDValue Op0Op1 = Op0->getOperand(1);
589 SDValue Op1Op0 = Op1->getOperand(0);
590 SDValue Op1Op1 = Op1->getOperand(1);
591 bool IsLittleEndian = !Subtarget->isLittle();
593 SDValue IfSet, IfClr, Cond;
594 bool IsConstantMask = false;
597 // If Op0Op0 is an appropriate mask, try to find it's inverse in either
598 // Op1Op0, or Op1Op1. Keep track of the Cond, IfSet, and IfClr nodes, while
600 // IfClr will be set if we find a valid match.
601 if (isVSplat(Op0Op0, Mask, IsLittleEndian)) {
605 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
606 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
608 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
609 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
612 IsConstantMask = true;
615 // If IfClr is not yet set, and Op0Op1 is an appropriate mask, try the same
616 // thing again using this mask.
617 // IfClr will be set if we find a valid match.
618 if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) {
622 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
623 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
625 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
626 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
629 IsConstantMask = true;
632 // If IfClr is not yet set, try looking for a non-constant match.
633 // IfClr will be set if we find a valid match amongst the eight
635 if (!IfClr.getNode()) {
636 if (isBitwiseInverse(Op0Op0, Op1Op0)) {
640 } else if (isBitwiseInverse(Op0Op1, Op1Op0)) {
644 } else if (isBitwiseInverse(Op0Op0, Op1Op1)) {
648 } else if (isBitwiseInverse(Op0Op1, Op1Op1)) {
652 } else if (isBitwiseInverse(Op1Op0, Op0Op0)) {
656 } else if (isBitwiseInverse(Op1Op1, Op0Op0)) {
660 } else if (isBitwiseInverse(Op1Op0, Op0Op1)) {
664 } else if (isBitwiseInverse(Op1Op1, Op0Op1)) {
671 // At this point, IfClr will be set if we have a valid match.
672 if (!IfClr.getNode())
675 assert(Cond.getNode() && IfSet.getNode());
677 // Fold degenerate cases.
678 if (IsConstantMask) {
679 if (Mask.isAllOnesValue())
685 // Transform the DAG into an equivalent VSELECT.
686 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr);
692 static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
693 TargetLowering::DAGCombinerInfo &DCI,
694 const MipsSubtarget *Subtarget) {
695 if (DCI.isBeforeLegalize())
698 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
700 return SDValue(N, 0);
705 static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
706 EVT ShiftTy, SelectionDAG &DAG) {
707 // Clear the upper (64 - VT.sizeInBits) bits.
708 C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
712 return DAG.getConstant(0, VT);
718 // If c is power of 2, return (shl x, log2(c)).
719 if (isPowerOf2_64(C))
720 return DAG.getNode(ISD::SHL, DL, VT, X,
721 DAG.getConstant(Log2_64(C), ShiftTy));
723 unsigned Log2Ceil = Log2_64_Ceil(C);
724 uint64_t Floor = 1LL << Log2_64(C);
725 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
727 // If |c - floor_c| <= |c - ceil_c|,
728 // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
729 // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
730 if (C - Floor <= Ceil - C) {
731 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
732 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
733 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
736 // If |c - floor_c| > |c - ceil_c|,
737 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
738 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
739 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
740 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
743 static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
744 const TargetLowering::DAGCombinerInfo &DCI,
745 const MipsSETargetLowering *TL) {
746 EVT VT = N->getValueType(0);
748 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
750 return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N),
751 VT, TL->getScalarShiftAmountTy(VT), DAG);
753 return SDValue(N, 0);
756 static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
758 const MipsSubtarget *Subtarget) {
759 // See if this is a vector splat immediate node.
760 APInt SplatValue, SplatUndef;
761 unsigned SplatBitSize;
763 unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
764 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
766 if (!Subtarget->hasDSP())
770 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
771 EltSize, !Subtarget->isLittle()) ||
772 (SplatBitSize != EltSize) ||
773 (SplatValue.getZExtValue() >= EltSize))
776 return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
777 DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
780 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
781 TargetLowering::DAGCombinerInfo &DCI,
782 const MipsSubtarget *Subtarget) {
783 EVT Ty = N->getValueType(0);
785 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
788 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
791 // Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
792 // constant splats into MipsISD::SHRA_DSP for DSPr2.
794 // Performs the following transformations:
795 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
796 // sign/zero-extension is completely overwritten by the new one performed by
797 // the ISD::SRA and ISD::SHL nodes.
798 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
801 // See performDSPShiftCombine for more information about the transformation
803 static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
804 TargetLowering::DAGCombinerInfo &DCI,
805 const MipsSubtarget *Subtarget) {
806 EVT Ty = N->getValueType(0);
808 if (Subtarget->hasMSA()) {
809 SDValue Op0 = N->getOperand(0);
810 SDValue Op1 = N->getOperand(1);
812 // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
813 // where $d + sizeof($c) == 32
814 // or $d + sizeof($c) <= 32 and SExt
815 // -> (MipsVExtractSExt $a, $b, $c)
816 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
817 SDValue Op0Op0 = Op0->getOperand(0);
818 ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
823 if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
824 Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT)
827 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
828 unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
830 if (TotalBits == 32 ||
831 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
833 SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
834 Op0Op0->getOperand(2) };
835 DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT,
837 makeArrayRef(Ops, Op0Op0->getNumOperands()));
843 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
846 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
850 static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
851 TargetLowering::DAGCombinerInfo &DCI,
852 const MipsSubtarget *Subtarget) {
853 EVT Ty = N->getValueType(0);
855 if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
858 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
861 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
862 bool IsV216 = (Ty == MVT::v2i16);
866 case ISD::SETNE: return true;
870 case ISD::SETGE: return IsV216;
874 case ISD::SETUGE: return !IsV216;
875 default: return false;
879 static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
880 EVT Ty = N->getValueType(0);
882 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
885 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
888 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
889 N->getOperand(1), N->getOperand(2));
892 static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
893 EVT Ty = N->getValueType(0);
895 if (Ty.is128BitVector() && Ty.isInteger()) {
896 // Try the following combines:
897 // (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b)
898 // (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b)
899 // (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b)
900 // (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b)
901 // (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b)
902 // (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b)
903 // (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b)
904 // (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b)
905 // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but
906 // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the
908 SDValue Op0 = N->getOperand(0);
910 if (Op0->getOpcode() != ISD::SETCC)
913 ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get();
916 if (CondCode == ISD::SETLT || CondCode == ISD::SETLE)
918 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE)
923 SDValue Op1 = N->getOperand(1);
924 SDValue Op2 = N->getOperand(2);
925 SDValue Op0Op0 = Op0->getOperand(0);
926 SDValue Op0Op1 = Op0->getOperand(1);
928 if (Op1 == Op0Op0 && Op2 == Op0Op1)
929 return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N),
931 else if (Op1 == Op0Op1 && Op2 == Op0Op0)
932 return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N),
934 } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) {
935 SDValue SetCC = N->getOperand(0);
937 if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
940 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
941 SetCC.getOperand(0), SetCC.getOperand(1),
942 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
948 static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
949 const MipsSubtarget *Subtarget) {
950 EVT Ty = N->getValueType(0);
952 if (Subtarget->hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
953 // Try the following combines:
954 // (xor (or $a, $b), (build_vector allones))
955 // (xor (or $a, $b), (bitcast (build_vector allones)))
956 SDValue Op0 = N->getOperand(0);
957 SDValue Op1 = N->getOperand(1);
960 if (ISD::isBuildVectorAllOnes(Op0.getNode()))
962 else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
967 if (NotOp->getOpcode() == ISD::OR)
968 return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
969 NotOp->getOperand(1));
976 MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
977 SelectionDAG &DAG = DCI.DAG;
980 switch (N->getOpcode()) {
982 return performADDECombine(N, DAG, DCI, Subtarget);
984 Val = performANDCombine(N, DAG, DCI, Subtarget);
987 Val = performORCombine(N, DAG, DCI, Subtarget);
990 return performSUBECombine(N, DAG, DCI, Subtarget);
992 return performMULCombine(N, DAG, DCI, this);
994 return performSHLCombine(N, DAG, DCI, Subtarget);
996 return performSRACombine(N, DAG, DCI, Subtarget);
998 return performSRLCombine(N, DAG, DCI, Subtarget);
1000 return performVSELECTCombine(N, DAG);
1002 Val = performXORCombine(N, DAG, Subtarget);
1005 Val = performSETCCCombine(N, DAG);
1009 if (Val.getNode()) {
1010 DEBUG(dbgs() << "\nMipsSE DAG Combine:\n";
1011 N->printrWithDepth(dbgs(), &DAG);
1012 dbgs() << "\n=> \n";
1013 Val.getNode()->printrWithDepth(dbgs(), &DAG);
1018 return MipsTargetLowering::PerformDAGCombine(N, DCI);
1022 MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1023 MachineBasicBlock *BB) const {
1024 switch (MI->getOpcode()) {
1026 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
1027 case Mips::BPOSGE32_PSEUDO:
1028 return emitBPOSGE32(MI, BB);
1029 case Mips::SNZ_B_PSEUDO:
1030 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
1031 case Mips::SNZ_H_PSEUDO:
1032 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
1033 case Mips::SNZ_W_PSEUDO:
1034 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
1035 case Mips::SNZ_D_PSEUDO:
1036 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
1037 case Mips::SNZ_V_PSEUDO:
1038 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
1039 case Mips::SZ_B_PSEUDO:
1040 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
1041 case Mips::SZ_H_PSEUDO:
1042 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
1043 case Mips::SZ_W_PSEUDO:
1044 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
1045 case Mips::SZ_D_PSEUDO:
1046 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
1047 case Mips::SZ_V_PSEUDO:
1048 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
1049 case Mips::COPY_FW_PSEUDO:
1050 return emitCOPY_FW(MI, BB);
1051 case Mips::COPY_FD_PSEUDO:
1052 return emitCOPY_FD(MI, BB);
1053 case Mips::INSERT_FW_PSEUDO:
1054 return emitINSERT_FW(MI, BB);
1055 case Mips::INSERT_FD_PSEUDO:
1056 return emitINSERT_FD(MI, BB);
1057 case Mips::INSERT_B_VIDX_PSEUDO:
1058 return emitINSERT_DF_VIDX(MI, BB, 1, false);
1059 case Mips::INSERT_H_VIDX_PSEUDO:
1060 return emitINSERT_DF_VIDX(MI, BB, 2, false);
1061 case Mips::INSERT_W_VIDX_PSEUDO:
1062 return emitINSERT_DF_VIDX(MI, BB, 4, false);
1063 case Mips::INSERT_D_VIDX_PSEUDO:
1064 return emitINSERT_DF_VIDX(MI, BB, 8, false);
1065 case Mips::INSERT_FW_VIDX_PSEUDO:
1066 return emitINSERT_DF_VIDX(MI, BB, 4, true);
1067 case Mips::INSERT_FD_VIDX_PSEUDO:
1068 return emitINSERT_DF_VIDX(MI, BB, 8, true);
1069 case Mips::FILL_FW_PSEUDO:
1070 return emitFILL_FW(MI, BB);
1071 case Mips::FILL_FD_PSEUDO:
1072 return emitFILL_FD(MI, BB);
1073 case Mips::FEXP2_W_1_PSEUDO:
1074 return emitFEXP2_W_1(MI, BB);
1075 case Mips::FEXP2_D_1_PSEUDO:
1076 return emitFEXP2_D_1(MI, BB);
1080 bool MipsSETargetLowering::
1081 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
1082 unsigned NextStackOffset,
1083 const MipsFunctionInfo& FI) const {
1084 if (!EnableMipsTailCalls)
1087 // Return false if either the callee or caller has a byval argument.
1088 if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
1091 // Return true if the callee's argument area is no larger than the
1093 return NextStackOffset <= FI.getIncomingArgSize();
1096 void MipsSETargetLowering::
1097 getOpndList(SmallVectorImpl<SDValue> &Ops,
1098 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
1099 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
1100 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
1101 Ops.push_back(Callee);
1102 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
1103 InternalLinkage, CLI, Callee, Chain);
1106 SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1107 LoadSDNode &Nd = *cast<LoadSDNode>(Op);
1109 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1110 return MipsTargetLowering::lowerLOAD(Op, DAG);
1112 // Replace a double precision load with two i32 loads and a buildpair64.
1114 SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1115 EVT PtrVT = Ptr.getValueType();
1117 // i32 load from lower address.
1118 SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
1119 MachinePointerInfo(), Nd.isVolatile(),
1120 Nd.isNonTemporal(), Nd.isInvariant(),
1123 // i32 load from higher address.
1124 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
1125 SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
1126 MachinePointerInfo(), Nd.isVolatile(),
1127 Nd.isNonTemporal(), Nd.isInvariant(),
1128 std::min(Nd.getAlignment(), 4U));
1130 if (!Subtarget->isLittle())
1133 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
1134 SDValue Ops[2] = {BP, Hi.getValue(1)};
1135 return DAG.getMergeValues(Ops, DL);
1138 SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1139 StoreSDNode &Nd = *cast<StoreSDNode>(Op);
1141 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1142 return MipsTargetLowering::lowerSTORE(Op, DAG);
1144 // Replace a double precision store with two extractelement64s and i32 stores.
1146 SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1147 EVT PtrVT = Ptr.getValueType();
1148 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1149 Val, DAG.getConstant(0, MVT::i32));
1150 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1151 Val, DAG.getConstant(1, MVT::i32));
1153 if (!Subtarget->isLittle())
1156 // i32 store to lower address.
1157 Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
1158 Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
1161 // i32 store to higher address.
1162 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
1163 return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
1164 Nd.isVolatile(), Nd.isNonTemporal(),
1165 std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo());
1168 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
1169 bool HasLo, bool HasHi,
1170 SelectionDAG &DAG) const {
1171 EVT Ty = Op.getOperand(0).getValueType();
1173 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
1174 Op.getOperand(0), Op.getOperand(1));
1178 Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult);
1180 Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult);
1182 if (!HasLo || !HasHi)
1183 return HasLo ? Lo : Hi;
1185 SDValue Vals[] = { Lo, Hi };
1186 return DAG.getMergeValues(Vals, DL);
1190 static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
1191 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1192 DAG.getConstant(0, MVT::i32));
1193 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1194 DAG.getConstant(1, MVT::i32));
1195 return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
1198 static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
1199 SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op);
1200 SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op);
1201 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
1204 // This function expands mips intrinsic nodes which have 64-bit input operands
1205 // or output values.
1207 // out64 = intrinsic-node in64
1209 // lo = copy (extract-element (in64, 0))
1210 // hi = copy (extract-element (in64, 1))
1211 // mips-specific-node
1214 // out64 = merge-values (v0, v1)
1216 static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1218 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
1219 SmallVector<SDValue, 3> Ops;
1222 // See if Op has a chain input.
1224 Ops.push_back(Op->getOperand(OpNo++));
1226 // The next operand is the intrinsic opcode.
1227 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
1229 // See if the next operand has type i64.
1230 SDValue Opnd = Op->getOperand(++OpNo), In64;
1232 if (Opnd.getValueType() == MVT::i64)
1233 In64 = initAccumulator(Opnd, DL, DAG);
1235 Ops.push_back(Opnd);
1237 // Push the remaining operands.
1238 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
1239 Ops.push_back(Op->getOperand(OpNo));
1241 // Add In64 to the end of the list.
1243 Ops.push_back(In64);
1246 SmallVector<EVT, 2> ResTys;
1248 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1250 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
1253 SDValue Val = DAG.getNode(Opc, DL, ResTys, Ops);
1254 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
1259 assert(Val->getValueType(1) == MVT::Other);
1260 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
1261 return DAG.getMergeValues(Vals, DL);
1264 // Lower an MSA copy intrinsic into the specified SelectionDAG node
1265 static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1267 SDValue Vec = Op->getOperand(1);
1268 SDValue Idx = Op->getOperand(2);
1269 EVT ResTy = Op->getValueType(0);
1270 EVT EltTy = Vec->getValueType(0).getVectorElementType();
1272 SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1273 DAG.getValueType(EltTy));
1278 static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) {
1279 EVT ResVecTy = Op->getValueType(0);
1280 EVT ViaVecTy = ResVecTy;
1283 // When ResVecTy == MVT::v2i64, LaneA is the upper 32 bits of the lane and
1284 // LaneB is the lower 32-bits. Otherwise LaneA and LaneB are alternating
1287 SDValue LaneB = Op->getOperand(2);
1289 if (ResVecTy == MVT::v2i64) {
1290 LaneA = DAG.getConstant(0, MVT::i32);
1291 ViaVecTy = MVT::v4i32;
1295 SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,
1296 LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
1298 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy,
1299 makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
1301 if (ViaVecTy != ResVecTy)
1302 Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, Result);
1307 static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) {
1308 return DAG.getConstant(Op->getConstantOperandVal(ImmOp), Op->getValueType(0));
1311 static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue,
1312 bool BigEndian, SelectionDAG &DAG) {
1313 EVT ViaVecTy = VecTy;
1314 SDValue SplatValueA = SplatValue;
1315 SDValue SplatValueB = SplatValue;
1316 SDLoc DL(SplatValue);
1318 if (VecTy == MVT::v2i64) {
1319 // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's.
1320 ViaVecTy = MVT::v4i32;
1322 SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue);
1323 SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue,
1324 DAG.getConstant(32, MVT::i32));
1325 SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB);
1328 // We currently hold the parts in little endian order. Swap them if
1331 std::swap(SplatValueA, SplatValueB);
1333 SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1334 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1335 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1336 SplatValueA, SplatValueB, SplatValueA, SplatValueB };
1338 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy,
1339 makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
1341 if (VecTy != ViaVecTy)
1342 Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);
1347 static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG,
1348 unsigned Opc, SDValue Imm,
1350 EVT VecTy = Op->getValueType(0);
1354 // The DAG Combiner can't constant fold bitcasted vectors yet so we must do it
1356 if (VecTy == MVT::v2i64) {
1357 if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) {
1358 APInt BitImm = APInt(64, 1) << CImm->getAPIntValue();
1360 SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), MVT::i32);
1361 SDValue BitImmLoOp = DAG.getConstant(BitImm.trunc(32), MVT::i32);
1364 std::swap(BitImmLoOp, BitImmHiOp);
1367 DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
1368 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, BitImmLoOp,
1369 BitImmHiOp, BitImmLoOp, BitImmHiOp));
1373 if (!Exp2Imm.getNode()) {
1374 // We couldnt constant fold, do a vector shift instead
1376 // Extend i32 to i64 if necessary. Sign or zero extend doesn't matter since
1377 // only values 0-63 are valid.
1378 if (VecTy == MVT::v2i64)
1379 Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm);
1381 Exp2Imm = getBuildVectorSplat(VecTy, Imm, BigEndian, DAG);
1384 DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, VecTy), Exp2Imm);
1387 return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm);
1390 static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG) {
1391 EVT ResTy = Op->getValueType(0);
1393 SDValue One = DAG.getConstant(1, ResTy);
1394 SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, Op->getOperand(2));
1396 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
1397 DAG.getNOT(DL, Bit, ResTy));
1400 static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) {
1402 EVT ResTy = Op->getValueType(0);
1403 APInt BitImm = APInt(ResTy.getVectorElementType().getSizeInBits(), 1)
1404 << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue();
1405 SDValue BitMask = DAG.getConstant(~BitImm, ResTy);
1407 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
1410 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1411 SelectionDAG &DAG) const {
1414 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
1417 case Intrinsic::mips_shilo:
1418 return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1419 case Intrinsic::mips_dpau_h_qbl:
1420 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1421 case Intrinsic::mips_dpau_h_qbr:
1422 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1423 case Intrinsic::mips_dpsu_h_qbl:
1424 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1425 case Intrinsic::mips_dpsu_h_qbr:
1426 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1427 case Intrinsic::mips_dpa_w_ph:
1428 return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1429 case Intrinsic::mips_dps_w_ph:
1430 return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1431 case Intrinsic::mips_dpax_w_ph:
1432 return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1433 case Intrinsic::mips_dpsx_w_ph:
1434 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1435 case Intrinsic::mips_mulsa_w_ph:
1436 return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1437 case Intrinsic::mips_mult:
1438 return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1439 case Intrinsic::mips_multu:
1440 return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1441 case Intrinsic::mips_madd:
1442 return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1443 case Intrinsic::mips_maddu:
1444 return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1445 case Intrinsic::mips_msub:
1446 return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1447 case Intrinsic::mips_msubu:
1448 return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
1449 case Intrinsic::mips_addv_b:
1450 case Intrinsic::mips_addv_h:
1451 case Intrinsic::mips_addv_w:
1452 case Intrinsic::mips_addv_d:
1453 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1455 case Intrinsic::mips_addvi_b:
1456 case Intrinsic::mips_addvi_h:
1457 case Intrinsic::mips_addvi_w:
1458 case Intrinsic::mips_addvi_d:
1459 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1460 lowerMSASplatImm(Op, 2, DAG));
1461 case Intrinsic::mips_and_v:
1462 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1464 case Intrinsic::mips_andi_b:
1465 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1466 lowerMSASplatImm(Op, 2, DAG));
1467 case Intrinsic::mips_bclr_b:
1468 case Intrinsic::mips_bclr_h:
1469 case Intrinsic::mips_bclr_w:
1470 case Intrinsic::mips_bclr_d:
1471 return lowerMSABitClear(Op, DAG);
1472 case Intrinsic::mips_bclri_b:
1473 case Intrinsic::mips_bclri_h:
1474 case Intrinsic::mips_bclri_w:
1475 case Intrinsic::mips_bclri_d:
1476 return lowerMSABitClearImm(Op, DAG);
1477 case Intrinsic::mips_binsli_b:
1478 case Intrinsic::mips_binsli_h:
1479 case Intrinsic::mips_binsli_w:
1480 case Intrinsic::mips_binsli_d: {
1481 // binsli_x(IfClear, IfSet, nbits) -> (vselect LBitsMask, IfSet, IfClear)
1482 EVT VecTy = Op->getValueType(0);
1483 EVT EltTy = VecTy.getVectorElementType();
1484 APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(),
1485 Op->getConstantOperandVal(3));
1486 return DAG.getNode(ISD::VSELECT, DL, VecTy,
1487 DAG.getConstant(Mask, VecTy, true), Op->getOperand(2),
1490 case Intrinsic::mips_binsri_b:
1491 case Intrinsic::mips_binsri_h:
1492 case Intrinsic::mips_binsri_w:
1493 case Intrinsic::mips_binsri_d: {
1494 // binsri_x(IfClear, IfSet, nbits) -> (vselect RBitsMask, IfSet, IfClear)
1495 EVT VecTy = Op->getValueType(0);
1496 EVT EltTy = VecTy.getVectorElementType();
1497 APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(),
1498 Op->getConstantOperandVal(3));
1499 return DAG.getNode(ISD::VSELECT, DL, VecTy,
1500 DAG.getConstant(Mask, VecTy, true), Op->getOperand(2),
1503 case Intrinsic::mips_bmnz_v:
1504 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1505 Op->getOperand(2), Op->getOperand(1));
1506 case Intrinsic::mips_bmnzi_b:
1507 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1508 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2),
1510 case Intrinsic::mips_bmz_v:
1511 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1512 Op->getOperand(1), Op->getOperand(2));
1513 case Intrinsic::mips_bmzi_b:
1514 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1515 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1),
1517 case Intrinsic::mips_bneg_b:
1518 case Intrinsic::mips_bneg_h:
1519 case Intrinsic::mips_bneg_w:
1520 case Intrinsic::mips_bneg_d: {
1521 EVT VecTy = Op->getValueType(0);
1522 SDValue One = DAG.getConstant(1, VecTy);
1524 return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),
1525 DAG.getNode(ISD::SHL, DL, VecTy, One,
1526 Op->getOperand(2)));
1528 case Intrinsic::mips_bnegi_b:
1529 case Intrinsic::mips_bnegi_h:
1530 case Intrinsic::mips_bnegi_w:
1531 case Intrinsic::mips_bnegi_d:
1532 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2),
1533 !Subtarget->isLittle());
1534 case Intrinsic::mips_bnz_b:
1535 case Intrinsic::mips_bnz_h:
1536 case Intrinsic::mips_bnz_w:
1537 case Intrinsic::mips_bnz_d:
1538 return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),
1540 case Intrinsic::mips_bnz_v:
1541 return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),
1543 case Intrinsic::mips_bsel_v:
1544 // bsel_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1545 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1546 Op->getOperand(1), Op->getOperand(3),
1548 case Intrinsic::mips_bseli_b:
1549 // bseli_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
1550 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1551 Op->getOperand(1), lowerMSASplatImm(Op, 3, DAG),
1553 case Intrinsic::mips_bset_b:
1554 case Intrinsic::mips_bset_h:
1555 case Intrinsic::mips_bset_w:
1556 case Intrinsic::mips_bset_d: {
1557 EVT VecTy = Op->getValueType(0);
1558 SDValue One = DAG.getConstant(1, VecTy);
1560 return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),
1561 DAG.getNode(ISD::SHL, DL, VecTy, One,
1562 Op->getOperand(2)));
1564 case Intrinsic::mips_bseti_b:
1565 case Intrinsic::mips_bseti_h:
1566 case Intrinsic::mips_bseti_w:
1567 case Intrinsic::mips_bseti_d:
1568 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2),
1569 !Subtarget->isLittle());
1570 case Intrinsic::mips_bz_b:
1571 case Intrinsic::mips_bz_h:
1572 case Intrinsic::mips_bz_w:
1573 case Intrinsic::mips_bz_d:
1574 return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),
1576 case Intrinsic::mips_bz_v:
1577 return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),
1579 case Intrinsic::mips_ceq_b:
1580 case Intrinsic::mips_ceq_h:
1581 case Intrinsic::mips_ceq_w:
1582 case Intrinsic::mips_ceq_d:
1583 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1584 Op->getOperand(2), ISD::SETEQ);
1585 case Intrinsic::mips_ceqi_b:
1586 case Intrinsic::mips_ceqi_h:
1587 case Intrinsic::mips_ceqi_w:
1588 case Intrinsic::mips_ceqi_d:
1589 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1590 lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ);
1591 case Intrinsic::mips_cle_s_b:
1592 case Intrinsic::mips_cle_s_h:
1593 case Intrinsic::mips_cle_s_w:
1594 case Intrinsic::mips_cle_s_d:
1595 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1596 Op->getOperand(2), ISD::SETLE);
1597 case Intrinsic::mips_clei_s_b:
1598 case Intrinsic::mips_clei_s_h:
1599 case Intrinsic::mips_clei_s_w:
1600 case Intrinsic::mips_clei_s_d:
1601 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1602 lowerMSASplatImm(Op, 2, DAG), ISD::SETLE);
1603 case Intrinsic::mips_cle_u_b:
1604 case Intrinsic::mips_cle_u_h:
1605 case Intrinsic::mips_cle_u_w:
1606 case Intrinsic::mips_cle_u_d:
1607 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1608 Op->getOperand(2), ISD::SETULE);
1609 case Intrinsic::mips_clei_u_b:
1610 case Intrinsic::mips_clei_u_h:
1611 case Intrinsic::mips_clei_u_w:
1612 case Intrinsic::mips_clei_u_d:
1613 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1614 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1615 case Intrinsic::mips_clt_s_b:
1616 case Intrinsic::mips_clt_s_h:
1617 case Intrinsic::mips_clt_s_w:
1618 case Intrinsic::mips_clt_s_d:
1619 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1620 Op->getOperand(2), ISD::SETLT);
1621 case Intrinsic::mips_clti_s_b:
1622 case Intrinsic::mips_clti_s_h:
1623 case Intrinsic::mips_clti_s_w:
1624 case Intrinsic::mips_clti_s_d:
1625 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1626 lowerMSASplatImm(Op, 2, DAG), ISD::SETLT);
1627 case Intrinsic::mips_clt_u_b:
1628 case Intrinsic::mips_clt_u_h:
1629 case Intrinsic::mips_clt_u_w:
1630 case Intrinsic::mips_clt_u_d:
1631 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1632 Op->getOperand(2), ISD::SETULT);
1633 case Intrinsic::mips_clti_u_b:
1634 case Intrinsic::mips_clti_u_h:
1635 case Intrinsic::mips_clti_u_w:
1636 case Intrinsic::mips_clti_u_d:
1637 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1638 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
1639 case Intrinsic::mips_copy_s_b:
1640 case Intrinsic::mips_copy_s_h:
1641 case Intrinsic::mips_copy_s_w:
1642 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1643 case Intrinsic::mips_copy_s_d:
1645 // Lower directly into VEXTRACT_SEXT_ELT since i64 is legal on Mips64.
1646 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1648 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1649 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1650 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1651 Op->getValueType(0), Op->getOperand(1),
1654 case Intrinsic::mips_copy_u_b:
1655 case Intrinsic::mips_copy_u_h:
1656 case Intrinsic::mips_copy_u_w:
1657 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1658 case Intrinsic::mips_copy_u_d:
1660 // Lower directly into VEXTRACT_ZEXT_ELT since i64 is legal on Mips64.
1661 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1663 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1664 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1665 // Note: When i64 is illegal, this results in copy_s.w instructions
1666 // instead of copy_u.w instructions. This makes no difference to the
1667 // behaviour since i64 is only illegal when the register file is 32-bit.
1668 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1669 Op->getValueType(0), Op->getOperand(1),
1672 case Intrinsic::mips_div_s_b:
1673 case Intrinsic::mips_div_s_h:
1674 case Intrinsic::mips_div_s_w:
1675 case Intrinsic::mips_div_s_d:
1676 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1678 case Intrinsic::mips_div_u_b:
1679 case Intrinsic::mips_div_u_h:
1680 case Intrinsic::mips_div_u_w:
1681 case Intrinsic::mips_div_u_d:
1682 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1684 case Intrinsic::mips_fadd_w:
1685 case Intrinsic::mips_fadd_d:
1686 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1688 // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1689 case Intrinsic::mips_fceq_w:
1690 case Intrinsic::mips_fceq_d:
1691 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1692 Op->getOperand(2), ISD::SETOEQ);
1693 case Intrinsic::mips_fcle_w:
1694 case Intrinsic::mips_fcle_d:
1695 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1696 Op->getOperand(2), ISD::SETOLE);
1697 case Intrinsic::mips_fclt_w:
1698 case Intrinsic::mips_fclt_d:
1699 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1700 Op->getOperand(2), ISD::SETOLT);
1701 case Intrinsic::mips_fcne_w:
1702 case Intrinsic::mips_fcne_d:
1703 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1704 Op->getOperand(2), ISD::SETONE);
1705 case Intrinsic::mips_fcor_w:
1706 case Intrinsic::mips_fcor_d:
1707 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1708 Op->getOperand(2), ISD::SETO);
1709 case Intrinsic::mips_fcueq_w:
1710 case Intrinsic::mips_fcueq_d:
1711 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1712 Op->getOperand(2), ISD::SETUEQ);
1713 case Intrinsic::mips_fcule_w:
1714 case Intrinsic::mips_fcule_d:
1715 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1716 Op->getOperand(2), ISD::SETULE);
1717 case Intrinsic::mips_fcult_w:
1718 case Intrinsic::mips_fcult_d:
1719 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1720 Op->getOperand(2), ISD::SETULT);
1721 case Intrinsic::mips_fcun_w:
1722 case Intrinsic::mips_fcun_d:
1723 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1724 Op->getOperand(2), ISD::SETUO);
1725 case Intrinsic::mips_fcune_w:
1726 case Intrinsic::mips_fcune_d:
1727 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1728 Op->getOperand(2), ISD::SETUNE);
1729 case Intrinsic::mips_fdiv_w:
1730 case Intrinsic::mips_fdiv_d:
1731 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1733 case Intrinsic::mips_ffint_u_w:
1734 case Intrinsic::mips_ffint_u_d:
1735 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
1737 case Intrinsic::mips_ffint_s_w:
1738 case Intrinsic::mips_ffint_s_d:
1739 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
1741 case Intrinsic::mips_fill_b:
1742 case Intrinsic::mips_fill_h:
1743 case Intrinsic::mips_fill_w:
1744 case Intrinsic::mips_fill_d: {
1745 SmallVector<SDValue, 16> Ops;
1746 EVT ResTy = Op->getValueType(0);
1748 for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i)
1749 Ops.push_back(Op->getOperand(1));
1751 // If ResTy is v2i64 then the type legalizer will break this node down into
1752 // an equivalent v4i32.
1753 return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, Ops);
1755 case Intrinsic::mips_fexp2_w:
1756 case Intrinsic::mips_fexp2_d: {
1757 EVT ResTy = Op->getValueType(0);
1759 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1760 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
1762 case Intrinsic::mips_flog2_w:
1763 case Intrinsic::mips_flog2_d:
1764 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
1765 case Intrinsic::mips_fmadd_w:
1766 case Intrinsic::mips_fmadd_d:
1767 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
1768 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1769 case Intrinsic::mips_fmul_w:
1770 case Intrinsic::mips_fmul_d:
1771 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1773 case Intrinsic::mips_fmsub_w:
1774 case Intrinsic::mips_fmsub_d: {
1775 EVT ResTy = Op->getValueType(0);
1776 return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1),
1777 DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy,
1778 Op->getOperand(2), Op->getOperand(3)));
1780 case Intrinsic::mips_frint_w:
1781 case Intrinsic::mips_frint_d:
1782 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
1783 case Intrinsic::mips_fsqrt_w:
1784 case Intrinsic::mips_fsqrt_d:
1785 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
1786 case Intrinsic::mips_fsub_w:
1787 case Intrinsic::mips_fsub_d:
1788 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1790 case Intrinsic::mips_ftrunc_u_w:
1791 case Intrinsic::mips_ftrunc_u_d:
1792 return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
1794 case Intrinsic::mips_ftrunc_s_w:
1795 case Intrinsic::mips_ftrunc_s_d:
1796 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
1798 case Intrinsic::mips_ilvev_b:
1799 case Intrinsic::mips_ilvev_h:
1800 case Intrinsic::mips_ilvev_w:
1801 case Intrinsic::mips_ilvev_d:
1802 return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),
1803 Op->getOperand(1), Op->getOperand(2));
1804 case Intrinsic::mips_ilvl_b:
1805 case Intrinsic::mips_ilvl_h:
1806 case Intrinsic::mips_ilvl_w:
1807 case Intrinsic::mips_ilvl_d:
1808 return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),
1809 Op->getOperand(1), Op->getOperand(2));
1810 case Intrinsic::mips_ilvod_b:
1811 case Intrinsic::mips_ilvod_h:
1812 case Intrinsic::mips_ilvod_w:
1813 case Intrinsic::mips_ilvod_d:
1814 return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),
1815 Op->getOperand(1), Op->getOperand(2));
1816 case Intrinsic::mips_ilvr_b:
1817 case Intrinsic::mips_ilvr_h:
1818 case Intrinsic::mips_ilvr_w:
1819 case Intrinsic::mips_ilvr_d:
1820 return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),
1821 Op->getOperand(1), Op->getOperand(2));
1822 case Intrinsic::mips_insert_b:
1823 case Intrinsic::mips_insert_h:
1824 case Intrinsic::mips_insert_w:
1825 case Intrinsic::mips_insert_d:
1826 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1827 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
1828 case Intrinsic::mips_insve_b:
1829 case Intrinsic::mips_insve_h:
1830 case Intrinsic::mips_insve_w:
1831 case Intrinsic::mips_insve_d:
1832 return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0),
1833 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3),
1834 DAG.getConstant(0, MVT::i32));
1835 case Intrinsic::mips_ldi_b:
1836 case Intrinsic::mips_ldi_h:
1837 case Intrinsic::mips_ldi_w:
1838 case Intrinsic::mips_ldi_d:
1839 return lowerMSASplatImm(Op, 1, DAG);
1840 case Intrinsic::mips_lsa:
1841 case Intrinsic::mips_dlsa: {
1842 EVT ResTy = Op->getValueType(0);
1843 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1844 DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
1845 Op->getOperand(2), Op->getOperand(3)));
1847 case Intrinsic::mips_maddv_b:
1848 case Intrinsic::mips_maddv_h:
1849 case Intrinsic::mips_maddv_w:
1850 case Intrinsic::mips_maddv_d: {
1851 EVT ResTy = Op->getValueType(0);
1852 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1853 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1854 Op->getOperand(2), Op->getOperand(3)));
1856 case Intrinsic::mips_max_s_b:
1857 case Intrinsic::mips_max_s_h:
1858 case Intrinsic::mips_max_s_w:
1859 case Intrinsic::mips_max_s_d:
1860 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1861 Op->getOperand(1), Op->getOperand(2));
1862 case Intrinsic::mips_max_u_b:
1863 case Intrinsic::mips_max_u_h:
1864 case Intrinsic::mips_max_u_w:
1865 case Intrinsic::mips_max_u_d:
1866 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1867 Op->getOperand(1), Op->getOperand(2));
1868 case Intrinsic::mips_maxi_s_b:
1869 case Intrinsic::mips_maxi_s_h:
1870 case Intrinsic::mips_maxi_s_w:
1871 case Intrinsic::mips_maxi_s_d:
1872 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1873 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1874 case Intrinsic::mips_maxi_u_b:
1875 case Intrinsic::mips_maxi_u_h:
1876 case Intrinsic::mips_maxi_u_w:
1877 case Intrinsic::mips_maxi_u_d:
1878 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1879 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1880 case Intrinsic::mips_min_s_b:
1881 case Intrinsic::mips_min_s_h:
1882 case Intrinsic::mips_min_s_w:
1883 case Intrinsic::mips_min_s_d:
1884 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1885 Op->getOperand(1), Op->getOperand(2));
1886 case Intrinsic::mips_min_u_b:
1887 case Intrinsic::mips_min_u_h:
1888 case Intrinsic::mips_min_u_w:
1889 case Intrinsic::mips_min_u_d:
1890 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1891 Op->getOperand(1), Op->getOperand(2));
1892 case Intrinsic::mips_mini_s_b:
1893 case Intrinsic::mips_mini_s_h:
1894 case Intrinsic::mips_mini_s_w:
1895 case Intrinsic::mips_mini_s_d:
1896 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1897 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1898 case Intrinsic::mips_mini_u_b:
1899 case Intrinsic::mips_mini_u_h:
1900 case Intrinsic::mips_mini_u_w:
1901 case Intrinsic::mips_mini_u_d:
1902 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1903 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1904 case Intrinsic::mips_mod_s_b:
1905 case Intrinsic::mips_mod_s_h:
1906 case Intrinsic::mips_mod_s_w:
1907 case Intrinsic::mips_mod_s_d:
1908 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
1910 case Intrinsic::mips_mod_u_b:
1911 case Intrinsic::mips_mod_u_h:
1912 case Intrinsic::mips_mod_u_w:
1913 case Intrinsic::mips_mod_u_d:
1914 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
1916 case Intrinsic::mips_mulv_b:
1917 case Intrinsic::mips_mulv_h:
1918 case Intrinsic::mips_mulv_w:
1919 case Intrinsic::mips_mulv_d:
1920 return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
1922 case Intrinsic::mips_msubv_b:
1923 case Intrinsic::mips_msubv_h:
1924 case Intrinsic::mips_msubv_w:
1925 case Intrinsic::mips_msubv_d: {
1926 EVT ResTy = Op->getValueType(0);
1927 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
1928 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1929 Op->getOperand(2), Op->getOperand(3)));
1931 case Intrinsic::mips_nlzc_b:
1932 case Intrinsic::mips_nlzc_h:
1933 case Intrinsic::mips_nlzc_w:
1934 case Intrinsic::mips_nlzc_d:
1935 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
1936 case Intrinsic::mips_nor_v: {
1937 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1938 Op->getOperand(1), Op->getOperand(2));
1939 return DAG.getNOT(DL, Res, Res->getValueType(0));
1941 case Intrinsic::mips_nori_b: {
1942 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1944 lowerMSASplatImm(Op, 2, DAG));
1945 return DAG.getNOT(DL, Res, Res->getValueType(0));
1947 case Intrinsic::mips_or_v:
1948 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
1950 case Intrinsic::mips_ori_b:
1951 return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1952 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1953 case Intrinsic::mips_pckev_b:
1954 case Intrinsic::mips_pckev_h:
1955 case Intrinsic::mips_pckev_w:
1956 case Intrinsic::mips_pckev_d:
1957 return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),
1958 Op->getOperand(1), Op->getOperand(2));
1959 case Intrinsic::mips_pckod_b:
1960 case Intrinsic::mips_pckod_h:
1961 case Intrinsic::mips_pckod_w:
1962 case Intrinsic::mips_pckod_d:
1963 return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),
1964 Op->getOperand(1), Op->getOperand(2));
1965 case Intrinsic::mips_pcnt_b:
1966 case Intrinsic::mips_pcnt_h:
1967 case Intrinsic::mips_pcnt_w:
1968 case Intrinsic::mips_pcnt_d:
1969 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
1970 case Intrinsic::mips_shf_b:
1971 case Intrinsic::mips_shf_h:
1972 case Intrinsic::mips_shf_w:
1973 return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),
1974 Op->getOperand(2), Op->getOperand(1));
1975 case Intrinsic::mips_sll_b:
1976 case Intrinsic::mips_sll_h:
1977 case Intrinsic::mips_sll_w:
1978 case Intrinsic::mips_sll_d:
1979 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
1981 case Intrinsic::mips_slli_b:
1982 case Intrinsic::mips_slli_h:
1983 case Intrinsic::mips_slli_w:
1984 case Intrinsic::mips_slli_d:
1985 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
1986 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1987 case Intrinsic::mips_splat_b:
1988 case Intrinsic::mips_splat_h:
1989 case Intrinsic::mips_splat_w:
1990 case Intrinsic::mips_splat_d:
1991 // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle
1992 // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because
1993 // EXTRACT_VECTOR_ELT can't extract i64's on MIPS32.
1994 // Instead we lower to MipsISD::VSHF and match from there.
1995 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
1996 lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1),
1998 case Intrinsic::mips_splati_b:
1999 case Intrinsic::mips_splati_h:
2000 case Intrinsic::mips_splati_w:
2001 case Intrinsic::mips_splati_d:
2002 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2003 lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
2005 case Intrinsic::mips_sra_b:
2006 case Intrinsic::mips_sra_h:
2007 case Intrinsic::mips_sra_w:
2008 case Intrinsic::mips_sra_d:
2009 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
2011 case Intrinsic::mips_srai_b:
2012 case Intrinsic::mips_srai_h:
2013 case Intrinsic::mips_srai_w:
2014 case Intrinsic::mips_srai_d:
2015 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
2016 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2017 case Intrinsic::mips_srl_b:
2018 case Intrinsic::mips_srl_h:
2019 case Intrinsic::mips_srl_w:
2020 case Intrinsic::mips_srl_d:
2021 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
2023 case Intrinsic::mips_srli_b:
2024 case Intrinsic::mips_srli_h:
2025 case Intrinsic::mips_srli_w:
2026 case Intrinsic::mips_srli_d:
2027 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
2028 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2029 case Intrinsic::mips_subv_b:
2030 case Intrinsic::mips_subv_h:
2031 case Intrinsic::mips_subv_w:
2032 case Intrinsic::mips_subv_d:
2033 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
2035 case Intrinsic::mips_subvi_b:
2036 case Intrinsic::mips_subvi_h:
2037 case Intrinsic::mips_subvi_w:
2038 case Intrinsic::mips_subvi_d:
2039 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
2040 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2041 case Intrinsic::mips_vshf_b:
2042 case Intrinsic::mips_vshf_h:
2043 case Intrinsic::mips_vshf_w:
2044 case Intrinsic::mips_vshf_d:
2045 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2046 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
2047 case Intrinsic::mips_xor_v:
2048 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
2050 case Intrinsic::mips_xori_b:
2051 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
2052 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2056 static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
2058 SDValue ChainIn = Op->getOperand(0);
2059 SDValue Address = Op->getOperand(2);
2060 SDValue Offset = Op->getOperand(3);
2061 EVT ResTy = Op->getValueType(0);
2062 EVT PtrTy = Address->getValueType(0);
2064 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2066 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
2070 SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
2071 SelectionDAG &DAG) const {
2072 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2076 case Intrinsic::mips_extp:
2077 return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
2078 case Intrinsic::mips_extpdp:
2079 return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
2080 case Intrinsic::mips_extr_w:
2081 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
2082 case Intrinsic::mips_extr_r_w:
2083 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
2084 case Intrinsic::mips_extr_rs_w:
2085 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
2086 case Intrinsic::mips_extr_s_h:
2087 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
2088 case Intrinsic::mips_mthlip:
2089 return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
2090 case Intrinsic::mips_mulsaq_s_w_ph:
2091 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
2092 case Intrinsic::mips_maq_s_w_phl:
2093 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
2094 case Intrinsic::mips_maq_s_w_phr:
2095 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
2096 case Intrinsic::mips_maq_sa_w_phl:
2097 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
2098 case Intrinsic::mips_maq_sa_w_phr:
2099 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
2100 case Intrinsic::mips_dpaq_s_w_ph:
2101 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
2102 case Intrinsic::mips_dpsq_s_w_ph:
2103 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
2104 case Intrinsic::mips_dpaq_sa_l_w:
2105 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
2106 case Intrinsic::mips_dpsq_sa_l_w:
2107 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
2108 case Intrinsic::mips_dpaqx_s_w_ph:
2109 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
2110 case Intrinsic::mips_dpaqx_sa_w_ph:
2111 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
2112 case Intrinsic::mips_dpsqx_s_w_ph:
2113 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
2114 case Intrinsic::mips_dpsqx_sa_w_ph:
2115 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
2116 case Intrinsic::mips_ld_b:
2117 case Intrinsic::mips_ld_h:
2118 case Intrinsic::mips_ld_w:
2119 case Intrinsic::mips_ld_d:
2120 return lowerMSALoadIntr(Op, DAG, Intr);
2124 static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
2126 SDValue ChainIn = Op->getOperand(0);
2127 SDValue Value = Op->getOperand(2);
2128 SDValue Address = Op->getOperand(3);
2129 SDValue Offset = Op->getOperand(4);
2130 EVT PtrTy = Address->getValueType(0);
2132 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2134 return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
2138 SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
2139 SelectionDAG &DAG) const {
2140 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2144 case Intrinsic::mips_st_b:
2145 case Intrinsic::mips_st_h:
2146 case Intrinsic::mips_st_w:
2147 case Intrinsic::mips_st_d:
2148 return lowerMSAStoreIntr(Op, DAG, Intr);
2152 /// \brief Check if the given BuildVectorSDNode is a splat.
2153 /// This method currently relies on DAG nodes being reused when equivalent,
2154 /// so it's possible for this to return false even when isConstantSplat returns
2156 static bool isSplatVector(const BuildVectorSDNode *N) {
2157 unsigned int nOps = N->getNumOperands();
2158 assert(nOps > 1 && "isSplatVector has 0 or 1 sized build vector");
2160 SDValue Operand0 = N->getOperand(0);
2162 for (unsigned int i = 1; i < nOps; ++i) {
2163 if (N->getOperand(i) != Operand0)
2170 // Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
2172 // The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
2173 // choose to sign-extend but we could have equally chosen zero-extend. The
2174 // DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
2175 // result into this node later (possibly changing it to a zero-extend in the
2177 SDValue MipsSETargetLowering::
2178 lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
2180 EVT ResTy = Op->getValueType(0);
2181 SDValue Op0 = Op->getOperand(0);
2182 EVT VecTy = Op0->getValueType(0);
2184 if (!VecTy.is128BitVector())
2187 if (ResTy.isInteger()) {
2188 SDValue Op1 = Op->getOperand(1);
2189 EVT EltTy = VecTy.getVectorElementType();
2190 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
2191 DAG.getValueType(EltTy));
2197 static bool isConstantOrUndef(const SDValue Op) {
2198 if (Op->getOpcode() == ISD::UNDEF)
2200 if (dyn_cast<ConstantSDNode>(Op))
2202 if (dyn_cast<ConstantFPSDNode>(Op))
2207 static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) {
2208 for (unsigned i = 0; i < Op->getNumOperands(); ++i)
2209 if (isConstantOrUndef(Op->getOperand(i)))
2214 // Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
2217 // Lowers according to the following rules:
2218 // - Constant splats are legal as-is as long as the SplatBitSize is a power of
2219 // 2 less than or equal to 64 and the value fits into a signed 10-bit
2221 // - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
2222 // is a power of 2 less than or equal to 64 and the value does not fit into a
2223 // signed 10-bit immediate
2224 // - Non-constant splats are legal as-is.
2225 // - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
2226 // - All others are illegal and must be expanded.
2227 SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
2228 SelectionDAG &DAG) const {
2229 BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
2230 EVT ResTy = Op->getValueType(0);
2232 APInt SplatValue, SplatUndef;
2233 unsigned SplatBitSize;
2236 if (!Subtarget->hasMSA() || !ResTy.is128BitVector())
2239 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
2241 !Subtarget->isLittle()) && SplatBitSize <= 64) {
2242 // We can only cope with 8, 16, 32, or 64-bit elements
2243 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
2247 // If the value fits into a simm10 then we can use ldi.[bhwd]
2248 // However, if it isn't an integer type we will have to bitcast from an
2249 // integer type first. Also, if there are any undefs, we must lower them
2250 // to defined values first.
2251 if (ResTy.isInteger() && !HasAnyUndefs && SplatValue.isSignedIntN(10))
2256 switch (SplatBitSize) {
2260 ViaVecTy = MVT::v16i8;
2263 ViaVecTy = MVT::v8i16;
2266 ViaVecTy = MVT::v4i32;
2269 // There's no fill.d to fall back on for 64-bit values
2273 // SelectionDAG::getConstant will promote SplatValue appropriately.
2274 SDValue Result = DAG.getConstant(SplatValue, ViaVecTy);
2276 // Bitcast to the type we originally wanted
2277 if (ViaVecTy != ResTy)
2278 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
2281 } else if (isSplatVector(Node))
2283 else if (!isConstantOrUndefBUILD_VECTOR(Node)) {
2284 // Use INSERT_VECTOR_ELT operations rather than expand to stores.
2285 // The resulting code is the same length as the expansion, but it doesn't
2286 // use memory operations
2287 EVT ResTy = Node->getValueType(0);
2289 assert(ResTy.isVector());
2291 unsigned NumElts = ResTy.getVectorNumElements();
2292 SDValue Vector = DAG.getUNDEF(ResTy);
2293 for (unsigned i = 0; i < NumElts; ++i) {
2294 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
2295 Node->getOperand(i),
2296 DAG.getConstant(i, MVT::i32));
2304 // Lower VECTOR_SHUFFLE into SHF (if possible).
2306 // SHF splits the vector into blocks of four elements, then shuffles these
2307 // elements according to a <4 x i2> constant (encoded as an integer immediate).
2309 // It is therefore possible to lower into SHF when the mask takes the form:
2310 // <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...>
2311 // When undef's appear they are treated as if they were whatever value is
2312 // necessary in order to fit the above form.
2315 // %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
2316 // <8 x i32> <i32 3, i32 2, i32 1, i32 0,
2317 // i32 7, i32 6, i32 5, i32 4>
2319 // (SHF_H $w0, $w1, 27)
2320 // where the 27 comes from:
2321 // 3 + (2 << 2) + (1 << 4) + (0 << 6)
2322 static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy,
2323 SmallVector<int, 16> Indices,
2324 SelectionDAG &DAG) {
2325 int SHFIndices[4] = { -1, -1, -1, -1 };
2327 if (Indices.size() < 4)
2330 for (unsigned i = 0; i < 4; ++i) {
2331 for (unsigned j = i; j < Indices.size(); j += 4) {
2332 int Idx = Indices[j];
2334 // Convert from vector index to 4-element subvector index
2335 // If an index refers to an element outside of the subvector then give up
2338 if (Idx < 0 || Idx >= 4)
2342 // If the mask has an undef, replace it with the current index.
2343 // Note that it might still be undef if the current index is also undef
2344 if (SHFIndices[i] == -1)
2345 SHFIndices[i] = Idx;
2347 // Check that non-undef values are the same as in the mask. If they
2348 // aren't then give up
2349 if (!(Idx == -1 || Idx == SHFIndices[i]))
2354 // Calculate the immediate. Replace any remaining undefs with zero
2356 for (int i = 3; i >= 0; --i) {
2357 int Idx = SHFIndices[i];
2366 return DAG.getNode(MipsISD::SHF, SDLoc(Op), ResTy,
2367 DAG.getConstant(Imm, MVT::i32), Op->getOperand(0));
2370 // Lower VECTOR_SHUFFLE into ILVEV (if possible).
2372 // ILVEV interleaves the even elements from each vector.
2374 // It is possible to lower into ILVEV when the mask takes the form:
2375 // <0, n, 2, n+2, 4, n+4, ...>
2376 // where n is the number of elements in the vector.
2378 // When undef's appear in the mask they are treated as if they were whatever
2379 // value is necessary in order to fit the above form.
2380 static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy,
2381 SmallVector<int, 16> Indices,
2382 SelectionDAG &DAG) {
2383 assert ((Indices.size() % 2) == 0);
2385 int WtIdx = ResTy.getVectorNumElements();
2387 for (unsigned i = 0; i < Indices.size(); i += 2) {
2388 if (Indices[i] != -1 && Indices[i] != WsIdx)
2390 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2396 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Op->getOperand(0),
2400 // Lower VECTOR_SHUFFLE into ILVOD (if possible).
2402 // ILVOD interleaves the odd elements from each vector.
2404 // It is possible to lower into ILVOD when the mask takes the form:
2405 // <1, n+1, 3, n+3, 5, n+5, ...>
2406 // where n is the number of elements in the vector.
2408 // When undef's appear in the mask they are treated as if they were whatever
2409 // value is necessary in order to fit the above form.
2410 static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy,
2411 SmallVector<int, 16> Indices,
2412 SelectionDAG &DAG) {
2413 assert ((Indices.size() % 2) == 0);
2415 int WtIdx = ResTy.getVectorNumElements() + 1;
2417 for (unsigned i = 0; i < Indices.size(); i += 2) {
2418 if (Indices[i] != -1 && Indices[i] != WsIdx)
2420 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2426 return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Op->getOperand(0),
2430 // Lower VECTOR_SHUFFLE into ILVL (if possible).
2432 // ILVL interleaves consecutive elements from the left half of each vector.
2434 // It is possible to lower into ILVL when the mask takes the form:
2435 // <0, n, 1, n+1, 2, n+2, ...>
2436 // where n is the number of elements in the vector.
2438 // When undef's appear in the mask they are treated as if they were whatever
2439 // value is necessary in order to fit the above form.
2440 static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy,
2441 SmallVector<int, 16> Indices,
2442 SelectionDAG &DAG) {
2443 assert ((Indices.size() % 2) == 0);
2445 int WtIdx = ResTy.getVectorNumElements();
2447 for (unsigned i = 0; i < Indices.size(); i += 2) {
2448 if (Indices[i] != -1 && Indices[i] != WsIdx)
2450 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2456 return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Op->getOperand(0),
2460 // Lower VECTOR_SHUFFLE into ILVR (if possible).
2462 // ILVR interleaves consecutive elements from the right half of each vector.
2464 // It is possible to lower into ILVR when the mask takes the form:
2465 // <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>
2466 // where n is the number of elements in the vector and x is half n.
2468 // When undef's appear in the mask they are treated as if they were whatever
2469 // value is necessary in order to fit the above form.
2470 static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy,
2471 SmallVector<int, 16> Indices,
2472 SelectionDAG &DAG) {
2473 assert ((Indices.size() % 2) == 0);
2474 unsigned NumElts = ResTy.getVectorNumElements();
2475 int WsIdx = NumElts / 2;
2476 int WtIdx = NumElts + NumElts / 2;
2478 for (unsigned i = 0; i < Indices.size(); i += 2) {
2479 if (Indices[i] != -1 && Indices[i] != WsIdx)
2481 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2487 return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Op->getOperand(0),
2491 // Lower VECTOR_SHUFFLE into PCKEV (if possible).
2493 // PCKEV copies the even elements of each vector into the result vector.
2495 // It is possible to lower into PCKEV when the mask takes the form:
2496 // <0, 2, 4, ..., n, n+2, n+4, ...>
2497 // where n is the number of elements in the vector.
2499 // When undef's appear in the mask they are treated as if they were whatever
2500 // value is necessary in order to fit the above form.
2501 static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy,
2502 SmallVector<int, 16> Indices,
2503 SelectionDAG &DAG) {
2504 assert ((Indices.size() % 2) == 0);
2507 for (unsigned i = 0; i < Indices.size(); ++i) {
2508 if (Indices[i] != -1 && Indices[i] != Idx)
2513 return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Op->getOperand(0),
2517 // Lower VECTOR_SHUFFLE into PCKOD (if possible).
2519 // PCKOD copies the odd elements of each vector into the result vector.
2521 // It is possible to lower into PCKOD when the mask takes the form:
2522 // <1, 3, 5, ..., n+1, n+3, n+5, ...>
2523 // where n is the number of elements in the vector.
2525 // When undef's appear in the mask they are treated as if they were whatever
2526 // value is necessary in order to fit the above form.
2527 static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy,
2528 SmallVector<int, 16> Indices,
2529 SelectionDAG &DAG) {
2530 assert ((Indices.size() % 2) == 0);
2533 for (unsigned i = 0; i < Indices.size(); ++i) {
2534 if (Indices[i] != -1 && Indices[i] != Idx)
2539 return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Op->getOperand(0),
2543 // Lower VECTOR_SHUFFLE into VSHF.
2545 // This mostly consists of converting the shuffle indices in Indices into a
2546 // BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is
2547 // also code to eliminate unused operands of the VECTOR_SHUFFLE. For example,
2548 // if the type is v8i16 and all the indices are less than 8 then the second
2549 // operand is unused and can be replaced with anything. We choose to replace it
2550 // with the used operand since this reduces the number of instructions overall.
2551 static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
2552 SmallVector<int, 16> Indices,
2553 SelectionDAG &DAG) {
2554 SmallVector<SDValue, 16> Ops;
2557 EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2558 EVT MaskEltTy = MaskVecTy.getVectorElementType();
2559 bool Using1stVec = false;
2560 bool Using2ndVec = false;
2562 int ResTyNumElts = ResTy.getVectorNumElements();
2564 for (int i = 0; i < ResTyNumElts; ++i) {
2565 // Idx == -1 means UNDEF
2566 int Idx = Indices[i];
2568 if (0 <= Idx && Idx < ResTyNumElts)
2570 if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
2574 for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
2576 Ops.push_back(DAG.getTargetConstant(*I, MaskEltTy));
2578 SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, Ops);
2580 if (Using1stVec && Using2ndVec) {
2581 Op0 = Op->getOperand(0);
2582 Op1 = Op->getOperand(1);
2583 } else if (Using1stVec)
2584 Op0 = Op1 = Op->getOperand(0);
2585 else if (Using2ndVec)
2586 Op0 = Op1 = Op->getOperand(1);
2588 llvm_unreachable("shuffle vector mask references neither vector operand?");
2590 // VECTOR_SHUFFLE concatenates the vectors in an vectorwise fashion.
2591 // <0b00, 0b01> + <0b10, 0b11> -> <0b00, 0b01, 0b10, 0b11>
2592 // VSHF concatenates the vectors in a bitwise fashion:
2593 // <0b00, 0b01> + <0b10, 0b11> ->
2594 // 0b0100 + 0b1110 -> 0b01001110
2595 // <0b10, 0b11, 0b00, 0b01>
2596 // We must therefore swap the operands to get the correct result.
2597 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op1, Op0);
2600 // Lower VECTOR_SHUFFLE into one of a number of instructions depending on the
2601 // indices in the shuffle.
2602 SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
2603 SelectionDAG &DAG) const {
2604 ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
2605 EVT ResTy = Op->getValueType(0);
2607 if (!ResTy.is128BitVector())
2610 int ResTyNumElts = ResTy.getVectorNumElements();
2611 SmallVector<int, 16> Indices;
2613 for (int i = 0; i < ResTyNumElts; ++i)
2614 Indices.push_back(Node->getMaskElt(i));
2616 SDValue Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG);
2617 if (Result.getNode())
2619 Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG);
2620 if (Result.getNode())
2622 Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG);
2623 if (Result.getNode())
2625 Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG);
2626 if (Result.getNode())
2628 Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG);
2629 if (Result.getNode())
2631 Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG);
2632 if (Result.getNode())
2634 Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG);
2635 if (Result.getNode())
2637 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2640 MachineBasicBlock * MipsSETargetLowering::
2641 emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
2643 // bposge32_pseudo $vr0
2653 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
2655 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2656 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2657 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2658 DebugLoc DL = MI->getDebugLoc();
2659 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2660 MachineFunction::iterator It = std::next(MachineFunction::iterator(BB));
2661 MachineFunction *F = BB->getParent();
2662 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2663 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2664 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
2667 F->insert(It, Sink);
2669 // Transfer the remainder of BB and its successor edges to Sink.
2670 Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
2672 Sink->transferSuccessorsAndUpdatePHIs(BB);
2675 BB->addSuccessor(FBB);
2676 BB->addSuccessor(TBB);
2677 FBB->addSuccessor(Sink);
2678 TBB->addSuccessor(Sink);
2680 // Insert the real bposge32 instruction to $BB.
2681 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
2684 unsigned VR2 = RegInfo.createVirtualRegister(RC);
2685 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
2686 .addReg(Mips::ZERO).addImm(0);
2687 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2690 unsigned VR1 = RegInfo.createVirtualRegister(RC);
2691 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
2692 .addReg(Mips::ZERO).addImm(1);
2694 // Insert phi function to $Sink.
2695 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2696 MI->getOperand(0).getReg())
2697 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
2699 MI->eraseFromParent(); // The pseudo instruction is gone now.
2703 MachineBasicBlock * MipsSETargetLowering::
2704 emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
2705 unsigned BranchOp) const{
2707 // vany_nonzero $rd, $ws
2718 // $rd = phi($rd1, $fbb, $rd2, $tbb)
2720 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2721 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2722 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2723 DebugLoc DL = MI->getDebugLoc();
2724 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2725 MachineFunction::iterator It = std::next(MachineFunction::iterator(BB));
2726 MachineFunction *F = BB->getParent();
2727 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2728 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2729 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
2732 F->insert(It, Sink);
2734 // Transfer the remainder of BB and its successor edges to Sink.
2735 Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
2737 Sink->transferSuccessorsAndUpdatePHIs(BB);
2740 BB->addSuccessor(FBB);
2741 BB->addSuccessor(TBB);
2742 FBB->addSuccessor(Sink);
2743 TBB->addSuccessor(Sink);
2745 // Insert the real bnz.b instruction to $BB.
2746 BuildMI(BB, DL, TII->get(BranchOp))
2747 .addReg(MI->getOperand(1).getReg())
2751 unsigned RD1 = RegInfo.createVirtualRegister(RC);
2752 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
2753 .addReg(Mips::ZERO).addImm(0);
2754 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2757 unsigned RD2 = RegInfo.createVirtualRegister(RC);
2758 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
2759 .addReg(Mips::ZERO).addImm(1);
2761 // Insert phi function to $Sink.
2762 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2763 MI->getOperand(0).getReg())
2764 .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
2766 MI->eraseFromParent(); // The pseudo instruction is gone now.
2770 // Emit the COPY_FW pseudo instruction.
2772 // copy_fw_pseudo $fd, $ws, n
2774 // copy_u_w $rt, $ws, $n
2777 // When n is zero, the equivalent operation can be performed with (potentially)
2778 // zero instructions due to register overlaps. This optimization is never valid
2779 // for lane 1 because it would require FR=0 mode which isn't supported by MSA.
2780 MachineBasicBlock * MipsSETargetLowering::
2781 emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{
2782 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2783 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2784 DebugLoc DL = MI->getDebugLoc();
2785 unsigned Fd = MI->getOperand(0).getReg();
2786 unsigned Ws = MI->getOperand(1).getReg();
2787 unsigned Lane = MI->getOperand(2).getImm();
2790 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_lo);
2792 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2794 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
2795 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
2798 MI->eraseFromParent(); // The pseudo instruction is gone now.
2802 // Emit the COPY_FD pseudo instruction.
2804 // copy_fd_pseudo $fd, $ws, n
2806 // splati.d $wt, $ws, $n
2807 // copy $fd, $wt:sub_64
2809 // When n is zero, the equivalent operation can be performed with (potentially)
2810 // zero instructions due to register overlaps. This optimization is always
2811 // valid because FR=1 mode which is the only supported mode in MSA.
2812 MachineBasicBlock * MipsSETargetLowering::
2813 emitCOPY_FD(MachineInstr *MI, MachineBasicBlock *BB) const{
2814 assert(Subtarget->isFP64bit());
2816 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2817 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2818 unsigned Fd = MI->getOperand(0).getReg();
2819 unsigned Ws = MI->getOperand(1).getReg();
2820 unsigned Lane = MI->getOperand(2).getImm() * 2;
2821 DebugLoc DL = MI->getDebugLoc();
2824 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
2826 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2828 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
2829 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
2832 MI->eraseFromParent(); // The pseudo instruction is gone now.
2836 // Emit the INSERT_FW pseudo instruction.
2838 // insert_fw_pseudo $wd, $wd_in, $n, $fs
2840 // subreg_to_reg $wt:sub_lo, $fs
2841 // insve_w $wd[$n], $wd_in, $wt[0]
2843 MipsSETargetLowering::emitINSERT_FW(MachineInstr *MI,
2844 MachineBasicBlock *BB) const {
2845 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2846 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2847 DebugLoc DL = MI->getDebugLoc();
2848 unsigned Wd = MI->getOperand(0).getReg();
2849 unsigned Wd_in = MI->getOperand(1).getReg();
2850 unsigned Lane = MI->getOperand(2).getImm();
2851 unsigned Fs = MI->getOperand(3).getReg();
2852 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2854 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
2857 .addImm(Mips::sub_lo);
2858 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
2864 MI->eraseFromParent(); // The pseudo instruction is gone now.
2868 // Emit the INSERT_FD pseudo instruction.
2870 // insert_fd_pseudo $wd, $fs, n
2872 // subreg_to_reg $wt:sub_64, $fs
2873 // insve_d $wd[$n], $wd_in, $wt[0]
2875 MipsSETargetLowering::emitINSERT_FD(MachineInstr *MI,
2876 MachineBasicBlock *BB) const {
2877 assert(Subtarget->isFP64bit());
2879 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2880 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2881 DebugLoc DL = MI->getDebugLoc();
2882 unsigned Wd = MI->getOperand(0).getReg();
2883 unsigned Wd_in = MI->getOperand(1).getReg();
2884 unsigned Lane = MI->getOperand(2).getImm();
2885 unsigned Fs = MI->getOperand(3).getReg();
2886 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2888 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
2891 .addImm(Mips::sub_64);
2892 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
2898 MI->eraseFromParent(); // The pseudo instruction is gone now.
2902 // Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction.
2905 // (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $rs)
2907 // (SLL $lanetmp1, $lane, <log2size)
2908 // (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
2909 // (INSERT_[BHWD], $wdtmp2, $wdtmp1, 0, $rs)
2910 // (NEG $lanetmp2, $lanetmp1)
2911 // (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2)
2913 // For floating point:
2914 // (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $fs)
2916 // (SUBREG_TO_REG $wt, $fs, <subreg>)
2917 // (SLL $lanetmp1, $lane, <log2size)
2918 // (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
2919 // (INSVE_[WD], $wdtmp2, 0, $wdtmp1, 0)
2920 // (NEG $lanetmp2, $lanetmp1)
2921 // (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2)
2923 MipsSETargetLowering::emitINSERT_DF_VIDX(MachineInstr *MI,
2924 MachineBasicBlock *BB,
2925 unsigned EltSizeInBytes,
2927 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2928 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2929 DebugLoc DL = MI->getDebugLoc();
2930 unsigned Wd = MI->getOperand(0).getReg();
2931 unsigned SrcVecReg = MI->getOperand(1).getReg();
2932 unsigned LaneReg = MI->getOperand(2).getReg();
2933 unsigned SrcValReg = MI->getOperand(3).getReg();
2935 const TargetRegisterClass *VecRC = nullptr;
2936 const TargetRegisterClass *GPRRC = isGP64bit() ? &Mips::GPR64RegClass
2937 : &Mips::GPR32RegClass;
2938 unsigned EltLog2Size;
2939 unsigned InsertOp = 0;
2940 unsigned InsveOp = 0;
2941 switch (EltSizeInBytes) {
2943 llvm_unreachable("Unexpected size");
2946 InsertOp = Mips::INSERT_B;
2947 InsveOp = Mips::INSVE_B;
2948 VecRC = &Mips::MSA128BRegClass;
2952 InsertOp = Mips::INSERT_H;
2953 InsveOp = Mips::INSVE_H;
2954 VecRC = &Mips::MSA128HRegClass;
2958 InsertOp = Mips::INSERT_W;
2959 InsveOp = Mips::INSVE_W;
2960 VecRC = &Mips::MSA128WRegClass;
2964 InsertOp = Mips::INSERT_D;
2965 InsveOp = Mips::INSVE_D;
2966 VecRC = &Mips::MSA128DRegClass;
2971 unsigned Wt = RegInfo.createVirtualRegister(VecRC);
2972 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
2975 .addImm(EltSizeInBytes == 8 ? Mips::sub_64 : Mips::sub_lo);
2979 // Convert the lane index into a byte index
2980 if (EltSizeInBytes != 1) {
2981 unsigned LaneTmp1 = RegInfo.createVirtualRegister(GPRRC);
2982 BuildMI(*BB, MI, DL, TII->get(Mips::SLL), LaneTmp1)
2984 .addImm(EltLog2Size);
2988 // Rotate bytes around so that the desired lane is element zero
2989 unsigned WdTmp1 = RegInfo.createVirtualRegister(VecRC);
2990 BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), WdTmp1)
2995 unsigned WdTmp2 = RegInfo.createVirtualRegister(VecRC);
2997 // Use insve.df to insert to element zero
2998 BuildMI(*BB, MI, DL, TII->get(InsveOp), WdTmp2)
3004 // Use insert.df to insert to element zero
3005 BuildMI(*BB, MI, DL, TII->get(InsertOp), WdTmp2)
3011 // Rotate elements the rest of the way for a full rotation.
3012 // sld.df inteprets $rt modulo the number of columns so we only need to negate
3013 // the lane index to do this.
3014 unsigned LaneTmp2 = RegInfo.createVirtualRegister(GPRRC);
3015 BuildMI(*BB, MI, DL, TII->get(Mips::SUB), LaneTmp2)
3018 BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), Wd)
3023 MI->eraseFromParent(); // The pseudo instruction is gone now.
3027 // Emit the FILL_FW pseudo instruction.
3029 // fill_fw_pseudo $wd, $fs
3031 // implicit_def $wt1
3032 // insert_subreg $wt2:subreg_lo, $wt1, $fs
3033 // splati.w $wd, $wt2[0]
3035 MipsSETargetLowering::emitFILL_FW(MachineInstr *MI,
3036 MachineBasicBlock *BB) const {
3037 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3038 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3039 DebugLoc DL = MI->getDebugLoc();
3040 unsigned Wd = MI->getOperand(0).getReg();
3041 unsigned Fs = MI->getOperand(1).getReg();
3042 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3043 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3045 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3046 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3049 .addImm(Mips::sub_lo);
3050 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0);
3052 MI->eraseFromParent(); // The pseudo instruction is gone now.
3056 // Emit the FILL_FD pseudo instruction.
3058 // fill_fd_pseudo $wd, $fs
3060 // implicit_def $wt1
3061 // insert_subreg $wt2:subreg_64, $wt1, $fs
3062 // splati.d $wd, $wt2[0]
3064 MipsSETargetLowering::emitFILL_FD(MachineInstr *MI,
3065 MachineBasicBlock *BB) const {
3066 assert(Subtarget->isFP64bit());
3068 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3069 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3070 DebugLoc DL = MI->getDebugLoc();
3071 unsigned Wd = MI->getOperand(0).getReg();
3072 unsigned Fs = MI->getOperand(1).getReg();
3073 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3074 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3076 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3077 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3080 .addImm(Mips::sub_64);
3081 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0);
3083 MI->eraseFromParent(); // The pseudo instruction is gone now.
3087 // Emit the FEXP2_W_1 pseudo instructions.
3089 // fexp2_w_1_pseudo $wd, $wt
3092 // fexp2.w $wd, $ws, $wt
3094 MipsSETargetLowering::emitFEXP2_W_1(MachineInstr *MI,
3095 MachineBasicBlock *BB) const {
3096 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3097 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3098 const TargetRegisterClass *RC = &Mips::MSA128WRegClass;
3099 unsigned Ws1 = RegInfo.createVirtualRegister(RC);
3100 unsigned Ws2 = RegInfo.createVirtualRegister(RC);
3101 DebugLoc DL = MI->getDebugLoc();
3103 // Splat 1.0 into a vector
3104 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1);
3105 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1);
3107 // Emit 1.0 * fexp2(Wt)
3108 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI->getOperand(0).getReg())
3110 .addReg(MI->getOperand(1).getReg());
3112 MI->eraseFromParent(); // The pseudo instruction is gone now.
3116 // Emit the FEXP2_D_1 pseudo instructions.
3118 // fexp2_d_1_pseudo $wd, $wt
3121 // fexp2.d $wd, $ws, $wt
3123 MipsSETargetLowering::emitFEXP2_D_1(MachineInstr *MI,
3124 MachineBasicBlock *BB) const {
3125 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3126 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3127 const TargetRegisterClass *RC = &Mips::MSA128DRegClass;
3128 unsigned Ws1 = RegInfo.createVirtualRegister(RC);
3129 unsigned Ws2 = RegInfo.createVirtualRegister(RC);
3130 DebugLoc DL = MI->getDebugLoc();
3132 // Splat 1.0 into a vector
3133 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1);
3134 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1);
3136 // Emit 1.0 * fexp2(Wt)
3137 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI->getOperand(0).getReg())
3139 .addReg(MI->getOperand(1).getReg());
3141 MI->eraseFromParent(); // The pseudo instruction is gone now.