1 //===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsTargetLowering specialized for mips32/64.
12 //===----------------------------------------------------------------------===//
13 #include "MipsSEISelLowering.h"
14 #include "MipsRegisterInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/IR/Intrinsics.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Target/TargetInstrInfo.h"
25 EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
26 cl::desc("MIPS: Enable tail calls."), cl::init(false));
28 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
29 cl::desc("Expand double precision loads and "
30 "stores to their single precision "
33 MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
34 : MipsTargetLowering(TM) {
35 // Set up the register classes
37 clearRegisterClasses();
39 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
42 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
44 if (Subtarget->hasDSP()) {
45 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
47 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
48 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
50 // Expand all builtin opcodes.
51 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
52 setOperationAction(Opc, VecTys[i], Expand);
54 setOperationAction(ISD::ADD, VecTys[i], Legal);
55 setOperationAction(ISD::SUB, VecTys[i], Legal);
56 setOperationAction(ISD::LOAD, VecTys[i], Legal);
57 setOperationAction(ISD::STORE, VecTys[i], Legal);
58 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
61 // Expand all truncating stores and extending loads.
62 unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
63 unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
65 for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
66 for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
67 setTruncStoreAction((MVT::SimpleValueType)VT0,
68 (MVT::SimpleValueType)VT1, Expand);
70 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
71 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
72 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
75 setTargetDAGCombine(ISD::SHL);
76 setTargetDAGCombine(ISD::SRA);
77 setTargetDAGCombine(ISD::SRL);
78 setTargetDAGCombine(ISD::SETCC);
79 setTargetDAGCombine(ISD::VSELECT);
82 if (Subtarget->hasDSPR2())
83 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
85 if (Subtarget->hasMSA()) {
86 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
87 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
88 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
89 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
90 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
91 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
92 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
95 if (!Subtarget->mipsSEUsesSoftFloat()) {
96 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
98 // When dealing with single precision only, use libcalls
99 if (!Subtarget->isSingleFloat()) {
100 if (Subtarget->isFP64bit())
101 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
103 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
107 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
108 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
109 setOperationAction(ISD::MULHS, MVT::i32, Custom);
110 setOperationAction(ISD::MULHU, MVT::i32, Custom);
113 setOperationAction(ISD::MULHS, MVT::i64, Custom);
114 setOperationAction(ISD::MULHU, MVT::i64, Custom);
115 setOperationAction(ISD::MUL, MVT::i64, Custom);
118 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
119 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
121 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
122 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
123 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
124 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
125 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
126 setOperationAction(ISD::LOAD, MVT::i32, Custom);
127 setOperationAction(ISD::STORE, MVT::i32, Custom);
129 setTargetDAGCombine(ISD::ADDE);
130 setTargetDAGCombine(ISD::SUBE);
131 setTargetDAGCombine(ISD::MUL);
133 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
134 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
135 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
138 setOperationAction(ISD::LOAD, MVT::f64, Custom);
139 setOperationAction(ISD::STORE, MVT::f64, Custom);
142 computeRegisterProperties();
145 const MipsTargetLowering *
146 llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
147 return new MipsSETargetLowering(TM);
150 // Enable MSA support for the given integer type and Register class.
151 void MipsSETargetLowering::
152 addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
153 addRegisterClass(Ty, RC);
155 // Expand all builtin opcodes.
156 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
157 setOperationAction(Opc, Ty, Expand);
159 setOperationAction(ISD::BITCAST, Ty, Legal);
160 setOperationAction(ISD::LOAD, Ty, Legal);
161 setOperationAction(ISD::STORE, Ty, Legal);
162 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
164 setOperationAction(ISD::ADD, Ty, Legal);
165 setOperationAction(ISD::AND, Ty, Legal);
166 setOperationAction(ISD::CTLZ, Ty, Legal);
167 setOperationAction(ISD::MUL, Ty, Legal);
168 setOperationAction(ISD::OR, Ty, Legal);
169 setOperationAction(ISD::SDIV, Ty, Legal);
170 setOperationAction(ISD::SHL, Ty, Legal);
171 setOperationAction(ISD::SRA, Ty, Legal);
172 setOperationAction(ISD::SRL, Ty, Legal);
173 setOperationAction(ISD::SUB, Ty, Legal);
174 setOperationAction(ISD::UDIV, Ty, Legal);
175 setOperationAction(ISD::XOR, Ty, Legal);
178 // Enable MSA support for the given floating-point type and Register class.
179 void MipsSETargetLowering::
180 addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
181 addRegisterClass(Ty, RC);
183 // Expand all builtin opcodes.
184 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
185 setOperationAction(Opc, Ty, Expand);
187 setOperationAction(ISD::LOAD, Ty, Legal);
188 setOperationAction(ISD::STORE, Ty, Legal);
189 setOperationAction(ISD::BITCAST, Ty, Legal);
191 if (Ty != MVT::v8f16) {
192 setOperationAction(ISD::FADD, Ty, Legal);
193 setOperationAction(ISD::FDIV, Ty, Legal);
194 setOperationAction(ISD::FLOG2, Ty, Legal);
195 setOperationAction(ISD::FMUL, Ty, Legal);
196 setOperationAction(ISD::FRINT, Ty, Legal);
197 setOperationAction(ISD::FSQRT, Ty, Legal);
198 setOperationAction(ISD::FSUB, Ty, Legal);
203 MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
204 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
217 SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
218 SelectionDAG &DAG) const {
219 switch(Op.getOpcode()) {
220 case ISD::LOAD: return lowerLOAD(Op, DAG);
221 case ISD::STORE: return lowerSTORE(Op, DAG);
222 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
223 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
224 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
225 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
226 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
227 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
228 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
230 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
231 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
232 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
233 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
236 return MipsTargetLowering::LowerOperation(Op, DAG);
240 // Transforms a subgraph in CurDAG if the following pattern is found:
241 // (addc multLo, Lo0), (adde multHi, Hi0),
243 // multHi/Lo: product of multiplication
244 // Lo0: initial value of Lo register
245 // Hi0: initial value of Hi register
246 // Return true if pattern matching was successful.
247 static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
248 // ADDENode's second operand must be a flag output of an ADDC node in order
249 // for the matching to be successful.
250 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
252 if (ADDCNode->getOpcode() != ISD::ADDC)
255 SDValue MultHi = ADDENode->getOperand(0);
256 SDValue MultLo = ADDCNode->getOperand(0);
257 SDNode *MultNode = MultHi.getNode();
258 unsigned MultOpc = MultHi.getOpcode();
260 // MultHi and MultLo must be generated by the same node,
261 if (MultLo.getNode() != MultNode)
264 // and it must be a multiplication.
265 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
268 // MultLo amd MultHi must be the first and second output of MultNode
270 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
273 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
274 // of the values of MultNode, in which case MultNode will be removed in later
276 // If there exist users other than ADDENode or ADDCNode, this function returns
277 // here, which will result in MultNode being mapped to a single MULT
278 // instruction node rather than a pair of MULT and MADD instructions being
280 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
285 // Initialize accumulator.
286 SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
287 ADDCNode->getOperand(1),
288 ADDENode->getOperand(1));
290 // create MipsMAdd(u) node
291 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
293 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
294 MultNode->getOperand(0),// Factor 0
295 MultNode->getOperand(1),// Factor 1
298 // replace uses of adde and addc here
299 if (!SDValue(ADDCNode, 0).use_empty()) {
300 SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
301 SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
303 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
305 if (!SDValue(ADDENode, 0).use_empty()) {
306 SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
307 SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
309 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
316 // Transforms a subgraph in CurDAG if the following pattern is found:
317 // (addc Lo0, multLo), (sube Hi0, multHi),
319 // multHi/Lo: product of multiplication
320 // Lo0: initial value of Lo register
321 // Hi0: initial value of Hi register
322 // Return true if pattern matching was successful.
323 static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
324 // SUBENode's second operand must be a flag output of an SUBC node in order
325 // for the matching to be successful.
326 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
328 if (SUBCNode->getOpcode() != ISD::SUBC)
331 SDValue MultHi = SUBENode->getOperand(1);
332 SDValue MultLo = SUBCNode->getOperand(1);
333 SDNode *MultNode = MultHi.getNode();
334 unsigned MultOpc = MultHi.getOpcode();
336 // MultHi and MultLo must be generated by the same node,
337 if (MultLo.getNode() != MultNode)
340 // and it must be a multiplication.
341 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
344 // MultLo amd MultHi must be the first and second output of MultNode
346 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
349 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
350 // of the values of MultNode, in which case MultNode will be removed in later
352 // If there exist users other than SUBENode or SUBCNode, this function returns
353 // here, which will result in MultNode being mapped to a single MULT
354 // instruction node rather than a pair of MULT and MSUB instructions being
356 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
361 // Initialize accumulator.
362 SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
363 SUBCNode->getOperand(0),
364 SUBENode->getOperand(0));
366 // create MipsSub(u) node
367 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
369 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
370 MultNode->getOperand(0),// Factor 0
371 MultNode->getOperand(1),// Factor 1
374 // replace uses of sube and subc here
375 if (!SDValue(SUBCNode, 0).use_empty()) {
376 SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
377 SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
379 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
381 if (!SDValue(SUBENode, 0).use_empty()) {
382 SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
383 SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
385 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
391 static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
392 TargetLowering::DAGCombinerInfo &DCI,
393 const MipsSubtarget *Subtarget) {
394 if (DCI.isBeforeLegalize())
397 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
399 return SDValue(N, 0);
404 static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
405 TargetLowering::DAGCombinerInfo &DCI,
406 const MipsSubtarget *Subtarget) {
407 if (DCI.isBeforeLegalize())
410 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
412 return SDValue(N, 0);
417 static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
418 EVT ShiftTy, SelectionDAG &DAG) {
419 // Clear the upper (64 - VT.sizeInBits) bits.
420 C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
424 return DAG.getConstant(0, VT);
430 // If c is power of 2, return (shl x, log2(c)).
431 if (isPowerOf2_64(C))
432 return DAG.getNode(ISD::SHL, DL, VT, X,
433 DAG.getConstant(Log2_64(C), ShiftTy));
435 unsigned Log2Ceil = Log2_64_Ceil(C);
436 uint64_t Floor = 1LL << Log2_64(C);
437 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
439 // If |c - floor_c| <= |c - ceil_c|,
440 // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
441 // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
442 if (C - Floor <= Ceil - C) {
443 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
444 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
445 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
448 // If |c - floor_c| > |c - ceil_c|,
449 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
450 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
451 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
452 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
455 static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
456 const TargetLowering::DAGCombinerInfo &DCI,
457 const MipsSETargetLowering *TL) {
458 EVT VT = N->getValueType(0);
460 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
462 return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N),
463 VT, TL->getScalarShiftAmountTy(VT), DAG);
465 return SDValue(N, 0);
468 static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
470 const MipsSubtarget *Subtarget) {
471 // See if this is a vector splat immediate node.
472 APInt SplatValue, SplatUndef;
473 unsigned SplatBitSize;
475 unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
476 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
479 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
480 EltSize, !Subtarget->isLittle()) ||
481 (SplatBitSize != EltSize) ||
482 (SplatValue.getZExtValue() >= EltSize))
485 return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
486 DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
489 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
490 TargetLowering::DAGCombinerInfo &DCI,
491 const MipsSubtarget *Subtarget) {
492 EVT Ty = N->getValueType(0);
494 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
497 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
500 static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
501 TargetLowering::DAGCombinerInfo &DCI,
502 const MipsSubtarget *Subtarget) {
503 EVT Ty = N->getValueType(0);
505 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
508 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
512 static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
513 TargetLowering::DAGCombinerInfo &DCI,
514 const MipsSubtarget *Subtarget) {
515 EVT Ty = N->getValueType(0);
517 if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
520 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
523 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
524 bool IsV216 = (Ty == MVT::v2i16);
528 case ISD::SETNE: return true;
532 case ISD::SETGE: return IsV216;
536 case ISD::SETUGE: return !IsV216;
537 default: return false;
541 static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
542 EVT Ty = N->getValueType(0);
544 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
547 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
550 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
551 N->getOperand(1), N->getOperand(2));
554 static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
555 EVT Ty = N->getValueType(0);
557 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
560 SDValue SetCC = N->getOperand(0);
562 if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
565 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
566 SetCC.getOperand(0), SetCC.getOperand(1), N->getOperand(1),
567 N->getOperand(2), SetCC.getOperand(2));
571 MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
572 SelectionDAG &DAG = DCI.DAG;
575 switch (N->getOpcode()) {
577 return performADDECombine(N, DAG, DCI, Subtarget);
579 return performSUBECombine(N, DAG, DCI, Subtarget);
581 return performMULCombine(N, DAG, DCI, this);
583 return performSHLCombine(N, DAG, DCI, Subtarget);
585 return performSRACombine(N, DAG, DCI, Subtarget);
587 return performSRLCombine(N, DAG, DCI, Subtarget);
589 return performVSELECTCombine(N, DAG);
591 Val = performSETCCCombine(N, DAG);
599 return MipsTargetLowering::PerformDAGCombine(N, DCI);
603 MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
604 MachineBasicBlock *BB) const {
605 switch (MI->getOpcode()) {
607 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
608 case Mips::BPOSGE32_PSEUDO:
609 return emitBPOSGE32(MI, BB);
610 case Mips::SNZ_B_PSEUDO:
611 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
612 case Mips::SNZ_H_PSEUDO:
613 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
614 case Mips::SNZ_W_PSEUDO:
615 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
616 case Mips::SNZ_D_PSEUDO:
617 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
618 case Mips::SNZ_V_PSEUDO:
619 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
620 case Mips::SZ_B_PSEUDO:
621 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
622 case Mips::SZ_H_PSEUDO:
623 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
624 case Mips::SZ_W_PSEUDO:
625 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
626 case Mips::SZ_D_PSEUDO:
627 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
628 case Mips::SZ_V_PSEUDO:
629 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
633 bool MipsSETargetLowering::
634 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
635 unsigned NextStackOffset,
636 const MipsFunctionInfo& FI) const {
637 if (!EnableMipsTailCalls)
640 // Return false if either the callee or caller has a byval argument.
641 if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
644 // Return true if the callee's argument area is no larger than the
646 return NextStackOffset <= FI.getIncomingArgSize();
649 void MipsSETargetLowering::
650 getOpndList(SmallVectorImpl<SDValue> &Ops,
651 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
652 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
653 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
654 // T9 should contain the address of the callee function if
655 // -reloction-model=pic or it is an indirect call.
656 if (IsPICCall || !GlobalOrExternal) {
657 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
658 RegsToPass.push_front(std::make_pair(T9Reg, Callee));
660 Ops.push_back(Callee);
662 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
663 InternalLinkage, CLI, Callee, Chain);
666 SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
667 LoadSDNode &Nd = *cast<LoadSDNode>(Op);
669 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
670 return MipsTargetLowering::lowerLOAD(Op, DAG);
672 // Replace a double precision load with two i32 loads and a buildpair64.
674 SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
675 EVT PtrVT = Ptr.getValueType();
677 // i32 load from lower address.
678 SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
679 MachinePointerInfo(), Nd.isVolatile(),
680 Nd.isNonTemporal(), Nd.isInvariant(),
683 // i32 load from higher address.
684 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
685 SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
686 MachinePointerInfo(), Nd.isVolatile(),
687 Nd.isNonTemporal(), Nd.isInvariant(),
688 std::min(Nd.getAlignment(), 4U));
690 if (!Subtarget->isLittle())
693 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
694 SDValue Ops[2] = {BP, Hi.getValue(1)};
695 return DAG.getMergeValues(Ops, 2, DL);
698 SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
699 StoreSDNode &Nd = *cast<StoreSDNode>(Op);
701 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
702 return MipsTargetLowering::lowerSTORE(Op, DAG);
704 // Replace a double precision store with two extractelement64s and i32 stores.
706 SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
707 EVT PtrVT = Ptr.getValueType();
708 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
709 Val, DAG.getConstant(0, MVT::i32));
710 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
711 Val, DAG.getConstant(1, MVT::i32));
713 if (!Subtarget->isLittle())
716 // i32 store to lower address.
717 Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
718 Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
721 // i32 store to higher address.
722 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
723 return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
724 Nd.isVolatile(), Nd.isNonTemporal(),
725 std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo());
728 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
729 bool HasLo, bool HasHi,
730 SelectionDAG &DAG) const {
731 EVT Ty = Op.getOperand(0).getValueType();
733 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
734 Op.getOperand(0), Op.getOperand(1));
738 Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
739 DAG.getConstant(Mips::sub_lo, MVT::i32));
741 Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
742 DAG.getConstant(Mips::sub_hi, MVT::i32));
744 if (!HasLo || !HasHi)
745 return HasLo ? Lo : Hi;
747 SDValue Vals[] = { Lo, Hi };
748 return DAG.getMergeValues(Vals, 2, DL);
752 static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
753 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
754 DAG.getConstant(0, MVT::i32));
755 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
756 DAG.getConstant(1, MVT::i32));
757 return DAG.getNode(MipsISD::InsertLOHI, DL, MVT::Untyped, InLo, InHi);
760 static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
761 SDValue Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
762 DAG.getConstant(Mips::sub_lo, MVT::i32));
763 SDValue Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
764 DAG.getConstant(Mips::sub_hi, MVT::i32));
765 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
768 // This function expands mips intrinsic nodes which have 64-bit input operands
771 // out64 = intrinsic-node in64
773 // lo = copy (extract-element (in64, 0))
774 // hi = copy (extract-element (in64, 1))
775 // mips-specific-node
778 // out64 = merge-values (v0, v1)
780 static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
782 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
783 SmallVector<SDValue, 3> Ops;
786 // See if Op has a chain input.
788 Ops.push_back(Op->getOperand(OpNo++));
790 // The next operand is the intrinsic opcode.
791 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
793 // See if the next operand has type i64.
794 SDValue Opnd = Op->getOperand(++OpNo), In64;
796 if (Opnd.getValueType() == MVT::i64)
797 In64 = initAccumulator(Opnd, DL, DAG);
801 // Push the remaining operands.
802 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
803 Ops.push_back(Op->getOperand(OpNo));
805 // Add In64 to the end of the list.
810 SmallVector<EVT, 2> ResTys;
812 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
814 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
817 SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size());
818 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
823 assert(Val->getValueType(1) == MVT::Other);
824 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
825 return DAG.getMergeValues(Vals, 2, DL);
828 static SDValue lowerMSABinaryIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
830 SDValue LHS = Op->getOperand(1);
831 SDValue RHS = Op->getOperand(2);
832 EVT ResTy = Op->getValueType(0);
834 SDValue Result = DAG.getNode(Opc, DL, ResTy, LHS, RHS);
839 static SDValue lowerMSABranchIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
841 SDValue Value = Op->getOperand(1);
842 EVT ResTy = Op->getValueType(0);
844 SDValue Result = DAG.getNode(Opc, DL, ResTy, Value);
849 static SDValue lowerMSAUnaryIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
851 SDValue Value = Op->getOperand(1);
852 EVT ResTy = Op->getValueType(0);
854 SDValue Result = DAG.getNode(Opc, DL, ResTy, Value);
859 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
860 SelectionDAG &DAG) const {
861 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
864 case Intrinsic::mips_shilo:
865 return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
866 case Intrinsic::mips_dpau_h_qbl:
867 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
868 case Intrinsic::mips_dpau_h_qbr:
869 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
870 case Intrinsic::mips_dpsu_h_qbl:
871 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
872 case Intrinsic::mips_dpsu_h_qbr:
873 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
874 case Intrinsic::mips_dpa_w_ph:
875 return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
876 case Intrinsic::mips_dps_w_ph:
877 return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
878 case Intrinsic::mips_dpax_w_ph:
879 return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
880 case Intrinsic::mips_dpsx_w_ph:
881 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
882 case Intrinsic::mips_mulsa_w_ph:
883 return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
884 case Intrinsic::mips_mult:
885 return lowerDSPIntr(Op, DAG, MipsISD::Mult);
886 case Intrinsic::mips_multu:
887 return lowerDSPIntr(Op, DAG, MipsISD::Multu);
888 case Intrinsic::mips_madd:
889 return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
890 case Intrinsic::mips_maddu:
891 return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
892 case Intrinsic::mips_msub:
893 return lowerDSPIntr(Op, DAG, MipsISD::MSub);
894 case Intrinsic::mips_msubu:
895 return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
896 case Intrinsic::mips_addv_b:
897 case Intrinsic::mips_addv_h:
898 case Intrinsic::mips_addv_w:
899 case Intrinsic::mips_addv_d:
900 return lowerMSABinaryIntr(Op, DAG, ISD::ADD);
901 case Intrinsic::mips_and_v:
902 return lowerMSABinaryIntr(Op, DAG, ISD::AND);
903 case Intrinsic::mips_bnz_b:
904 case Intrinsic::mips_bnz_h:
905 case Intrinsic::mips_bnz_w:
906 case Intrinsic::mips_bnz_d:
907 return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_NONZERO);
908 case Intrinsic::mips_bnz_v:
909 return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_NONZERO);
910 case Intrinsic::mips_bz_b:
911 case Intrinsic::mips_bz_h:
912 case Intrinsic::mips_bz_w:
913 case Intrinsic::mips_bz_d:
914 return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_ZERO);
915 case Intrinsic::mips_bz_v:
916 return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_ZERO);
917 case Intrinsic::mips_div_s_b:
918 case Intrinsic::mips_div_s_h:
919 case Intrinsic::mips_div_s_w:
920 case Intrinsic::mips_div_s_d:
921 return lowerMSABinaryIntr(Op, DAG, ISD::SDIV);
922 case Intrinsic::mips_div_u_b:
923 case Intrinsic::mips_div_u_h:
924 case Intrinsic::mips_div_u_w:
925 case Intrinsic::mips_div_u_d:
926 return lowerMSABinaryIntr(Op, DAG, ISD::UDIV);
927 case Intrinsic::mips_fadd_w:
928 case Intrinsic::mips_fadd_d:
929 return lowerMSABinaryIntr(Op, DAG, ISD::FADD);
930 case Intrinsic::mips_fdiv_w:
931 case Intrinsic::mips_fdiv_d:
932 return lowerMSABinaryIntr(Op, DAG, ISD::FDIV);
933 case Intrinsic::mips_fill_b:
934 case Intrinsic::mips_fill_h:
935 case Intrinsic::mips_fill_w:
936 return lowerMSAUnaryIntr(Op, DAG, MipsISD::VSPLAT);
937 case Intrinsic::mips_flog2_w:
938 case Intrinsic::mips_flog2_d:
939 return lowerMSAUnaryIntr(Op, DAG, ISD::FLOG2);
940 case Intrinsic::mips_fmul_w:
941 case Intrinsic::mips_fmul_d:
942 return lowerMSABinaryIntr(Op, DAG, ISD::FMUL);
943 case Intrinsic::mips_frint_w:
944 case Intrinsic::mips_frint_d:
945 return lowerMSAUnaryIntr(Op, DAG, ISD::FRINT);
946 case Intrinsic::mips_fsqrt_w:
947 case Intrinsic::mips_fsqrt_d:
948 return lowerMSAUnaryIntr(Op, DAG, ISD::FSQRT);
949 case Intrinsic::mips_fsub_w:
950 case Intrinsic::mips_fsub_d:
951 return lowerMSABinaryIntr(Op, DAG, ISD::FSUB);
952 case Intrinsic::mips_ldi_b:
953 case Intrinsic::mips_ldi_h:
954 case Intrinsic::mips_ldi_w:
955 case Intrinsic::mips_ldi_d:
956 return lowerMSAUnaryIntr(Op, DAG, MipsISD::VSPLAT);
957 case Intrinsic::mips_mulv_b:
958 case Intrinsic::mips_mulv_h:
959 case Intrinsic::mips_mulv_w:
960 case Intrinsic::mips_mulv_d:
961 return lowerMSABinaryIntr(Op, DAG, ISD::MUL);
962 case Intrinsic::mips_nlzc_b:
963 case Intrinsic::mips_nlzc_h:
964 case Intrinsic::mips_nlzc_w:
965 case Intrinsic::mips_nlzc_d:
966 return lowerMSAUnaryIntr(Op, DAG, ISD::CTLZ);
967 case Intrinsic::mips_or_v:
968 return lowerMSABinaryIntr(Op, DAG, ISD::OR);
969 case Intrinsic::mips_sll_b:
970 case Intrinsic::mips_sll_h:
971 case Intrinsic::mips_sll_w:
972 case Intrinsic::mips_sll_d:
973 return lowerMSABinaryIntr(Op, DAG, ISD::SHL);
974 case Intrinsic::mips_sra_b:
975 case Intrinsic::mips_sra_h:
976 case Intrinsic::mips_sra_w:
977 case Intrinsic::mips_sra_d:
978 return lowerMSABinaryIntr(Op, DAG, ISD::SRA);
979 case Intrinsic::mips_srl_b:
980 case Intrinsic::mips_srl_h:
981 case Intrinsic::mips_srl_w:
982 case Intrinsic::mips_srl_d:
983 return lowerMSABinaryIntr(Op, DAG, ISD::SRL);
984 case Intrinsic::mips_subv_b:
985 case Intrinsic::mips_subv_h:
986 case Intrinsic::mips_subv_w:
987 case Intrinsic::mips_subv_d:
988 return lowerMSABinaryIntr(Op, DAG, ISD::SUB);
989 case Intrinsic::mips_xor_v:
990 return lowerMSABinaryIntr(Op, DAG, ISD::XOR);
994 static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
996 SDValue ChainIn = Op->getOperand(0);
997 SDValue Address = Op->getOperand(2);
998 SDValue Offset = Op->getOperand(3);
999 EVT ResTy = Op->getValueType(0);
1000 EVT PtrTy = Address->getValueType(0);
1002 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
1004 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
1008 SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
1009 SelectionDAG &DAG) const {
1010 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1014 case Intrinsic::mips_extp:
1015 return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
1016 case Intrinsic::mips_extpdp:
1017 return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
1018 case Intrinsic::mips_extr_w:
1019 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
1020 case Intrinsic::mips_extr_r_w:
1021 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
1022 case Intrinsic::mips_extr_rs_w:
1023 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
1024 case Intrinsic::mips_extr_s_h:
1025 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
1026 case Intrinsic::mips_mthlip:
1027 return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
1028 case Intrinsic::mips_mulsaq_s_w_ph:
1029 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
1030 case Intrinsic::mips_maq_s_w_phl:
1031 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
1032 case Intrinsic::mips_maq_s_w_phr:
1033 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
1034 case Intrinsic::mips_maq_sa_w_phl:
1035 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
1036 case Intrinsic::mips_maq_sa_w_phr:
1037 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
1038 case Intrinsic::mips_dpaq_s_w_ph:
1039 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
1040 case Intrinsic::mips_dpsq_s_w_ph:
1041 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
1042 case Intrinsic::mips_dpaq_sa_l_w:
1043 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
1044 case Intrinsic::mips_dpsq_sa_l_w:
1045 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
1046 case Intrinsic::mips_dpaqx_s_w_ph:
1047 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
1048 case Intrinsic::mips_dpaqx_sa_w_ph:
1049 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
1050 case Intrinsic::mips_dpsqx_s_w_ph:
1051 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
1052 case Intrinsic::mips_dpsqx_sa_w_ph:
1053 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
1054 case Intrinsic::mips_ld_b:
1055 case Intrinsic::mips_ld_h:
1056 case Intrinsic::mips_ld_w:
1057 case Intrinsic::mips_ld_d:
1058 case Intrinsic::mips_ldx_b:
1059 case Intrinsic::mips_ldx_h:
1060 case Intrinsic::mips_ldx_w:
1061 case Intrinsic::mips_ldx_d:
1062 return lowerMSALoadIntr(Op, DAG, Intr);
1066 static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
1068 SDValue ChainIn = Op->getOperand(0);
1069 SDValue Value = Op->getOperand(2);
1070 SDValue Address = Op->getOperand(3);
1071 SDValue Offset = Op->getOperand(4);
1072 EVT PtrTy = Address->getValueType(0);
1074 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
1076 return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
1080 SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
1081 SelectionDAG &DAG) const {
1082 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1086 case Intrinsic::mips_st_b:
1087 case Intrinsic::mips_st_h:
1088 case Intrinsic::mips_st_w:
1089 case Intrinsic::mips_st_d:
1090 case Intrinsic::mips_stx_b:
1091 case Intrinsic::mips_stx_h:
1092 case Intrinsic::mips_stx_w:
1093 case Intrinsic::mips_stx_d:
1094 return lowerMSAStoreIntr(Op, DAG, Intr);
1098 /// \brief Check if the given BuildVectorSDNode is a splat.
1099 /// This method currently relies on DAG nodes being reused when equivalent,
1100 /// so it's possible for this to return false even when isConstantSplat returns
1102 static bool isSplatVector(const BuildVectorSDNode *N) {
1103 unsigned int nOps = N->getNumOperands();
1104 assert(nOps > 1 && "isSplat has 0 or 1 sized build vector");
1106 SDValue Operand0 = N->getOperand(0);
1108 for (unsigned int i = 1; i < nOps; ++i) {
1109 if (N->getOperand(i) != Operand0)
1116 // Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
1119 // Lowers according to the following rules:
1120 // - Vectors of 128-bits may be legal subject to the other rules. Other sizes
1122 // - Non-constant splats are legal and are lowered to MipsISD::VSPLAT.
1123 // - Constant splats with an element size of 32-bits or less are legal and are
1124 // lowered to MipsISD::VSPLAT.
1125 // - Constant splats with an element size of 64-bits but whose value would fit
1126 // within a 10 bit immediate are legal and are lowered to MipsISD::VSPLATD.
1127 // - All other ISD::BUILD_VECTORS are not legal
1128 SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
1129 SelectionDAG &DAG) const {
1130 BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
1131 EVT ResTy = Op->getValueType(0);
1133 APInt SplatValue, SplatUndef;
1134 unsigned SplatBitSize;
1137 if (!Subtarget->hasMSA() || !ResTy.is128BitVector())
1140 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
1142 !Subtarget->isLittle())) {
1145 EVT ConstTy = MVT::i32;
1146 unsigned SplatOp = MipsISD::VSPLAT;
1148 switch (SplatBitSize) {
1152 TmpVecTy = MVT::v2i64;
1154 // i64 is an illegal type on Mips32, but if it the constant fits into a
1155 // signed 10-bit value then we can still handle it using VSPLATD and an
1159 else if (isInt<10>(SplatValue.getSExtValue())) {
1160 SplatValue = SplatValue.trunc(32);
1161 SplatOp = MipsISD::VSPLATD;
1166 TmpVecTy = MVT::v4i32;
1169 TmpVecTy = MVT::v8i16;
1170 SplatValue = SplatValue.sext(32);
1173 TmpVecTy = MVT::v16i8;
1174 SplatValue = SplatValue.sext(32);
1178 Result = DAG.getNode(SplatOp, DL, TmpVecTy,
1179 DAG.getConstant(SplatValue, ConstTy));
1180 if (ResTy != Result.getValueType())
1181 Result = DAG.getNode(ISD::BITCAST, DL, ResTy, Result);
1185 else if (isSplatVector(Node))
1186 return DAG.getNode(MipsISD::VSPLAT, DL, ResTy, Op->getOperand(0));
1191 MachineBasicBlock * MipsSETargetLowering::
1192 emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
1194 // bposge32_pseudo $vr0
1204 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
1206 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
1207 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1208 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
1209 DebugLoc DL = MI->getDebugLoc();
1210 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1211 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
1212 MachineFunction *F = BB->getParent();
1213 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
1214 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
1215 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
1218 F->insert(It, Sink);
1220 // Transfer the remainder of BB and its successor edges to Sink.
1221 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
1223 Sink->transferSuccessorsAndUpdatePHIs(BB);
1226 BB->addSuccessor(FBB);
1227 BB->addSuccessor(TBB);
1228 FBB->addSuccessor(Sink);
1229 TBB->addSuccessor(Sink);
1231 // Insert the real bposge32 instruction to $BB.
1232 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
1235 unsigned VR2 = RegInfo.createVirtualRegister(RC);
1236 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
1237 .addReg(Mips::ZERO).addImm(0);
1238 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
1241 unsigned VR1 = RegInfo.createVirtualRegister(RC);
1242 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
1243 .addReg(Mips::ZERO).addImm(1);
1245 // Insert phi function to $Sink.
1246 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
1247 MI->getOperand(0).getReg())
1248 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
1250 MI->eraseFromParent(); // The pseudo instruction is gone now.
1254 MachineBasicBlock * MipsSETargetLowering::
1255 emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
1256 unsigned BranchOp) const{
1258 // vany_nonzero $rd, $ws
1269 // $rd = phi($rd1, $fbb, $rd2, $tbb)
1271 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
1272 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1273 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
1274 DebugLoc DL = MI->getDebugLoc();
1275 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1276 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
1277 MachineFunction *F = BB->getParent();
1278 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
1279 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
1280 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
1283 F->insert(It, Sink);
1285 // Transfer the remainder of BB and its successor edges to Sink.
1286 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
1288 Sink->transferSuccessorsAndUpdatePHIs(BB);
1291 BB->addSuccessor(FBB);
1292 BB->addSuccessor(TBB);
1293 FBB->addSuccessor(Sink);
1294 TBB->addSuccessor(Sink);
1296 // Insert the real bnz.b instruction to $BB.
1297 BuildMI(BB, DL, TII->get(BranchOp))
1298 .addReg(MI->getOperand(1).getReg())
1302 unsigned RD1 = RegInfo.createVirtualRegister(RC);
1303 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
1304 .addReg(Mips::ZERO).addImm(0);
1305 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
1308 unsigned RD2 = RegInfo.createVirtualRegister(RC);
1309 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
1310 .addReg(Mips::ZERO).addImm(1);
1312 // Insert phi function to $Sink.
1313 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
1314 MI->getOperand(0).getReg())
1315 .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
1317 MI->eraseFromParent(); // The pseudo instruction is gone now.