1 //===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsTargetLowering specialized for mips32/64.
12 //===----------------------------------------------------------------------===//
13 #include "MipsSEISelLowering.h"
14 #include "MipsRegisterInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/IR/Intrinsics.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Target/TargetInstrInfo.h"
25 EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
26 cl::desc("MIPS: Enable tail calls."), cl::init(false));
28 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
29 cl::desc("Expand double precision loads and "
30 "stores to their single precision "
33 MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
34 : MipsTargetLowering(TM) {
35 // Set up the register classes
37 clearRegisterClasses();
39 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
42 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
44 if (Subtarget->hasDSP()) {
45 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
47 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
48 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
50 // Expand all builtin opcodes.
51 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
52 setOperationAction(Opc, VecTys[i], Expand);
54 setOperationAction(ISD::ADD, VecTys[i], Legal);
55 setOperationAction(ISD::SUB, VecTys[i], Legal);
56 setOperationAction(ISD::LOAD, VecTys[i], Legal);
57 setOperationAction(ISD::STORE, VecTys[i], Legal);
58 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
61 // Expand all truncating stores and extending loads.
62 unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
63 unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
65 for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
66 for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
67 setTruncStoreAction((MVT::SimpleValueType)VT0,
68 (MVT::SimpleValueType)VT1, Expand);
70 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
71 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
72 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
75 setTargetDAGCombine(ISD::SHL);
76 setTargetDAGCombine(ISD::SRA);
77 setTargetDAGCombine(ISD::SRL);
78 setTargetDAGCombine(ISD::SETCC);
79 setTargetDAGCombine(ISD::VSELECT);
82 if (Subtarget->hasDSPR2())
83 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
85 if (Subtarget->hasMSA()) {
86 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
87 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
88 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
89 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
90 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
91 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
92 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
95 if (!Subtarget->mipsSEUsesSoftFloat()) {
96 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
98 // When dealing with single precision only, use libcalls
99 if (!Subtarget->isSingleFloat()) {
100 if (Subtarget->isFP64bit())
101 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
103 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
107 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
108 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
109 setOperationAction(ISD::MULHS, MVT::i32, Custom);
110 setOperationAction(ISD::MULHU, MVT::i32, Custom);
113 setOperationAction(ISD::MULHS, MVT::i64, Custom);
114 setOperationAction(ISD::MULHU, MVT::i64, Custom);
115 setOperationAction(ISD::MUL, MVT::i64, Custom);
118 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
119 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
121 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
122 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
123 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
124 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
125 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
126 setOperationAction(ISD::LOAD, MVT::i32, Custom);
127 setOperationAction(ISD::STORE, MVT::i32, Custom);
129 setTargetDAGCombine(ISD::ADDE);
130 setTargetDAGCombine(ISD::SUBE);
131 setTargetDAGCombine(ISD::MUL);
133 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
134 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
135 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
138 setOperationAction(ISD::LOAD, MVT::f64, Custom);
139 setOperationAction(ISD::STORE, MVT::f64, Custom);
142 computeRegisterProperties();
145 const MipsTargetLowering *
146 llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
147 return new MipsSETargetLowering(TM);
150 void MipsSETargetLowering::
151 addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
152 addRegisterClass(Ty, RC);
154 // Expand all builtin opcodes.
155 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
156 setOperationAction(Opc, Ty, Expand);
158 setOperationAction(ISD::BITCAST, Ty, Legal);
159 setOperationAction(ISD::LOAD, Ty, Legal);
160 setOperationAction(ISD::STORE, Ty, Legal);
162 setOperationAction(ISD::ADD, Ty, Legal);
163 setOperationAction(ISD::SDIV, Ty, Legal);
164 setOperationAction(ISD::UDIV, Ty, Legal);
167 void MipsSETargetLowering::
168 addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
169 addRegisterClass(Ty, RC);
171 // Expand all builtin opcodes.
172 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
173 setOperationAction(Opc, Ty, Expand);
175 setOperationAction(ISD::LOAD, Ty, Legal);
176 setOperationAction(ISD::STORE, Ty, Legal);
177 setOperationAction(ISD::BITCAST, Ty, Legal);
181 MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
182 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
195 SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
196 SelectionDAG &DAG) const {
197 switch(Op.getOpcode()) {
198 case ISD::LOAD: return lowerLOAD(Op, DAG);
199 case ISD::STORE: return lowerSTORE(Op, DAG);
200 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
201 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
202 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
203 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
204 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
205 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
206 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
208 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
209 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
210 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
213 return MipsTargetLowering::LowerOperation(Op, DAG);
217 // Transforms a subgraph in CurDAG if the following pattern is found:
218 // (addc multLo, Lo0), (adde multHi, Hi0),
220 // multHi/Lo: product of multiplication
221 // Lo0: initial value of Lo register
222 // Hi0: initial value of Hi register
223 // Return true if pattern matching was successful.
224 static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
225 // ADDENode's second operand must be a flag output of an ADDC node in order
226 // for the matching to be successful.
227 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
229 if (ADDCNode->getOpcode() != ISD::ADDC)
232 SDValue MultHi = ADDENode->getOperand(0);
233 SDValue MultLo = ADDCNode->getOperand(0);
234 SDNode *MultNode = MultHi.getNode();
235 unsigned MultOpc = MultHi.getOpcode();
237 // MultHi and MultLo must be generated by the same node,
238 if (MultLo.getNode() != MultNode)
241 // and it must be a multiplication.
242 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
245 // MultLo amd MultHi must be the first and second output of MultNode
247 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
250 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
251 // of the values of MultNode, in which case MultNode will be removed in later
253 // If there exist users other than ADDENode or ADDCNode, this function returns
254 // here, which will result in MultNode being mapped to a single MULT
255 // instruction node rather than a pair of MULT and MADD instructions being
257 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
262 // Initialize accumulator.
263 SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
264 ADDCNode->getOperand(1),
265 ADDENode->getOperand(1));
267 // create MipsMAdd(u) node
268 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
270 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
271 MultNode->getOperand(0),// Factor 0
272 MultNode->getOperand(1),// Factor 1
275 // replace uses of adde and addc here
276 if (!SDValue(ADDCNode, 0).use_empty()) {
277 SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
278 SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
280 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
282 if (!SDValue(ADDENode, 0).use_empty()) {
283 SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
284 SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
286 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
293 // Transforms a subgraph in CurDAG if the following pattern is found:
294 // (addc Lo0, multLo), (sube Hi0, multHi),
296 // multHi/Lo: product of multiplication
297 // Lo0: initial value of Lo register
298 // Hi0: initial value of Hi register
299 // Return true if pattern matching was successful.
300 static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
301 // SUBENode's second operand must be a flag output of an SUBC node in order
302 // for the matching to be successful.
303 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
305 if (SUBCNode->getOpcode() != ISD::SUBC)
308 SDValue MultHi = SUBENode->getOperand(1);
309 SDValue MultLo = SUBCNode->getOperand(1);
310 SDNode *MultNode = MultHi.getNode();
311 unsigned MultOpc = MultHi.getOpcode();
313 // MultHi and MultLo must be generated by the same node,
314 if (MultLo.getNode() != MultNode)
317 // and it must be a multiplication.
318 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
321 // MultLo amd MultHi must be the first and second output of MultNode
323 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
326 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
327 // of the values of MultNode, in which case MultNode will be removed in later
329 // If there exist users other than SUBENode or SUBCNode, this function returns
330 // here, which will result in MultNode being mapped to a single MULT
331 // instruction node rather than a pair of MULT and MSUB instructions being
333 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
338 // Initialize accumulator.
339 SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
340 SUBCNode->getOperand(0),
341 SUBENode->getOperand(0));
343 // create MipsSub(u) node
344 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
346 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
347 MultNode->getOperand(0),// Factor 0
348 MultNode->getOperand(1),// Factor 1
351 // replace uses of sube and subc here
352 if (!SDValue(SUBCNode, 0).use_empty()) {
353 SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
354 SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
356 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
358 if (!SDValue(SUBENode, 0).use_empty()) {
359 SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
360 SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
362 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
368 static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
369 TargetLowering::DAGCombinerInfo &DCI,
370 const MipsSubtarget *Subtarget) {
371 if (DCI.isBeforeLegalize())
374 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
376 return SDValue(N, 0);
381 static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
382 TargetLowering::DAGCombinerInfo &DCI,
383 const MipsSubtarget *Subtarget) {
384 if (DCI.isBeforeLegalize())
387 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
389 return SDValue(N, 0);
394 static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
395 EVT ShiftTy, SelectionDAG &DAG) {
396 // Clear the upper (64 - VT.sizeInBits) bits.
397 C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
401 return DAG.getConstant(0, VT);
407 // If c is power of 2, return (shl x, log2(c)).
408 if (isPowerOf2_64(C))
409 return DAG.getNode(ISD::SHL, DL, VT, X,
410 DAG.getConstant(Log2_64(C), ShiftTy));
412 unsigned Log2Ceil = Log2_64_Ceil(C);
413 uint64_t Floor = 1LL << Log2_64(C);
414 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
416 // If |c - floor_c| <= |c - ceil_c|,
417 // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
418 // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
419 if (C - Floor <= Ceil - C) {
420 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
421 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
422 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
425 // If |c - floor_c| > |c - ceil_c|,
426 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
427 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
428 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
429 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
432 static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
433 const TargetLowering::DAGCombinerInfo &DCI,
434 const MipsSETargetLowering *TL) {
435 EVT VT = N->getValueType(0);
437 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
439 return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N),
440 VT, TL->getScalarShiftAmountTy(VT), DAG);
442 return SDValue(N, 0);
445 static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
447 const MipsSubtarget *Subtarget) {
448 // See if this is a vector splat immediate node.
449 APInt SplatValue, SplatUndef;
450 unsigned SplatBitSize;
452 unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
453 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
456 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
457 EltSize, !Subtarget->isLittle()) ||
458 (SplatBitSize != EltSize) ||
459 (SplatValue.getZExtValue() >= EltSize))
462 return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
463 DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
466 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
467 TargetLowering::DAGCombinerInfo &DCI,
468 const MipsSubtarget *Subtarget) {
469 EVT Ty = N->getValueType(0);
471 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
474 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
477 static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
478 TargetLowering::DAGCombinerInfo &DCI,
479 const MipsSubtarget *Subtarget) {
480 EVT Ty = N->getValueType(0);
482 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
485 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
489 static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
490 TargetLowering::DAGCombinerInfo &DCI,
491 const MipsSubtarget *Subtarget) {
492 EVT Ty = N->getValueType(0);
494 if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
497 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
500 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
501 bool IsV216 = (Ty == MVT::v2i16);
505 case ISD::SETNE: return true;
509 case ISD::SETGE: return IsV216;
513 case ISD::SETUGE: return !IsV216;
514 default: return false;
518 static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
519 EVT Ty = N->getValueType(0);
521 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
524 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
527 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
528 N->getOperand(1), N->getOperand(2));
531 static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
532 EVT Ty = N->getValueType(0);
534 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
537 SDValue SetCC = N->getOperand(0);
539 if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
542 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
543 SetCC.getOperand(0), SetCC.getOperand(1), N->getOperand(1),
544 N->getOperand(2), SetCC.getOperand(2));
548 MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
549 SelectionDAG &DAG = DCI.DAG;
552 switch (N->getOpcode()) {
554 return performADDECombine(N, DAG, DCI, Subtarget);
556 return performSUBECombine(N, DAG, DCI, Subtarget);
558 return performMULCombine(N, DAG, DCI, this);
560 return performSHLCombine(N, DAG, DCI, Subtarget);
562 return performSRACombine(N, DAG, DCI, Subtarget);
564 return performSRLCombine(N, DAG, DCI, Subtarget);
566 return performVSELECTCombine(N, DAG);
568 Val = performSETCCCombine(N, DAG);
576 return MipsTargetLowering::PerformDAGCombine(N, DCI);
580 MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
581 MachineBasicBlock *BB) const {
582 switch (MI->getOpcode()) {
584 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
585 case Mips::BPOSGE32_PSEUDO:
586 return emitBPOSGE32(MI, BB);
587 case Mips::SNZ_B_PSEUDO:
588 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
589 case Mips::SNZ_H_PSEUDO:
590 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
591 case Mips::SNZ_W_PSEUDO:
592 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
593 case Mips::SNZ_D_PSEUDO:
594 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
595 case Mips::SNZ_V_PSEUDO:
596 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
597 case Mips::SZ_B_PSEUDO:
598 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
599 case Mips::SZ_H_PSEUDO:
600 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
601 case Mips::SZ_W_PSEUDO:
602 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
603 case Mips::SZ_D_PSEUDO:
604 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
605 case Mips::SZ_V_PSEUDO:
606 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
610 bool MipsSETargetLowering::
611 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
612 unsigned NextStackOffset,
613 const MipsFunctionInfo& FI) const {
614 if (!EnableMipsTailCalls)
617 // Return false if either the callee or caller has a byval argument.
618 if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
621 // Return true if the callee's argument area is no larger than the
623 return NextStackOffset <= FI.getIncomingArgSize();
626 void MipsSETargetLowering::
627 getOpndList(SmallVectorImpl<SDValue> &Ops,
628 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
629 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
630 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
631 // T9 should contain the address of the callee function if
632 // -reloction-model=pic or it is an indirect call.
633 if (IsPICCall || !GlobalOrExternal) {
634 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
635 RegsToPass.push_front(std::make_pair(T9Reg, Callee));
637 Ops.push_back(Callee);
639 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
640 InternalLinkage, CLI, Callee, Chain);
643 SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
644 LoadSDNode &Nd = *cast<LoadSDNode>(Op);
646 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
647 return MipsTargetLowering::lowerLOAD(Op, DAG);
649 // Replace a double precision load with two i32 loads and a buildpair64.
651 SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
652 EVT PtrVT = Ptr.getValueType();
654 // i32 load from lower address.
655 SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
656 MachinePointerInfo(), Nd.isVolatile(),
657 Nd.isNonTemporal(), Nd.isInvariant(),
660 // i32 load from higher address.
661 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
662 SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
663 MachinePointerInfo(), Nd.isVolatile(),
664 Nd.isNonTemporal(), Nd.isInvariant(),
665 std::min(Nd.getAlignment(), 4U));
667 if (!Subtarget->isLittle())
670 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
671 SDValue Ops[2] = {BP, Hi.getValue(1)};
672 return DAG.getMergeValues(Ops, 2, DL);
675 SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
676 StoreSDNode &Nd = *cast<StoreSDNode>(Op);
678 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
679 return MipsTargetLowering::lowerSTORE(Op, DAG);
681 // Replace a double precision store with two extractelement64s and i32 stores.
683 SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
684 EVT PtrVT = Ptr.getValueType();
685 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
686 Val, DAG.getConstant(0, MVT::i32));
687 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
688 Val, DAG.getConstant(1, MVT::i32));
690 if (!Subtarget->isLittle())
693 // i32 store to lower address.
694 Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
695 Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
698 // i32 store to higher address.
699 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
700 return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
701 Nd.isVolatile(), Nd.isNonTemporal(),
702 std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo());
705 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
706 bool HasLo, bool HasHi,
707 SelectionDAG &DAG) const {
708 EVT Ty = Op.getOperand(0).getValueType();
710 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
711 Op.getOperand(0), Op.getOperand(1));
715 Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
716 DAG.getConstant(Mips::sub_lo, MVT::i32));
718 Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
719 DAG.getConstant(Mips::sub_hi, MVT::i32));
721 if (!HasLo || !HasHi)
722 return HasLo ? Lo : Hi;
724 SDValue Vals[] = { Lo, Hi };
725 return DAG.getMergeValues(Vals, 2, DL);
729 static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
730 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
731 DAG.getConstant(0, MVT::i32));
732 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
733 DAG.getConstant(1, MVT::i32));
734 return DAG.getNode(MipsISD::InsertLOHI, DL, MVT::Untyped, InLo, InHi);
737 static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
738 SDValue Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
739 DAG.getConstant(Mips::sub_lo, MVT::i32));
740 SDValue Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
741 DAG.getConstant(Mips::sub_hi, MVT::i32));
742 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
745 // This function expands mips intrinsic nodes which have 64-bit input operands
748 // out64 = intrinsic-node in64
750 // lo = copy (extract-element (in64, 0))
751 // hi = copy (extract-element (in64, 1))
752 // mips-specific-node
755 // out64 = merge-values (v0, v1)
757 static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
759 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
760 SmallVector<SDValue, 3> Ops;
763 // See if Op has a chain input.
765 Ops.push_back(Op->getOperand(OpNo++));
767 // The next operand is the intrinsic opcode.
768 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
770 // See if the next operand has type i64.
771 SDValue Opnd = Op->getOperand(++OpNo), In64;
773 if (Opnd.getValueType() == MVT::i64)
774 In64 = initAccumulator(Opnd, DL, DAG);
778 // Push the remaining operands.
779 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
780 Ops.push_back(Op->getOperand(OpNo));
782 // Add In64 to the end of the list.
787 SmallVector<EVT, 2> ResTys;
789 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
791 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
794 SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size());
795 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
800 assert(Val->getValueType(1) == MVT::Other);
801 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
802 return DAG.getMergeValues(Vals, 2, DL);
805 static SDValue lowerMSABinaryIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
807 SDValue LHS = Op->getOperand(1);
808 SDValue RHS = Op->getOperand(2);
809 EVT ResTy = Op->getValueType(0);
811 SDValue Result = DAG.getNode(Opc, DL, ResTy, LHS, RHS);
816 static SDValue lowerMSABranchIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
818 SDValue Value = Op->getOperand(1);
819 EVT ResTy = Op->getValueType(0);
821 SDValue Result = DAG.getNode(Opc, DL, ResTy, Value);
826 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
827 SelectionDAG &DAG) const {
828 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
831 case Intrinsic::mips_shilo:
832 return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
833 case Intrinsic::mips_dpau_h_qbl:
834 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
835 case Intrinsic::mips_dpau_h_qbr:
836 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
837 case Intrinsic::mips_dpsu_h_qbl:
838 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
839 case Intrinsic::mips_dpsu_h_qbr:
840 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
841 case Intrinsic::mips_dpa_w_ph:
842 return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
843 case Intrinsic::mips_dps_w_ph:
844 return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
845 case Intrinsic::mips_dpax_w_ph:
846 return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
847 case Intrinsic::mips_dpsx_w_ph:
848 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
849 case Intrinsic::mips_mulsa_w_ph:
850 return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
851 case Intrinsic::mips_mult:
852 return lowerDSPIntr(Op, DAG, MipsISD::Mult);
853 case Intrinsic::mips_multu:
854 return lowerDSPIntr(Op, DAG, MipsISD::Multu);
855 case Intrinsic::mips_madd:
856 return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
857 case Intrinsic::mips_maddu:
858 return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
859 case Intrinsic::mips_msub:
860 return lowerDSPIntr(Op, DAG, MipsISD::MSub);
861 case Intrinsic::mips_msubu:
862 return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
863 case Intrinsic::mips_addv_b:
864 case Intrinsic::mips_addv_h:
865 case Intrinsic::mips_addv_w:
866 case Intrinsic::mips_addv_d:
867 return lowerMSABinaryIntr(Op, DAG, ISD::ADD);
868 case Intrinsic::mips_bnz_b:
869 case Intrinsic::mips_bnz_h:
870 case Intrinsic::mips_bnz_w:
871 case Intrinsic::mips_bnz_d:
872 return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_NONZERO);
873 case Intrinsic::mips_bnz_v:
874 return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_NONZERO);
875 case Intrinsic::mips_bz_b:
876 case Intrinsic::mips_bz_h:
877 case Intrinsic::mips_bz_w:
878 case Intrinsic::mips_bz_d:
879 return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_ZERO);
880 case Intrinsic::mips_bz_v:
881 return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_ZERO);
882 case Intrinsic::mips_div_s_b:
883 case Intrinsic::mips_div_s_h:
884 case Intrinsic::mips_div_s_w:
885 case Intrinsic::mips_div_s_d:
886 return lowerMSABinaryIntr(Op, DAG, ISD::SDIV);
887 case Intrinsic::mips_div_u_b:
888 case Intrinsic::mips_div_u_h:
889 case Intrinsic::mips_div_u_w:
890 case Intrinsic::mips_div_u_d:
891 return lowerMSABinaryIntr(Op, DAG, ISD::UDIV);
895 static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
897 SDValue ChainIn = Op->getOperand(0);
898 SDValue Address = Op->getOperand(2);
899 SDValue Offset = Op->getOperand(3);
900 EVT ResTy = Op->getValueType(0);
901 EVT PtrTy = Address->getValueType(0);
903 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
905 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
909 SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
910 SelectionDAG &DAG) const {
911 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
915 case Intrinsic::mips_extp:
916 return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
917 case Intrinsic::mips_extpdp:
918 return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
919 case Intrinsic::mips_extr_w:
920 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
921 case Intrinsic::mips_extr_r_w:
922 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
923 case Intrinsic::mips_extr_rs_w:
924 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
925 case Intrinsic::mips_extr_s_h:
926 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
927 case Intrinsic::mips_mthlip:
928 return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
929 case Intrinsic::mips_mulsaq_s_w_ph:
930 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
931 case Intrinsic::mips_maq_s_w_phl:
932 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
933 case Intrinsic::mips_maq_s_w_phr:
934 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
935 case Intrinsic::mips_maq_sa_w_phl:
936 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
937 case Intrinsic::mips_maq_sa_w_phr:
938 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
939 case Intrinsic::mips_dpaq_s_w_ph:
940 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
941 case Intrinsic::mips_dpsq_s_w_ph:
942 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
943 case Intrinsic::mips_dpaq_sa_l_w:
944 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
945 case Intrinsic::mips_dpsq_sa_l_w:
946 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
947 case Intrinsic::mips_dpaqx_s_w_ph:
948 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
949 case Intrinsic::mips_dpaqx_sa_w_ph:
950 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
951 case Intrinsic::mips_dpsqx_s_w_ph:
952 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
953 case Intrinsic::mips_dpsqx_sa_w_ph:
954 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
955 case Intrinsic::mips_ld_b:
956 case Intrinsic::mips_ld_h:
957 case Intrinsic::mips_ld_w:
958 case Intrinsic::mips_ld_d:
959 case Intrinsic::mips_ldx_b:
960 case Intrinsic::mips_ldx_h:
961 case Intrinsic::mips_ldx_w:
962 case Intrinsic::mips_ldx_d:
963 return lowerMSALoadIntr(Op, DAG, Intr);
967 static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
969 SDValue ChainIn = Op->getOperand(0);
970 SDValue Value = Op->getOperand(2);
971 SDValue Address = Op->getOperand(3);
972 SDValue Offset = Op->getOperand(4);
973 EVT PtrTy = Address->getValueType(0);
975 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
977 return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
981 SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
982 SelectionDAG &DAG) const {
983 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
987 case Intrinsic::mips_st_b:
988 case Intrinsic::mips_st_h:
989 case Intrinsic::mips_st_w:
990 case Intrinsic::mips_st_d:
991 case Intrinsic::mips_stx_b:
992 case Intrinsic::mips_stx_h:
993 case Intrinsic::mips_stx_w:
994 case Intrinsic::mips_stx_d:
995 return lowerMSAStoreIntr(Op, DAG, Intr);
999 MachineBasicBlock * MipsSETargetLowering::
1000 emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
1002 // bposge32_pseudo $vr0
1012 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
1014 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
1015 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1016 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
1017 DebugLoc DL = MI->getDebugLoc();
1018 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1019 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
1020 MachineFunction *F = BB->getParent();
1021 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
1022 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
1023 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
1026 F->insert(It, Sink);
1028 // Transfer the remainder of BB and its successor edges to Sink.
1029 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
1031 Sink->transferSuccessorsAndUpdatePHIs(BB);
1034 BB->addSuccessor(FBB);
1035 BB->addSuccessor(TBB);
1036 FBB->addSuccessor(Sink);
1037 TBB->addSuccessor(Sink);
1039 // Insert the real bposge32 instruction to $BB.
1040 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
1043 unsigned VR2 = RegInfo.createVirtualRegister(RC);
1044 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
1045 .addReg(Mips::ZERO).addImm(0);
1046 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
1049 unsigned VR1 = RegInfo.createVirtualRegister(RC);
1050 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
1051 .addReg(Mips::ZERO).addImm(1);
1053 // Insert phi function to $Sink.
1054 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
1055 MI->getOperand(0).getReg())
1056 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
1058 MI->eraseFromParent(); // The pseudo instruction is gone now.
1062 MachineBasicBlock * MipsSETargetLowering::
1063 emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
1064 unsigned BranchOp) const{
1066 // vany_nonzero $rd, $ws
1077 // $rd = phi($rd1, $fbb, $rd2, $tbb)
1079 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
1080 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1081 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
1082 DebugLoc DL = MI->getDebugLoc();
1083 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1084 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
1085 MachineFunction *F = BB->getParent();
1086 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
1087 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
1088 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
1091 F->insert(It, Sink);
1093 // Transfer the remainder of BB and its successor edges to Sink.
1094 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
1096 Sink->transferSuccessorsAndUpdatePHIs(BB);
1099 BB->addSuccessor(FBB);
1100 BB->addSuccessor(TBB);
1101 FBB->addSuccessor(Sink);
1102 TBB->addSuccessor(Sink);
1104 // Insert the real bnz.b instruction to $BB.
1105 BuildMI(BB, DL, TII->get(BranchOp))
1106 .addReg(MI->getOperand(1).getReg())
1110 unsigned RD1 = RegInfo.createVirtualRegister(RC);
1111 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
1112 .addReg(Mips::ZERO).addImm(0);
1113 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
1116 unsigned RD2 = RegInfo.createVirtualRegister(RC);
1117 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
1118 .addReg(Mips::ZERO).addImm(1);
1120 // Insert phi function to $Sink.
1121 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
1122 MI->getOperand(0).getReg())
1123 .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
1125 MI->eraseFromParent(); // The pseudo instruction is gone now.