1 //===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsDAGToDAGISel specialized for mips32/64.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
15 #include "MipsSEISelDAGToDAG.h"
17 #include "MCTargetDesc/MipsBaseInfo.h"
18 #include "MipsAnalyzeImmediate.h"
19 #include "MipsMachineFunction.h"
20 #include "MipsRegisterInfo.h"
21 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/CFG.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetMachine.h"
38 bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
39 if (Subtarget.inMips16Mode())
41 return MipsDAGToDAGISel::runOnMachineFunction(MF);
44 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
45 MachineFunction &MF) {
46 MachineInstrBuilder MIB(MF, &MI);
47 unsigned Mask = MI.getOperand(1).getImm();
48 unsigned Flag = IsDef ? RegState::ImplicitDefine : RegState::Implicit;
51 MIB.addReg(Mips::DSPPos, Flag);
54 MIB.addReg(Mips::DSPSCount, Flag);
57 MIB.addReg(Mips::DSPCarry, Flag);
60 MIB.addReg(Mips::DSPOutFlag, Flag);
63 MIB.addReg(Mips::DSPCCond, Flag);
66 MIB.addReg(Mips::DSPEFI, Flag);
69 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
70 switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
72 llvm_unreachable("Could not map int to register");
73 case 0: return Mips::MSAIR;
74 case 1: return Mips::MSACSR;
75 case 2: return Mips::MSAAccess;
76 case 3: return Mips::MSASave;
77 case 4: return Mips::MSAModify;
78 case 5: return Mips::MSARequest;
79 case 6: return Mips::MSAMap;
80 case 7: return Mips::MSAUnmap;
84 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
85 const MachineInstr& MI) {
86 unsigned DstReg = 0, ZeroReg = 0;
88 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
89 if ((MI.getOpcode() == Mips::ADDiu) &&
90 (MI.getOperand(1).getReg() == Mips::ZERO) &&
91 (MI.getOperand(2).getImm() == 0)) {
92 DstReg = MI.getOperand(0).getReg();
94 } else if ((MI.getOpcode() == Mips::DADDiu) &&
95 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
96 (MI.getOperand(2).getImm() == 0)) {
97 DstReg = MI.getOperand(0).getReg();
98 ZeroReg = Mips::ZERO_64;
104 // Replace uses with ZeroReg.
105 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
106 E = MRI->use_end(); U != E;) {
107 MachineOperand &MO = U.getOperand();
108 unsigned OpNo = U.getOperandNo();
109 MachineInstr *MI = MO.getParent();
112 // Do not replace if it is a phi's operand or is tied to def operand.
113 if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
122 void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
123 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
125 if (!MipsFI->globalBaseRegSet())
128 MachineBasicBlock &MBB = MF.front();
129 MachineBasicBlock::iterator I = MBB.begin();
130 MachineRegisterInfo &RegInfo = MF.getRegInfo();
131 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
132 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
133 unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
134 const TargetRegisterClass *RC;
136 if (Subtarget.isABI_N64())
137 RC = (const TargetRegisterClass*)&Mips::GPR64RegClass;
139 RC = (const TargetRegisterClass*)&Mips::GPR32RegClass;
141 V0 = RegInfo.createVirtualRegister(RC);
142 V1 = RegInfo.createVirtualRegister(RC);
144 if (Subtarget.isABI_N64()) {
145 MF.getRegInfo().addLiveIn(Mips::T9_64);
146 MBB.addLiveIn(Mips::T9_64);
148 // lui $v0, %hi(%neg(%gp_rel(fname)))
149 // daddu $v1, $v0, $t9
150 // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
151 const GlobalValue *FName = MF.getFunction();
152 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
153 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
154 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
155 .addReg(Mips::T9_64);
156 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
157 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
161 if (MF.getTarget().getRelocationModel() == Reloc::Static) {
162 // Set global register to __gnu_local_gp.
164 // lui $v0, %hi(__gnu_local_gp)
165 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
166 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
167 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
168 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
169 .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
173 MF.getRegInfo().addLiveIn(Mips::T9);
174 MBB.addLiveIn(Mips::T9);
176 if (Subtarget.isABI_N32()) {
177 // lui $v0, %hi(%neg(%gp_rel(fname)))
178 // addu $v1, $v0, $t9
179 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
180 const GlobalValue *FName = MF.getFunction();
181 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
182 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
183 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
184 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
185 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
189 assert(Subtarget.isABI_O32());
191 // For O32 ABI, the following instruction sequence is emitted to initialize
192 // the global base register:
194 // 0. lui $2, %hi(_gp_disp)
195 // 1. addiu $2, $2, %lo(_gp_disp)
196 // 2. addu $globalbasereg, $2, $t9
198 // We emit only the last instruction here.
200 // GNU linker requires that the first two instructions appear at the beginning
201 // of a function and no instructions be inserted before or between them.
202 // The two instructions are emitted during lowering to MC layer in order to
203 // avoid any reordering.
205 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
206 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
208 MF.getRegInfo().addLiveIn(Mips::V0);
209 MBB.addLiveIn(Mips::V0);
210 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
211 .addReg(Mips::V0).addReg(Mips::T9);
214 void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
215 initGlobalBaseReg(MF);
217 MachineRegisterInfo *MRI = &MF.getRegInfo();
219 for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
221 for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) {
222 if (I->getOpcode() == Mips::RDDSP)
223 addDSPCtrlRegOperands(false, *I, MF);
224 else if (I->getOpcode() == Mips::WRDSP)
225 addDSPCtrlRegOperands(true, *I, MF);
227 replaceUsesWithZeroReg(MRI, *I);
231 SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
232 SDValue CmpLHS, SDLoc DL,
233 SDNode *Node) const {
234 unsigned Opc = InFlag.getOpcode(); (void)Opc;
236 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
237 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
238 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
240 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
241 SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
242 EVT VT = LHS.getValueType();
244 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops);
245 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT,
246 SDValue(Carry, 0), RHS);
247 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
248 SDValue(AddCarry, 0));
251 /// ComplexPattern used on MipsInstrInfo
252 /// Used on Mips Load/Store instructions
253 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
254 SDValue &Offset) const {
255 EVT ValTy = Addr.getValueType();
257 // if Address is FI, get the TargetFrameIndex.
258 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
259 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
260 Offset = CurDAG->getTargetConstant(0, ValTy);
264 // on PIC code Load GA
265 if (Addr.getOpcode() == MipsISD::Wrapper) {
266 Base = Addr.getOperand(0);
267 Offset = Addr.getOperand(1);
271 if (TM.getRelocationModel() != Reloc::PIC_) {
272 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
273 Addr.getOpcode() == ISD::TargetGlobalAddress))
277 // Addresses of the form FI+const or FI|const
278 if (CurDAG->isBaseWithConstantOffset(Addr)) {
279 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
280 if (isInt<16>(CN->getSExtValue())) {
282 // If the first operand is a FI, get the TargetFI Node
283 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
284 (Addr.getOperand(0)))
285 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
287 Base = Addr.getOperand(0);
289 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
294 // Operand is a result from an ADD.
295 if (Addr.getOpcode() == ISD::ADD) {
296 // When loading from constant pools, load the lower address part in
297 // the instruction itself. Example, instead of:
298 // lui $2, %hi($CPI1_0)
299 // addiu $2, $2, %lo($CPI1_0)
302 // lui $2, %hi($CPI1_0)
303 // lwc1 $f0, %lo($CPI1_0)($2)
304 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
305 Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
306 SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
307 if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
308 isa<JumpTableSDNode>(Opnd0)) {
309 Base = Addr.getOperand(0);
319 bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
320 SDValue &Offset) const {
322 Offset = CurDAG->getTargetConstant(0, Addr.getValueType());
326 bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
327 SDValue &Offset) const {
328 return selectAddrRegImm(Addr, Base, Offset) ||
329 selectAddrDefault(Addr, Base, Offset);
332 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
333 bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
334 SDValue &Offset) const {
335 EVT ValTy = Addr.getValueType();
337 // Addresses of the form FI+const or FI|const
338 if (CurDAG->isBaseWithConstantOffset(Addr)) {
339 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
340 if (isInt<12>(CN->getSExtValue())) {
342 // If the first operand is a FI, get the TargetFI Node
343 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
344 (Addr.getOperand(0)))
345 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
347 Base = Addr.getOperand(0);
349 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
357 bool MipsSEDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
358 SDValue &Offset) const {
359 return selectAddrRegImm12(Addr, Base, Offset) ||
360 selectAddrDefault(Addr, Base, Offset);
363 std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
364 unsigned Opcode = Node->getOpcode();
368 // Instruction Selection not handled by the auto-generated
369 // tablegen selection should be handled here.
377 SDValue InFlag = Node->getOperand(2);
378 Result = selectAddESubE(Mips::SUBu, InFlag, InFlag.getOperand(0), DL, Node);
379 return std::make_pair(true, Result);
383 if (Subtarget.hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
385 SDValue InFlag = Node->getOperand(2);
386 Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node);
387 return std::make_pair(true, Result);
390 case ISD::ConstantFP: {
391 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
392 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
393 if (Subtarget.hasMips64()) {
394 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
395 Mips::ZERO_64, MVT::i64);
396 Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
398 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
399 Mips::ZERO, MVT::i32);
400 Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero,
404 return std::make_pair(true, Result);
409 case ISD::Constant: {
410 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
411 unsigned Size = CN->getValueSizeInBits(0);
416 MipsAnalyzeImmediate AnalyzeImm;
417 int64_t Imm = CN->getSExtValue();
419 const MipsAnalyzeImmediate::InstSeq &Seq =
420 AnalyzeImm.Analyze(Imm, Size, false);
422 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
425 SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
428 // The first instruction can be a LUi which is different from other
429 // instructions (ADDiu, ORI and SLL) in that it does not have a register
431 if (Inst->Opc == Mips::LUi64)
432 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
435 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
436 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
439 // The remaining instructions in the sequence are handled here.
440 for (++Inst; Inst != Seq.end(); ++Inst) {
441 ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
443 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
444 SDValue(RegOpnd, 0), ImmOpnd);
447 return std::make_pair(true, RegOpnd);
450 case ISD::INTRINSIC_W_CHAIN: {
451 switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
455 case Intrinsic::mips_cfcmsa: {
456 SDValue ChainIn = Node->getOperand(0);
457 SDValue RegIdx = Node->getOperand(2);
458 SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
459 getMSACtrlReg(RegIdx), MVT::i32);
460 return std::make_pair(true, Reg.getNode());
466 case ISD::INTRINSIC_WO_CHAIN: {
467 switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
471 case Intrinsic::mips_move_v:
472 // Like an assignment but will always produce a move.v even if
474 return std::make_pair(true,
475 CurDAG->getMachineNode(Mips::MOVE_V, DL,
476 Node->getValueType(0),
477 Node->getOperand(1)));
482 case ISD::INTRINSIC_VOID: {
483 switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
487 case Intrinsic::mips_ctcmsa: {
488 SDValue ChainIn = Node->getOperand(0);
489 SDValue RegIdx = Node->getOperand(2);
490 SDValue Value = Node->getOperand(3);
491 SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
492 getMSACtrlReg(RegIdx), Value);
493 return std::make_pair(true, ChainOut.getNode());
499 case MipsISD::ThreadPointer: {
500 EVT PtrVT = getTargetLowering()->getPointerTy();
501 unsigned RdhwrOpc, DestReg;
503 if (PtrVT == MVT::i32) {
504 RdhwrOpc = Mips::RDHWR;
507 RdhwrOpc = Mips::RDHWR64;
508 DestReg = Mips::V1_64;
512 CurDAG->getMachineNode(RdhwrOpc, SDLoc(Node),
513 Node->getValueType(0),
514 CurDAG->getRegister(Mips::HWR29, MVT::i32));
515 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
517 SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
518 ReplaceUses(SDValue(Node, 0), ResNode);
519 return std::make_pair(true, ResNode.getNode());
522 case MipsISD::InsertLOHI: {
523 unsigned RCID = Subtarget.hasDSP() ? Mips::ACC64DSPRegClassID :
524 Mips::ACC64RegClassID;
525 SDValue RegClass = CurDAG->getTargetConstant(RCID, MVT::i32);
526 SDValue LoIdx = CurDAG->getTargetConstant(Mips::sub_lo, MVT::i32);
527 SDValue HiIdx = CurDAG->getTargetConstant(Mips::sub_hi, MVT::i32);
528 const SDValue Ops[] = { RegClass, Node->getOperand(0), LoIdx,
529 Node->getOperand(1), HiIdx };
530 SDNode *Res = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL,
532 return std::make_pair(true, Res);
536 return std::make_pair(false, (SDNode*)NULL);
539 FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) {
540 return new MipsSEDAGToDAGISel(TM);