1 //===- MipsRegisterInfo.td - Mips Register defs ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the MIPS register file
12 //===----------------------------------------------------------------------===//
13 let Namespace = "Mips" in {
14 def sub_fpeven : SubRegIndex;
15 def sub_fpodd : SubRegIndex;
16 def sub_32 : SubRegIndex;
19 // We have banks of 32 registers each.
20 class MipsReg<string n> : Register<n> {
22 let Namespace = "Mips";
25 class MipsRegWithSubRegs<string n, list<Register> subregs>
26 : RegisterWithSubRegs<n, subregs> {
28 let Namespace = "Mips";
32 class MipsGPRReg<bits<5> num, string n> : MipsReg<n> {
36 // Mips 32-bit FPU Registers
37 class FPR<bits<5> num, string n> : MipsReg<n> {
41 // Mips 64-bit (aliased) FPU Registers
42 class AFPR<bits<5> num, string n, list<Register> subregs>
43 : MipsRegWithSubRegs<n, subregs> {
45 let SubRegIndices = [sub_fpeven, sub_fpodd];
48 class AFPR64<bits<5> num, string n, list<Register> subregs>
49 : MipsRegWithSubRegs<n, subregs> {
51 let SubRegIndices = [sub_32];
54 // Mips Hardware Registers
55 class HWR<bits<5> num, string n> : MipsReg<n> {
59 //===----------------------------------------------------------------------===//
61 //===----------------------------------------------------------------------===//
63 let Namespace = "Mips" in {
65 // General Purpose Registers
66 def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<[0]>;
67 def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>;
68 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
69 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
70 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
71 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
72 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
73 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
74 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
75 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
76 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>;
77 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>;
78 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>;
79 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>;
80 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>;
81 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>;
82 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>;
83 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>;
84 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>;
85 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>;
86 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>;
87 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>;
88 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>;
89 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>;
90 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>;
91 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>;
92 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>;
93 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>;
94 def GP : MipsGPRReg< 28, "GP">, DwarfRegNum<[28]>;
95 def SP : MipsGPRReg< 29, "SP">, DwarfRegNum<[29]>;
96 def FP : MipsGPRReg< 30, "FP">, DwarfRegNum<[30]>;
97 def RA : MipsGPRReg< 31, "RA">, DwarfRegNum<[31]>;
99 /// Mips Single point precision FPU Registers
100 def F0 : FPR< 0, "F0">, DwarfRegNum<[32]>;
101 def F1 : FPR< 1, "F1">, DwarfRegNum<[33]>;
102 def F2 : FPR< 2, "F2">, DwarfRegNum<[34]>;
103 def F3 : FPR< 3, "F3">, DwarfRegNum<[35]>;
104 def F4 : FPR< 4, "F4">, DwarfRegNum<[36]>;
105 def F5 : FPR< 5, "F5">, DwarfRegNum<[37]>;
106 def F6 : FPR< 6, "F6">, DwarfRegNum<[38]>;
107 def F7 : FPR< 7, "F7">, DwarfRegNum<[39]>;
108 def F8 : FPR< 8, "F8">, DwarfRegNum<[40]>;
109 def F9 : FPR< 9, "F9">, DwarfRegNum<[41]>;
110 def F10 : FPR<10, "F10">, DwarfRegNum<[42]>;
111 def F11 : FPR<11, "F11">, DwarfRegNum<[43]>;
112 def F12 : FPR<12, "F12">, DwarfRegNum<[44]>;
113 def F13 : FPR<13, "F13">, DwarfRegNum<[45]>;
114 def F14 : FPR<14, "F14">, DwarfRegNum<[46]>;
115 def F15 : FPR<15, "F15">, DwarfRegNum<[47]>;
116 def F16 : FPR<16, "F16">, DwarfRegNum<[48]>;
117 def F17 : FPR<17, "F17">, DwarfRegNum<[49]>;
118 def F18 : FPR<18, "F18">, DwarfRegNum<[50]>;
119 def F19 : FPR<19, "F19">, DwarfRegNum<[51]>;
120 def F20 : FPR<20, "F20">, DwarfRegNum<[52]>;
121 def F21 : FPR<21, "F21">, DwarfRegNum<[53]>;
122 def F22 : FPR<22, "F22">, DwarfRegNum<[54]>;
123 def F23 : FPR<23, "F23">, DwarfRegNum<[55]>;
124 def F24 : FPR<24, "F24">, DwarfRegNum<[56]>;
125 def F25 : FPR<25, "F25">, DwarfRegNum<[57]>;
126 def F26 : FPR<26, "F26">, DwarfRegNum<[58]>;
127 def F27 : FPR<27, "F27">, DwarfRegNum<[59]>;
128 def F28 : FPR<28, "F28">, DwarfRegNum<[60]>;
129 def F29 : FPR<29, "F29">, DwarfRegNum<[61]>;
130 def F30 : FPR<30, "F30">, DwarfRegNum<[62]>;
131 def F31 : FPR<31, "F31">, DwarfRegNum<[63]>;
133 /// Mips Double point precision FPU Registers (aliased
134 /// with the single precision to hold 64 bit values)
135 def D0 : AFPR< 0, "F0", [F0, F1]>;
136 def D1 : AFPR< 2, "F2", [F2, F3]>;
137 def D2 : AFPR< 4, "F4", [F4, F5]>;
138 def D3 : AFPR< 6, "F6", [F6, F7]>;
139 def D4 : AFPR< 8, "F8", [F8, F9]>;
140 def D5 : AFPR<10, "F10", [F10, F11]>;
141 def D6 : AFPR<12, "F12", [F12, F13]>;
142 def D7 : AFPR<14, "F14", [F14, F15]>;
143 def D8 : AFPR<16, "F16", [F16, F17]>;
144 def D9 : AFPR<18, "F18", [F18, F19]>;
145 def D10 : AFPR<20, "F20", [F20, F21]>;
146 def D11 : AFPR<22, "F22", [F22, F23]>;
147 def D12 : AFPR<24, "F24", [F24, F25]>;
148 def D13 : AFPR<26, "F26", [F26, F27]>;
149 def D14 : AFPR<28, "F28", [F28, F29]>;
150 def D15 : AFPR<30, "F30", [F30, F31]>;
152 /// Mips Double point precision FPU Registers in MFP64 mode.
153 def D0_64 : AFPR64<0, "F0", [F0]>;
154 def D1_64 : AFPR64<1, "F1", [F1]>;
155 def D2_64 : AFPR64<2, "F2", [F2]>;
156 def D3_64 : AFPR64<3, "F3", [F3]>;
157 def D4_64 : AFPR64<4, "F4", [F4]>;
158 def D5_64 : AFPR64<5, "F5", [F5]>;
159 def D6_64 : AFPR64<6, "F6", [F6]>;
160 def D7_64 : AFPR64<7, "F7", [F7]>;
161 def D8_64 : AFPR64<8, "F8", [F8]>;
162 def D9_64 : AFPR64<9, "F9", [F9]>;
163 def D10_64 : AFPR64<10, "F10", [F10]>;
164 def D11_64 : AFPR64<11, "F11", [F11]>;
165 def D12_64 : AFPR64<12, "F12", [F12]>;
166 def D13_64 : AFPR64<13, "F13", [F13]>;
167 def D14_64 : AFPR64<14, "F14", [F14]>;
168 def D15_64 : AFPR64<15, "F15", [F15]>;
169 def D16_64 : AFPR64<16, "F16", [F16]>;
170 def D17_64 : AFPR64<17, "F17", [F17]>;
171 def D18_64 : AFPR64<18, "F18", [F18]>;
172 def D19_64 : AFPR64<19, "F19", [F19]>;
173 def D20_64 : AFPR64<20, "F20", [F20]>;
174 def D21_64 : AFPR64<21, "F21", [F21]>;
175 def D22_64 : AFPR64<22, "F22", [F22]>;
176 def D23_64 : AFPR64<23, "F23", [F23]>;
177 def D24_64 : AFPR64<24, "F24", [F24]>;
178 def D25_64 : AFPR64<25, "F25", [F25]>;
179 def D26_64 : AFPR64<26, "F26", [F26]>;
180 def D27_64 : AFPR64<27, "F27", [F27]>;
181 def D28_64 : AFPR64<28, "F28", [F28]>;
182 def D29_64 : AFPR64<29, "F29", [F29]>;
183 def D30_64 : AFPR64<30, "F30", [F30]>;
184 def D31_64 : AFPR64<31, "F31", [F31]>;
187 def HI : Register<"hi">, DwarfRegNum<[64]>;
188 def LO : Register<"lo">, DwarfRegNum<[65]>;
190 // Status flags register
191 def FCR31 : Register<"31">;
193 // Hardware register $29
194 def HWR29 : Register<"29">;
197 //===----------------------------------------------------------------------===//
199 //===----------------------------------------------------------------------===//
201 def CPURegs : RegisterClass<"Mips", [i32], 32, (add
202 // Return Values and Arguments
203 V0, V1, A0, A1, A2, A3,
204 // Not preserved across procedure calls
205 T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
207 S0, S1, S2, S3, S4, S5, S6, S7,
209 ZERO, AT, K0, K1, GP, SP, FP, RA)>;
212 // * FGR64 - 32 64-bit registers
213 // * AFGR64 - 16 32-bit even registers (32-bit FP Mode)
216 // * FGR32 - 16 32-bit even registers
217 // * FGR32 - 32 32-bit registers (single float only mode)
218 def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>;
220 def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
221 // Return Values and Arguments
223 // Not preserved across procedure calls
224 D2, D3, D4, D5, D8, D9,
226 D10, D11, D12, D13, D14, D15)> {
227 let SubRegClasses = [(FGR32 sub_fpeven, sub_fpodd)];
230 // Condition Register for floating point operations
231 def CCR : RegisterClass<"Mips", [i32], 32, (add FCR31)>;
234 def HILO : RegisterClass<"Mips", [i32], 32, (add HI, LO)>;
236 // Hardware registers
237 def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>;