1 //===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-reg-info"
17 #include "MipsAnalyzeImmediate.h"
18 #include "MipsSubtarget.h"
19 #include "MipsRegisterInfo.h"
20 #include "MipsMachineFunction.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Type.h"
23 #include "llvm/Function.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/Target/TargetFrameLowering.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/ADT/BitVector.h"
37 #include "llvm/ADT/STLExtras.h"
38 #include "llvm/Analysis/DebugInfo.h"
40 #define GET_REGINFO_TARGET_DESC
41 #include "MipsGenRegisterInfo.inc"
45 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
46 const TargetInstrInfo &tii)
47 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST), TII(tii) {}
49 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
51 //===----------------------------------------------------------------------===//
52 // Callee Saved Registers methods
53 //===----------------------------------------------------------------------===//
55 /// Mips Callee Saved Registers
56 const unsigned* MipsRegisterInfo::
57 getCalleeSavedRegs(const MachineFunction *MF) const
59 // Mips callee-save register range is $16-$23, $f20-$f30
60 static const unsigned SingleFloatOnlyCalleeSavedRegs[] = {
61 Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26,
62 Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20,
63 Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4,
64 Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0
67 static const unsigned Mips32CalleeSavedRegs[] = {
68 Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10,
69 Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4,
70 Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0
73 static const unsigned N32CalleeSavedRegs[] = {
74 Mips::D31_64, Mips::D29_64, Mips::D27_64, Mips::D25_64, Mips::D23_64,
76 Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64,
77 Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64,
81 static const unsigned N64CalleeSavedRegs[] = {
82 Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64,
83 Mips::D26_64, Mips::D25_64, Mips::D24_64,
84 Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64,
85 Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64,
89 if (Subtarget.isSingleFloat())
90 return SingleFloatOnlyCalleeSavedRegs;
91 else if (!Subtarget.hasMips64())
92 return Mips32CalleeSavedRegs;
93 else if (Subtarget.isABI_N32())
94 return N32CalleeSavedRegs;
96 assert(Subtarget.isABI_N64());
97 return N64CalleeSavedRegs;
100 BitVector MipsRegisterInfo::
101 getReservedRegs(const MachineFunction &MF) const {
102 static const unsigned ReservedCPURegs[] = {
103 Mips::ZERO, Mips::AT, Mips::K0, Mips::K1,
104 Mips::SP, Mips::FP, Mips::RA
107 static const unsigned ReservedCPU64Regs[] = {
108 Mips::ZERO_64, Mips::AT_64, Mips::K0_64, Mips::K1_64,
109 Mips::SP_64, Mips::FP_64, Mips::RA_64
112 BitVector Reserved(getNumRegs());
113 typedef TargetRegisterClass::iterator RegIter;
115 for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I)
116 Reserved.set(ReservedCPURegs[I]);
118 if (Subtarget.hasMips64()) {
119 for (unsigned I = 0; I < array_lengthof(ReservedCPU64Regs); ++I)
120 Reserved.set(ReservedCPU64Regs[I]);
122 // Reserve all registers in AFGR64.
123 for (RegIter Reg = Mips::AFGR64RegisterClass->begin();
124 Reg != Mips::AFGR64RegisterClass->end(); ++Reg)
128 // Reserve all registers in CPU64Regs & FGR64.
129 for (RegIter Reg = Mips::CPU64RegsRegisterClass->begin();
130 Reg != Mips::CPU64RegsRegisterClass->end(); ++Reg)
133 for (RegIter Reg = Mips::FGR64RegisterClass->begin();
134 Reg != Mips::FGR64RegisterClass->end(); ++Reg)
138 // If GP is dedicated as a global base register, reserve it.
139 if (MF.getInfo<MipsFunctionInfo>()->globalBaseRegFixed()) {
140 Reserved.set(Mips::GP);
141 Reserved.set(Mips::GP_64);
147 // This function eliminate ADJCALLSTACKDOWN,
148 // ADJCALLSTACKUP pseudo instructions
149 void MipsRegisterInfo::
150 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
151 MachineBasicBlock::iterator I) const {
152 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
156 // FrameIndex represent objects inside a abstract stack.
157 // We must replace FrameIndex with an stack/frame pointer
159 void MipsRegisterInfo::
160 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
161 RegScavenger *RS) const {
162 MachineInstr &MI = *II;
163 MachineFunction &MF = *MI.getParent()->getParent();
164 MachineFrameInfo *MFI = MF.getFrameInfo();
165 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
168 while (!MI.getOperand(i).isFI()) {
170 assert(i < MI.getNumOperands() &&
171 "Instr doesn't have FrameIndex operand!");
174 DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n";
175 errs() << "<--------->\n" << MI);
177 int FrameIndex = MI.getOperand(i).getIndex();
178 uint64_t stackSize = MF.getFrameInfo()->getStackSize();
179 int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
181 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
182 << "spOffset : " << spOffset << "\n"
183 << "stackSize : " << stackSize << "\n");
185 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
190 MinCSFI = CSI[0].getFrameIdx();
191 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
194 // The following stack frame objects are always referenced relative to $sp:
195 // 1. Outgoing arguments.
196 // 2. Pointer to dynamically allocated stack space.
197 // 3. Locations for callee-saved registers.
198 // Everything else is referenced relative to whatever register
199 // getFrameRegister() returns.
202 if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex) ||
203 (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI))
204 FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP;
206 FrameReg = getFrameRegister(MF);
208 // Calculate final offset.
209 // - There is no need to change the offset if the frame object is one of the
210 // following: an outgoing argument, pointer to a dynamically allocated
211 // stack space or a $gp restore location,
212 // - If the frame object is any of the following, its offset must be adjusted
213 // by adding the size of the stack:
214 // incoming argument, callee-saved register location or local variable.
217 if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isGPFI(FrameIndex) ||
218 MipsFI->isDynAllocFI(FrameIndex))
221 Offset = spOffset + (int64_t)stackSize;
223 Offset += MI.getOperand(i+1).getImm();
225 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
227 // If MI is not a debug value, make sure Offset fits in the 16-bit immediate
229 if (!MI.isDebugValue() && !isInt<16>(Offset)) {
230 MachineBasicBlock &MBB = *MI.getParent();
231 DebugLoc DL = II->getDebugLoc();
232 MipsAnalyzeImmediate AnalyzeImm;
233 unsigned Size = Subtarget.isABI_N64() ? 64 : 32;
234 unsigned LUi = Subtarget.isABI_N64() ? Mips::LUi64 : Mips::LUi;
235 unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu;
236 unsigned ZEROReg = Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
237 unsigned ATReg = Subtarget.isABI_N64() ? Mips::AT_64 : Mips::AT;
238 const MipsAnalyzeImmediate::InstSeq &Seq =
239 AnalyzeImm.Analyze(Offset, Size, true /* LastInstrIsADDiu */);
240 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
242 // FIXME: change this when mips goes MC".
243 BuildMI(MBB, II, DL, TII.get(Mips::NOAT));
245 // The first instruction can be a LUi, which is different from other
246 // instructions (ADDiu, ORI and SLL) in that it does not have a register
248 if (Inst->Opc == LUi)
249 BuildMI(MBB, II, DL, TII.get(LUi), ATReg)
250 .addImm(SignExtend64<16>(Inst->ImmOpnd));
252 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg)
253 .addImm(SignExtend64<16>(Inst->ImmOpnd));
255 // Build the remaining instructions in Seq except for the last one.
256 for (++Inst; Inst != Seq.end() - 1; ++Inst)
257 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg)
258 .addImm(SignExtend64<16>(Inst->ImmOpnd));
260 BuildMI(MBB, II, DL, TII.get(ADDu), ATReg).addReg(FrameReg).addReg(ATReg);
263 Offset = SignExtend64<16>(Inst->ImmOpnd);
264 BuildMI(MBB, ++II, MI.getDebugLoc(), TII.get(Mips::ATMACRO));
267 MI.getOperand(i).ChangeToRegister(FrameReg, false);
268 MI.getOperand(i+1).ChangeToImmediate(Offset);
271 unsigned MipsRegisterInfo::
272 getFrameRegister(const MachineFunction &MF) const {
273 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
274 bool IsN64 = Subtarget.isABI_N64();
276 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
277 (IsN64 ? Mips::SP_64 : Mips::SP);
280 unsigned MipsRegisterInfo::
281 getEHExceptionRegister() const {
282 llvm_unreachable("What is the exception register");
285 unsigned MipsRegisterInfo::
286 getEHHandlerRegister() const {
287 llvm_unreachable("What is the exception handler register");