1 //===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips MSA ASE instructions.
12 //===----------------------------------------------------------------------===//
14 def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>;
15 def SDT_VSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
18 SDTCisVT<3, OtherVT>]>;
19 def SDT_VFSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
22 SDTCisVT<3, OtherVT>]>;
23 def SDT_VSHF : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>,
24 SDTCisInt<1>, SDTCisVec<1>,
25 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>;
26 def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
27 SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>;
28 def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
29 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
30 def SDT_INSVE : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
31 SDTCisVT<2, i32>, SDTCisSameAs<0, 3>,
34 def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>;
35 def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>;
36 def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>;
37 def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>;
38 def MipsVSMax : SDNode<"MipsISD::VSMAX", SDTIntBinOp,
39 [SDNPCommutative, SDNPAssociative]>;
40 def MipsVSMin : SDNode<"MipsISD::VSMIN", SDTIntBinOp,
41 [SDNPCommutative, SDNPAssociative]>;
42 def MipsVUMax : SDNode<"MipsISD::VUMAX", SDTIntBinOp,
43 [SDNPCommutative, SDNPAssociative]>;
44 def MipsVUMin : SDNode<"MipsISD::VUMIN", SDTIntBinOp,
45 [SDNPCommutative, SDNPAssociative]>;
46 def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp,
47 [SDNPCommutative, SDNPAssociative]>;
48 def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>;
49 def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>;
50 def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>;
51 def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>;
52 def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>;
53 def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>;
54 def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>;
55 def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>;
56 def MipsINSVE : SDNode<"MipsISD::INSVE", SDT_INSVE>;
58 def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>;
59 def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>;
61 def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT",
62 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
63 def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT",
64 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
68 def uimm2 : Operand<i32> {
69 let PrintMethod = "printUnsignedImm";
72 // The immediate of an LSA instruction needs special handling
73 // as the encoded value should be subtracted by one.
74 def uimm2LSAAsmOperand : AsmOperandClass {
76 let ParserMethod = "ParseLSAImm";
77 let RenderMethod = "addImmOperands";
80 def LSAImm : Operand<i32> {
81 let PrintMethod = "printUnsignedImm";
82 let EncoderMethod = "getLSAImmEncoding";
83 let DecoderMethod = "DecodeLSAImm";
84 let ParserMatchClass = uimm2LSAAsmOperand;
87 def uimm3 : Operand<i32> {
88 let PrintMethod = "printUnsignedImm8";
91 def uimm4 : Operand<i32> {
92 let PrintMethod = "printUnsignedImm8";
95 def uimm8 : Operand<i32> {
96 let PrintMethod = "printUnsignedImm8";
99 def simm5 : Operand<i32>;
101 def vsplat_uimm1 : Operand<vAny> {
102 let PrintMethod = "printUnsignedImm8";
105 def vsplat_uimm2 : Operand<vAny> {
106 let PrintMethod = "printUnsignedImm8";
109 def vsplat_uimm3 : Operand<vAny> {
110 let PrintMethod = "printUnsignedImm8";
113 def vsplat_uimm4 : Operand<vAny> {
114 let PrintMethod = "printUnsignedImm8";
117 def vsplat_uimm5 : Operand<vAny> {
118 let PrintMethod = "printUnsignedImm8";
121 def vsplat_uimm6 : Operand<vAny> {
122 let PrintMethod = "printUnsignedImm8";
125 def vsplat_uimm8 : Operand<vAny> {
126 let PrintMethod = "printUnsignedImm8";
129 def vsplat_simm5 : Operand<vAny>;
131 def vsplat_simm10 : Operand<vAny>;
133 def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>;
136 def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx),
137 (MipsVExtractSExt node:$vec, node:$idx, i8)>;
138 def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx),
139 (MipsVExtractSExt node:$vec, node:$idx, i16)>;
140 def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx),
141 (MipsVExtractSExt node:$vec, node:$idx, i32)>;
142 def vextract_sext_i64 : PatFrag<(ops node:$vec, node:$idx),
143 (MipsVExtractSExt node:$vec, node:$idx, i64)>;
145 def vextract_zext_i8 : PatFrag<(ops node:$vec, node:$idx),
146 (MipsVExtractZExt node:$vec, node:$idx, i8)>;
147 def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx),
148 (MipsVExtractZExt node:$vec, node:$idx, i16)>;
149 def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx),
150 (MipsVExtractZExt node:$vec, node:$idx, i32)>;
151 def vextract_zext_i64 : PatFrag<(ops node:$vec, node:$idx),
152 (MipsVExtractZExt node:$vec, node:$idx, i64)>;
154 def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx),
155 (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>;
156 def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx),
157 (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>;
158 def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx),
159 (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>;
160 def vinsert_v2i64 : PatFrag<(ops node:$vec, node:$val, node:$idx),
161 (v2i64 (vector_insert node:$vec, node:$val, node:$idx))>;
163 def insve_v16i8 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
164 (v16i8 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
165 def insve_v8i16 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
166 (v8i16 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
167 def insve_v4i32 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
168 (v4i32 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
169 def insve_v2i64 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
170 (v2i64 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
172 class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> :
173 PatFrag<(ops node:$lhs, node:$rhs),
174 (ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>;
176 // ISD::SETFALSE cannot occur
177 def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>;
178 def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>;
179 def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>;
180 def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>;
181 def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>;
182 def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>;
183 def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>;
184 def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>;
185 def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>;
186 def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>;
187 def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>;
188 def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>;
189 def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>;
190 def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>;
191 def vfsetun_v4f32 : vfsetcc_type<v4i32, v4f32, SETUO>;
192 def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>;
193 def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>;
194 def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>;
195 def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>;
196 def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>;
197 def vfsetugt_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGT>;
198 def vfsetugt_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGT>;
199 def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>;
200 def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>;
201 def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>;
202 def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>;
203 def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>;
204 def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>;
205 // ISD::SETTRUE cannot occur
206 // ISD::SETFALSE2 cannot occur
207 // ISD::SETTRUE2 cannot occur
209 class vsetcc_type<ValueType ResTy, CondCode CC> :
210 PatFrag<(ops node:$lhs, node:$rhs),
211 (ResTy (vsetcc node:$lhs, node:$rhs, CC))>;
213 def vseteq_v16i8 : vsetcc_type<v16i8, SETEQ>;
214 def vseteq_v8i16 : vsetcc_type<v8i16, SETEQ>;
215 def vseteq_v4i32 : vsetcc_type<v4i32, SETEQ>;
216 def vseteq_v2i64 : vsetcc_type<v2i64, SETEQ>;
217 def vsetle_v16i8 : vsetcc_type<v16i8, SETLE>;
218 def vsetle_v8i16 : vsetcc_type<v8i16, SETLE>;
219 def vsetle_v4i32 : vsetcc_type<v4i32, SETLE>;
220 def vsetle_v2i64 : vsetcc_type<v2i64, SETLE>;
221 def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>;
222 def vsetlt_v8i16 : vsetcc_type<v8i16, SETLT>;
223 def vsetlt_v4i32 : vsetcc_type<v4i32, SETLT>;
224 def vsetlt_v2i64 : vsetcc_type<v2i64, SETLT>;
225 def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>;
226 def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>;
227 def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>;
228 def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>;
229 def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>;
230 def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>;
231 def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>;
232 def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>;
234 def vsplati8 : PatFrag<(ops node:$e0),
235 (v16i8 (build_vector node:$e0, node:$e0,
242 node:$e0, node:$e0))>;
243 def vsplati16 : PatFrag<(ops node:$e0),
244 (v8i16 (build_vector node:$e0, node:$e0,
247 node:$e0, node:$e0))>;
248 def vsplati32 : PatFrag<(ops node:$e0),
249 (v4i32 (build_vector node:$e0, node:$e0,
250 node:$e0, node:$e0))>;
251 def vsplati64 : PatFrag<(ops node:$e0),
252 (v2i64 (build_vector node:$e0, node:$e0))>;
253 def vsplatf32 : PatFrag<(ops node:$e0),
254 (v4f32 (build_vector node:$e0, node:$e0,
255 node:$e0, node:$e0))>;
256 def vsplatf64 : PatFrag<(ops node:$e0),
257 (v2f64 (build_vector node:$e0, node:$e0))>;
259 def vsplati8_elt : PatFrag<(ops node:$v, node:$i),
260 (MipsVSHF (vsplati8 node:$i), node:$v, node:$v)>;
261 def vsplati16_elt : PatFrag<(ops node:$v, node:$i),
262 (MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>;
263 def vsplati32_elt : PatFrag<(ops node:$v, node:$i),
264 (MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>;
265 def vsplati64_elt : PatFrag<(ops node:$v, node:$i),
266 (MipsVSHF (vsplati64 node:$i), node:$v, node:$v)>;
268 class SplatPatLeaf<Operand opclass, dag frag, code pred = [{}],
269 SDNodeXForm xform = NOOP_SDNodeXForm>
270 : PatLeaf<frag, pred, xform> {
271 Operand OpClass = opclass;
274 class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn,
275 list<SDNode> roots = [],
276 list<SDNodeProperty> props = []> :
277 ComplexPattern<ty, numops, fn, roots, props> {
278 Operand OpClass = opclass;
281 def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1,
283 [build_vector, bitconvert]>;
285 def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1,
287 [build_vector, bitconvert]>;
289 def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1,
291 [build_vector, bitconvert]>;
293 def vsplati8_uimm8 : SplatComplexPattern<vsplat_uimm8, v16i8, 1,
295 [build_vector, bitconvert]>;
297 def vsplati8_simm5 : SplatComplexPattern<vsplat_simm5, v16i8, 1,
299 [build_vector, bitconvert]>;
301 def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1,
303 [build_vector, bitconvert]>;
305 def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1,
307 [build_vector, bitconvert]>;
309 def vsplati16_uimm5 : SplatComplexPattern<vsplat_uimm5, v8i16, 1,
311 [build_vector, bitconvert]>;
313 def vsplati16_simm5 : SplatComplexPattern<vsplat_simm5, v8i16, 1,
315 [build_vector, bitconvert]>;
317 def vsplati32_uimm2 : SplatComplexPattern<vsplat_uimm2, v4i32, 1,
319 [build_vector, bitconvert]>;
321 def vsplati32_uimm5 : SplatComplexPattern<vsplat_uimm5, v4i32, 1,
323 [build_vector, bitconvert]>;
325 def vsplati32_simm5 : SplatComplexPattern<vsplat_simm5, v4i32, 1,
327 [build_vector, bitconvert]>;
329 def vsplati64_uimm1 : SplatComplexPattern<vsplat_uimm1, v2i64, 1,
331 [build_vector, bitconvert]>;
333 def vsplati64_uimm5 : SplatComplexPattern<vsplat_uimm5, v2i64, 1,
335 [build_vector, bitconvert]>;
337 def vsplati64_uimm6 : SplatComplexPattern<vsplat_uimm6, v2i64, 1,
339 [build_vector, bitconvert]>;
341 def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1,
343 [build_vector, bitconvert]>;
345 // Any build_vector that is a constant splat with a value that is an exact
347 def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2",
348 [build_vector, bitconvert]>;
350 // Any build_vector that is a constant splat with a value that is the bitwise
351 // inverse of an exact power of 2
352 def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2",
353 [build_vector, bitconvert]>;
355 // Any build_vector that is a constant splat with only a consecutive sequence
356 // of left-most bits set.
357 def vsplat_maskl_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1,
359 [build_vector, bitconvert]>;
361 // Any build_vector that is a constant splat with only a consecutive sequence
362 // of right-most bits set.
363 def vsplat_maskr_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1,
365 [build_vector, bitconvert]>;
367 // Any build_vector that is a constant splat with a value that equals 1
368 // FIXME: These should be a ComplexPattern but we can't use them because the
369 // ISel generator requires the uses to have a name, but providing a name
370 // causes other errors ("used in pattern but not operand list")
371 def vsplat_imm_eq_1 : PatLeaf<(build_vector), [{
373 EVT EltTy = N->getValueType(0).getVectorElementType();
375 return selectVSplat (N, Imm) &&
376 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1;
379 def vsplati64_imm_eq_1 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{
381 SDNode *BV = N->getOperand(0).getNode();
382 EVT EltTy = N->getValueType(0).getVectorElementType();
384 return selectVSplat (BV, Imm) &&
385 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1;
388 def vbclr_b : PatFrag<(ops node:$ws, node:$wt),
389 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
391 def vbclr_h : PatFrag<(ops node:$ws, node:$wt),
392 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
394 def vbclr_w : PatFrag<(ops node:$ws, node:$wt),
395 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
397 def vbclr_d : PatFrag<(ops node:$ws, node:$wt),
398 (and node:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1),
400 (bitconvert (v4i32 immAllOnesV))))>;
402 def vbneg_b : PatFrag<(ops node:$ws, node:$wt),
403 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
404 def vbneg_h : PatFrag<(ops node:$ws, node:$wt),
405 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
406 def vbneg_w : PatFrag<(ops node:$ws, node:$wt),
407 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
408 def vbneg_d : PatFrag<(ops node:$ws, node:$wt),
409 (xor node:$ws, (shl (v2i64 vsplati64_imm_eq_1),
412 def vbset_b : PatFrag<(ops node:$ws, node:$wt),
413 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
414 def vbset_h : PatFrag<(ops node:$ws, node:$wt),
415 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
416 def vbset_w : PatFrag<(ops node:$ws, node:$wt),
417 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
418 def vbset_d : PatFrag<(ops node:$ws, node:$wt),
419 (or node:$ws, (shl (v2i64 vsplati64_imm_eq_1),
422 def fms : PatFrag<(ops node:$wd, node:$ws, node:$wt),
423 (fsub node:$wd, (fmul node:$ws, node:$wt))>;
425 def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt),
426 (add node:$wd, (mul node:$ws, node:$wt))>;
428 def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt),
429 (sub node:$wd, (mul node:$ws, node:$wt))>;
431 def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt),
432 (fmul node:$ws, (fexp2 node:$wt))>;
435 def immSExt5 : ImmLeaf<i32, [{return isInt<5>(Imm);}]>;
436 def immSExt10: ImmLeaf<i32, [{return isInt<10>(Imm);}]>;
438 // Instruction encoding.
439 class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>;
440 class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>;
441 class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>;
442 class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>;
444 class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>;
445 class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>;
446 class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>;
447 class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>;
449 class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>;
450 class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>;
451 class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>;
452 class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>;
454 class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>;
455 class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>;
456 class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>;
457 class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>;
459 class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>;
460 class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>;
461 class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>;
462 class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>;
464 class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>;
465 class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>;
466 class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>;
467 class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>;
469 class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>;
471 class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>;
473 class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>;
474 class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>;
475 class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>;
476 class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>;
478 class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>;
479 class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>;
480 class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>;
481 class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>;
483 class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>;
484 class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>;
485 class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>;
486 class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>;
488 class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>;
489 class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>;
490 class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>;
491 class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>;
493 class AVER_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010000>;
494 class AVER_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010000>;
495 class AVER_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010000>;
496 class AVER_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010000>;
498 class AVER_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010000>;
499 class AVER_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010000>;
500 class AVER_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010000>;
501 class AVER_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010000>;
503 class BCLR_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001101>;
504 class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>;
505 class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>;
506 class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>;
508 class BCLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001001>;
509 class BCLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001001>;
510 class BCLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001001>;
511 class BCLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001001>;
513 class BINSL_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001101>;
514 class BINSL_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001101>;
515 class BINSL_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001101>;
516 class BINSL_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001101>;
518 class BINSLI_B_ENC : MSA_BIT_B_FMT<0b110, 0b001001>;
519 class BINSLI_H_ENC : MSA_BIT_H_FMT<0b110, 0b001001>;
520 class BINSLI_W_ENC : MSA_BIT_W_FMT<0b110, 0b001001>;
521 class BINSLI_D_ENC : MSA_BIT_D_FMT<0b110, 0b001001>;
523 class BINSR_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001101>;
524 class BINSR_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001101>;
525 class BINSR_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001101>;
526 class BINSR_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001101>;
528 class BINSRI_B_ENC : MSA_BIT_B_FMT<0b111, 0b001001>;
529 class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>;
530 class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>;
531 class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>;
533 class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>;
535 class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>;
537 class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>;
539 class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>;
541 class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>;
542 class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>;
543 class BNEG_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001101>;
544 class BNEG_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001101>;
546 class BNEGI_B_ENC : MSA_BIT_B_FMT<0b101, 0b001001>;
547 class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>;
548 class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>;
549 class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>;
551 class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>;
552 class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>;
553 class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>;
554 class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>;
556 class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01111>;
558 class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>;
560 class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>;
562 class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>;
563 class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>;
564 class BSET_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001101>;
565 class BSET_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001101>;
567 class BSETI_B_ENC : MSA_BIT_B_FMT<0b100, 0b001001>;
568 class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>;
569 class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>;
570 class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>;
572 class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>;
573 class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>;
574 class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>;
575 class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>;
577 class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>;
579 class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>;
580 class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>;
581 class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>;
582 class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>;
584 class CEQI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000111>;
585 class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>;
586 class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>;
587 class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>;
589 class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>;
591 class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>;
592 class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>;
593 class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>;
594 class CLE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001111>;
596 class CLE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001111>;
597 class CLE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001111>;
598 class CLE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001111>;
599 class CLE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001111>;
601 class CLEI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000111>;
602 class CLEI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000111>;
603 class CLEI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000111>;
604 class CLEI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000111>;
606 class CLEI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000111>;
607 class CLEI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000111>;
608 class CLEI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000111>;
609 class CLEI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000111>;
611 class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>;
612 class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>;
613 class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>;
614 class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>;
616 class CLT_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001111>;
617 class CLT_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001111>;
618 class CLT_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001111>;
619 class CLT_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001111>;
621 class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>;
622 class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>;
623 class CLTI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000111>;
624 class CLTI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000111>;
626 class CLTI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000111>;
627 class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>;
628 class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>;
629 class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>;
631 class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>;
632 class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>;
633 class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>;
634 class COPY_S_D_ENC : MSA_ELM_COPY_D_FMT<0b0010, 0b011001>;
636 class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>;
637 class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>;
638 class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>;
639 class COPY_U_D_ENC : MSA_ELM_COPY_D_FMT<0b0011, 0b011001>;
641 class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>;
643 class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>;
644 class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>;
645 class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>;
646 class DIV_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010010>;
648 class DIV_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010010>;
649 class DIV_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010010>;
650 class DIV_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010010>;
651 class DIV_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010010>;
653 class DOTP_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010011>;
654 class DOTP_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010011>;
655 class DOTP_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010011>;
657 class DOTP_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010011>;
658 class DOTP_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010011>;
659 class DOTP_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010011>;
661 class DPADD_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010011>;
662 class DPADD_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010011>;
663 class DPADD_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010011>;
665 class DPADD_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010011>;
666 class DPADD_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010011>;
667 class DPADD_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010011>;
669 class DPSUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010011>;
670 class DPSUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010011>;
671 class DPSUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010011>;
673 class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>;
674 class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>;
675 class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>;
677 class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>;
678 class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>;
680 class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>;
681 class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>;
683 class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>;
684 class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>;
686 class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>;
687 class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>;
689 class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>;
690 class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>;
692 class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>;
693 class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>;
695 class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>;
696 class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>;
698 class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>;
699 class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>;
701 class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>;
702 class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>;
704 class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>;
705 class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>;
707 class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>;
708 class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>;
710 class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>;
711 class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>;
713 class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>;
714 class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>;
716 class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>;
717 class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>;
719 class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>;
720 class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>;
722 class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>;
723 class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>;
725 class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>;
726 class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>;
728 class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>;
729 class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>;
731 class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>;
732 class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>;
734 class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>;
735 class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>;
737 class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>;
738 class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>;
740 class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>;
741 class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>;
743 class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>;
744 class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>;
745 class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>;
746 class FILL_D_ENC : MSA_2R_FILL_D_FMT<0b11000000, 0b11, 0b011110>;
748 class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>;
749 class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>;
751 class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>;
752 class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>;
754 class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>;
755 class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>;
757 class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>;
758 class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>;
760 class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>;
761 class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>;
763 class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>;
764 class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>;
766 class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>;
767 class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>;
769 class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>;
770 class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>;
772 class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>;
773 class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>;
775 class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>;
776 class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>;
778 class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>;
779 class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>;
781 class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>;
782 class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>;
784 class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>;
785 class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>;
787 class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>;
788 class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>;
790 class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>;
791 class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>;
793 class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>;
794 class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>;
796 class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>;
797 class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>;
799 class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>;
800 class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>;
802 class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>;
803 class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>;
805 class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>;
806 class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>;
808 class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>;
809 class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>;
811 class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>;
812 class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>;
814 class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>;
815 class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>;
817 class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>;
818 class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>;
820 class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>;
821 class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>;
823 class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>;
824 class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>;
826 class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>;
827 class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>;
829 class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>;
830 class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>;
832 class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>;
833 class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>;
835 class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>;
836 class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>;
837 class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>;
839 class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>;
840 class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>;
841 class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>;
843 class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>;
844 class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>;
845 class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>;
847 class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>;
848 class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>;
849 class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>;
851 class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>;
852 class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>;
853 class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>;
854 class ILVEV_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010100>;
856 class ILVL_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010100>;
857 class ILVL_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010100>;
858 class ILVL_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010100>;
859 class ILVL_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010100>;
861 class ILVOD_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010100>;
862 class ILVOD_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010100>;
863 class ILVOD_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010100>;
864 class ILVOD_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010100>;
866 class ILVR_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010100>;
867 class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>;
868 class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>;
869 class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>;
871 class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>;
872 class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>;
873 class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>;
874 class INSERT_D_ENC : MSA_ELM_INSERT_D_FMT<0b0100, 0b011001>;
876 class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>;
877 class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>;
878 class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>;
879 class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>;
881 class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>;
882 class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>;
883 class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>;
884 class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>;
886 class LDI_B_ENC : MSA_I10_FMT<0b110, 0b00, 0b000111>;
887 class LDI_H_ENC : MSA_I10_FMT<0b110, 0b01, 0b000111>;
888 class LDI_W_ENC : MSA_I10_FMT<0b110, 0b10, 0b000111>;
889 class LDI_D_ENC : MSA_I10_FMT<0b110, 0b11, 0b000111>;
891 class LSA_ENC : SPECIAL_LSA_FMT<0b000101>;
892 class DLSA_ENC : SPECIAL_DLSA_FMT<0b010101>;
894 class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>;
895 class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>;
897 class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>;
898 class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>;
900 class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>;
901 class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>;
902 class MADDV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010010>;
903 class MADDV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010010>;
905 class MAX_A_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001110>;
906 class MAX_A_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001110>;
907 class MAX_A_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001110>;
908 class MAX_A_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001110>;
910 class MAX_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001110>;
911 class MAX_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001110>;
912 class MAX_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001110>;
913 class MAX_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001110>;
915 class MAX_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001110>;
916 class MAX_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001110>;
917 class MAX_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001110>;
918 class MAX_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001110>;
920 class MAXI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000110>;
921 class MAXI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000110>;
922 class MAXI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000110>;
923 class MAXI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000110>;
925 class MAXI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000110>;
926 class MAXI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000110>;
927 class MAXI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000110>;
928 class MAXI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000110>;
930 class MIN_A_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001110>;
931 class MIN_A_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001110>;
932 class MIN_A_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001110>;
933 class MIN_A_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001110>;
935 class MIN_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001110>;
936 class MIN_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001110>;
937 class MIN_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001110>;
938 class MIN_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001110>;
940 class MIN_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001110>;
941 class MIN_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001110>;
942 class MIN_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001110>;
943 class MIN_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001110>;
945 class MINI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000110>;
946 class MINI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000110>;
947 class MINI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000110>;
948 class MINI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000110>;
950 class MINI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000110>;
951 class MINI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000110>;
952 class MINI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000110>;
953 class MINI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000110>;
955 class MOD_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010010>;
956 class MOD_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010010>;
957 class MOD_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010010>;
958 class MOD_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010010>;
960 class MOD_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010010>;
961 class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>;
962 class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>;
963 class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>;
965 class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>;
967 class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>;
968 class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>;
970 class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>;
971 class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>;
973 class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>;
974 class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>;
975 class MSUBV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010010>;
976 class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>;
978 class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>;
979 class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>;
981 class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>;
982 class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>;
984 class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>;
985 class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>;
986 class MULV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010010>;
987 class MULV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010010>;
989 class NLOC_B_ENC : MSA_2R_FMT<0b11000010, 0b00, 0b011110>;
990 class NLOC_H_ENC : MSA_2R_FMT<0b11000010, 0b01, 0b011110>;
991 class NLOC_W_ENC : MSA_2R_FMT<0b11000010, 0b10, 0b011110>;
992 class NLOC_D_ENC : MSA_2R_FMT<0b11000010, 0b11, 0b011110>;
994 class NLZC_B_ENC : MSA_2R_FMT<0b11000011, 0b00, 0b011110>;
995 class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>;
996 class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>;
997 class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>;
999 class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>;
1001 class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>;
1003 class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>;
1005 class ORI_B_ENC : MSA_I8_FMT<0b01, 0b000000>;
1007 class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>;
1008 class PCKEV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010100>;
1009 class PCKEV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010100>;
1010 class PCKEV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010100>;
1012 class PCKOD_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010100>;
1013 class PCKOD_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010100>;
1014 class PCKOD_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010100>;
1015 class PCKOD_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010100>;
1017 class PCNT_B_ENC : MSA_2R_FMT<0b11000001, 0b00, 0b011110>;
1018 class PCNT_H_ENC : MSA_2R_FMT<0b11000001, 0b01, 0b011110>;
1019 class PCNT_W_ENC : MSA_2R_FMT<0b11000001, 0b10, 0b011110>;
1020 class PCNT_D_ENC : MSA_2R_FMT<0b11000001, 0b11, 0b011110>;
1022 class SAT_S_B_ENC : MSA_BIT_B_FMT<0b000, 0b001010>;
1023 class SAT_S_H_ENC : MSA_BIT_H_FMT<0b000, 0b001010>;
1024 class SAT_S_W_ENC : MSA_BIT_W_FMT<0b000, 0b001010>;
1025 class SAT_S_D_ENC : MSA_BIT_D_FMT<0b000, 0b001010>;
1027 class SAT_U_B_ENC : MSA_BIT_B_FMT<0b001, 0b001010>;
1028 class SAT_U_H_ENC : MSA_BIT_H_FMT<0b001, 0b001010>;
1029 class SAT_U_W_ENC : MSA_BIT_W_FMT<0b001, 0b001010>;
1030 class SAT_U_D_ENC : MSA_BIT_D_FMT<0b001, 0b001010>;
1032 class SHF_B_ENC : MSA_I8_FMT<0b00, 0b000010>;
1033 class SHF_H_ENC : MSA_I8_FMT<0b01, 0b000010>;
1034 class SHF_W_ENC : MSA_I8_FMT<0b10, 0b000010>;
1036 class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>;
1037 class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>;
1038 class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>;
1039 class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>;
1041 class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>;
1042 class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>;
1043 class SLDI_W_ENC : MSA_ELM_W_FMT<0b0000, 0b011001>;
1044 class SLDI_D_ENC : MSA_ELM_D_FMT<0b0000, 0b011001>;
1046 class SLL_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001101>;
1047 class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>;
1048 class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>;
1049 class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>;
1051 class SLLI_B_ENC : MSA_BIT_B_FMT<0b000, 0b001001>;
1052 class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>;
1053 class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>;
1054 class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>;
1056 class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>;
1057 class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>;
1058 class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>;
1059 class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>;
1061 class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>;
1062 class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>;
1063 class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>;
1064 class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>;
1066 class SRA_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001101>;
1067 class SRA_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001101>;
1068 class SRA_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001101>;
1069 class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>;
1071 class SRAI_B_ENC : MSA_BIT_B_FMT<0b001, 0b001001>;
1072 class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>;
1073 class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>;
1074 class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>;
1076 class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>;
1077 class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>;
1078 class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>;
1079 class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>;
1081 class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>;
1082 class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>;
1083 class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>;
1084 class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>;
1086 class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>;
1087 class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>;
1088 class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>;
1089 class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>;
1091 class SRLI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001001>;
1092 class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>;
1093 class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>;
1094 class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>;
1096 class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>;
1097 class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>;
1098 class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>;
1099 class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>;
1101 class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>;
1102 class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>;
1103 class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>;
1104 class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>;
1106 class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>;
1107 class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>;
1108 class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>;
1109 class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>;
1111 class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>;
1112 class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>;
1113 class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>;
1114 class SUBS_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010001>;
1116 class SUBS_U_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010001>;
1117 class SUBS_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010001>;
1118 class SUBS_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010001>;
1119 class SUBS_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010001>;
1121 class SUBSUS_U_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010001>;
1122 class SUBSUS_U_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010001>;
1123 class SUBSUS_U_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010001>;
1124 class SUBSUS_U_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010001>;
1126 class SUBSUU_S_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010001>;
1127 class SUBSUU_S_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010001>;
1128 class SUBSUU_S_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010001>;
1129 class SUBSUU_S_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010001>;
1131 class SUBV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001110>;
1132 class SUBV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001110>;
1133 class SUBV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001110>;
1134 class SUBV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001110>;
1136 class SUBVI_B_ENC : MSA_I5_FMT<0b001, 0b00, 0b000110>;
1137 class SUBVI_H_ENC : MSA_I5_FMT<0b001, 0b01, 0b000110>;
1138 class SUBVI_W_ENC : MSA_I5_FMT<0b001, 0b10, 0b000110>;
1139 class SUBVI_D_ENC : MSA_I5_FMT<0b001, 0b11, 0b000110>;
1141 class VSHF_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010101>;
1142 class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>;
1143 class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>;
1144 class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>;
1146 class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>;
1148 class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>;
1150 // Instruction desc.
1151 class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1152 ComplexPattern Imm, RegisterOperand ROWD,
1153 RegisterOperand ROWS = ROWD,
1154 InstrItinClass itin = NoItinerary> {
1155 dag OutOperandList = (outs ROWD:$wd);
1156 dag InOperandList = (ins ROWS:$ws, vsplat_uimm3:$m);
1157 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1158 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1159 InstrItinClass Itinerary = itin;
1162 class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1163 ComplexPattern Imm, RegisterOperand ROWD,
1164 RegisterOperand ROWS = ROWD,
1165 InstrItinClass itin = NoItinerary> {
1166 dag OutOperandList = (outs ROWD:$wd);
1167 dag InOperandList = (ins ROWS:$ws, vsplat_uimm4:$m);
1168 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1169 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1170 InstrItinClass Itinerary = itin;
1173 class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1174 ComplexPattern Imm, RegisterOperand ROWD,
1175 RegisterOperand ROWS = ROWD,
1176 InstrItinClass itin = NoItinerary> {
1177 dag OutOperandList = (outs ROWD:$wd);
1178 dag InOperandList = (ins ROWS:$ws, vsplat_uimm5:$m);
1179 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1180 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1181 InstrItinClass Itinerary = itin;
1184 class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1185 ComplexPattern Imm, RegisterOperand ROWD,
1186 RegisterOperand ROWS = ROWD,
1187 InstrItinClass itin = NoItinerary> {
1188 dag OutOperandList = (outs ROWD:$wd);
1189 dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m);
1190 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1191 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1192 InstrItinClass Itinerary = itin;
1195 // This class is deprecated and will be removed soon.
1196 class MSA_BIT_B_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1197 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1198 InstrItinClass itin = NoItinerary> {
1199 dag OutOperandList = (outs ROWD:$wd);
1200 dag InOperandList = (ins ROWS:$ws, uimm3:$m);
1201 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1202 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt3:$m))];
1203 InstrItinClass Itinerary = itin;
1206 // This class is deprecated and will be removed soon.
1207 class MSA_BIT_H_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1208 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1209 InstrItinClass itin = NoItinerary> {
1210 dag OutOperandList = (outs ROWD:$wd);
1211 dag InOperandList = (ins ROWS:$ws, uimm4:$m);
1212 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1213 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt4:$m))];
1214 InstrItinClass Itinerary = itin;
1217 // This class is deprecated and will be removed soon.
1218 class MSA_BIT_W_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1219 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1220 InstrItinClass itin = NoItinerary> {
1221 dag OutOperandList = (outs ROWD:$wd);
1222 dag InOperandList = (ins ROWS:$ws, uimm5:$m);
1223 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1224 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt5:$m))];
1225 InstrItinClass Itinerary = itin;
1228 // This class is deprecated and will be removed soon.
1229 class MSA_BIT_D_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1230 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1231 InstrItinClass itin = NoItinerary> {
1232 dag OutOperandList = (outs ROWD:$wd);
1233 dag InOperandList = (ins ROWS:$ws, uimm6:$m);
1234 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1235 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt6:$m))];
1236 InstrItinClass Itinerary = itin;
1239 class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty,
1240 ComplexPattern Mask, RegisterOperand ROWD,
1241 RegisterOperand ROWS = ROWD,
1242 InstrItinClass itin = NoItinerary> {
1243 dag OutOperandList = (outs ROWD:$wd);
1244 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, vsplat_uimm8:$m);
1245 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1246 // Note that binsxi and vselect treat the condition operand the opposite
1247 // way to each other.
1248 // (vselect cond, if_set, if_clear)
1249 // (BSEL_V cond, if_clear, if_set)
1250 list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$ws),
1252 InstrItinClass Itinerary = itin;
1253 string Constraints = "$wd = $wd_in";
1256 class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty,
1257 RegisterOperand ROWD,
1258 RegisterOperand ROWS = ROWD,
1259 InstrItinClass itin = NoItinerary> :
1260 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskl_bits, ROWD, ROWS, itin>;
1262 class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty,
1263 RegisterOperand ROWD,
1264 RegisterOperand ROWS = ROWD,
1265 InstrItinClass itin = NoItinerary> :
1266 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskr_bits, ROWD, ROWS, itin>;
1268 class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1269 SplatComplexPattern SplatImm,
1270 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1271 InstrItinClass itin = NoItinerary> {
1272 dag OutOperandList = (outs ROWD:$wd);
1273 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m);
1274 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1275 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))];
1276 InstrItinClass Itinerary = itin;
1279 class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1280 ValueType VecTy, RegisterOperand ROD,
1281 RegisterOperand ROWS,
1282 InstrItinClass itin = NoItinerary> {
1283 dag OutOperandList = (outs ROD:$rd);
1284 dag InOperandList = (ins ROWS:$ws, uimm4:$n);
1285 string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]");
1286 list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), immZExt4:$n))];
1287 InstrItinClass Itinerary = itin;
1290 class MSA_ELM_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1291 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1292 InstrItinClass itin = NoItinerary> {
1293 dag OutOperandList = (outs ROWD:$wd);
1294 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, uimm4:$n);
1295 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1296 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1298 string Constraints = "$wd = $wd_in";
1299 InstrItinClass Itinerary = itin;
1302 class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy,
1303 RegisterClass RCD, RegisterClass RCWS> :
1304 MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, uimm4:$n),
1305 [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), immZExt4:$n))]> {
1306 bit usesCustomInserter = 1;
1309 class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1310 SplatComplexPattern SplatImm, RegisterOperand ROWD,
1311 RegisterOperand ROWS = ROWD,
1312 InstrItinClass itin = NoItinerary> {
1313 dag OutOperandList = (outs ROWD:$wd);
1314 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm);
1315 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm");
1316 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))];
1317 InstrItinClass Itinerary = itin;
1320 class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1321 SplatComplexPattern SplatImm, RegisterOperand ROWD,
1322 RegisterOperand ROWS = ROWD,
1323 InstrItinClass itin = NoItinerary> {
1324 dag OutOperandList = (outs ROWD:$wd);
1325 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8);
1326 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1327 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))];
1328 InstrItinClass Itinerary = itin;
1331 class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1332 RegisterOperand ROWS = ROWD,
1333 InstrItinClass itin = NoItinerary> {
1334 dag OutOperandList = (outs ROWD:$wd);
1335 dag InOperandList = (ins ROWS:$ws, uimm8:$u8);
1336 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1337 list<dag> Pattern = [(set ROWD:$wd, (MipsSHF immZExt8:$u8, ROWS:$ws))];
1338 InstrItinClass Itinerary = itin;
1341 class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1342 InstrItinClass itin = NoItinerary> {
1343 dag OutOperandList = (outs ROWD:$wd);
1344 dag InOperandList = (ins vsplat_simm10:$s10);
1345 string AsmString = !strconcat(instr_asm, "\t$wd, $s10");
1346 // LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp
1347 list<dag> Pattern = [];
1348 bit hasSideEffects = 0;
1349 InstrItinClass Itinerary = itin;
1352 class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1353 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1354 InstrItinClass itin = NoItinerary> {
1355 dag OutOperandList = (outs ROWD:$wd);
1356 dag InOperandList = (ins ROWS:$ws);
1357 string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1358 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1359 InstrItinClass Itinerary = itin;
1362 class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT,
1363 SDPatternOperator OpNode, RegisterOperand ROWD,
1364 RegisterOperand ROS = ROWD,
1365 InstrItinClass itin = NoItinerary> {
1366 dag OutOperandList = (outs ROWD:$wd);
1367 dag InOperandList = (ins ROS:$rs);
1368 string AsmString = !strconcat(instr_asm, "\t$wd, $rs");
1369 list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))];
1370 InstrItinClass Itinerary = itin;
1373 class MSA_2R_FILL_PSEUDO_BASE<ValueType VT, SDPatternOperator OpNode,
1374 RegisterClass RCWD, RegisterClass RCWS = RCWD> :
1375 MSAPseudo<(outs RCWD:$wd), (ins RCWS:$fs),
1376 [(set RCWD:$wd, (OpNode RCWS:$fs))]> {
1377 let usesCustomInserter = 1;
1380 class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1381 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1382 InstrItinClass itin = NoItinerary> {
1383 dag OutOperandList = (outs ROWD:$wd);
1384 dag InOperandList = (ins ROWS:$ws);
1385 string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1386 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1387 InstrItinClass Itinerary = itin;
1390 class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1391 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1392 RegisterOperand ROWT = ROWD,
1393 InstrItinClass itin = NoItinerary> {
1394 dag OutOperandList = (outs ROWD:$wd);
1395 dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1396 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1397 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1398 InstrItinClass Itinerary = itin;
1401 class MSA_3R_BINSX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1402 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1403 RegisterOperand ROWT = ROWD,
1404 InstrItinClass itin = NoItinerary> {
1405 dag OutOperandList = (outs ROWD:$wd);
1406 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1407 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1408 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1410 string Constraints = "$wd = $wd_in";
1411 InstrItinClass Itinerary = itin;
1414 class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1415 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1416 InstrItinClass itin = NoItinerary> {
1417 dag OutOperandList = (outs ROWD:$wd);
1418 dag InOperandList = (ins ROWS:$ws, GPR32Opnd:$rt);
1419 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1420 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32Opnd:$rt))];
1421 InstrItinClass Itinerary = itin;
1424 class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1425 RegisterOperand ROWS = ROWD,
1426 RegisterOperand ROWT = ROWD,
1427 InstrItinClass itin = NoItinerary> {
1428 dag OutOperandList = (outs ROWD:$wd);
1429 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1430 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1431 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws,
1433 string Constraints = "$wd = $wd_in";
1434 InstrItinClass Itinerary = itin;
1437 class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1438 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1439 InstrItinClass itin = NoItinerary> {
1440 dag OutOperandList = (outs ROWD:$wd);
1441 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, GPR32Opnd:$rt);
1442 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1443 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1445 InstrItinClass Itinerary = itin;
1446 string Constraints = "$wd = $wd_in";
1449 class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1450 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1451 RegisterOperand ROWT = ROWD,
1452 InstrItinClass itin = NoItinerary> {
1453 dag OutOperandList = (outs ROWD:$wd);
1454 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1455 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1456 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1458 InstrItinClass Itinerary = itin;
1459 string Constraints = "$wd = $wd_in";
1462 class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1463 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1464 RegisterOperand ROWT = ROWD,
1465 InstrItinClass itin = NoItinerary> :
1466 MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1468 class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1469 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1470 RegisterOperand ROWT = ROWD,
1471 InstrItinClass itin = NoItinerary> :
1472 MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1474 class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> {
1475 dag OutOperandList = (outs);
1476 dag InOperandList = (ins ROWD:$wt, brtarget:$offset);
1477 string AsmString = !strconcat(instr_asm, "\t$wt, $offset");
1478 list<dag> Pattern = [];
1479 InstrItinClass Itinerary = IIBranch;
1481 bit isTerminator = 1;
1482 bit hasDelaySlot = 1;
1483 list<Register> Defs = [AT];
1486 class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1487 RegisterOperand ROWD, RegisterOperand ROS,
1488 InstrItinClass itin = NoItinerary> {
1489 dag OutOperandList = (outs ROWD:$wd);
1490 dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, uimm6:$n);
1491 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs");
1492 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
1495 InstrItinClass Itinerary = itin;
1496 string Constraints = "$wd = $wd_in";
1499 class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
1500 RegisterOperand ROWD, RegisterOperand ROFS> :
1501 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, uimm6:$n, ROFS:$fs),
1502 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs,
1504 bit usesCustomInserter = 1;
1505 string Constraints = "$wd = $wd_in";
1508 class MSA_INSERT_VIDX_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
1509 RegisterOperand ROWD, RegisterOperand ROFS> :
1510 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, GPR32Opnd:$n, ROFS:$fs),
1511 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs,
1513 bit usesCustomInserter = 1;
1514 string Constraints = "$wd = $wd_in";
1517 class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1518 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1519 InstrItinClass itin = NoItinerary> {
1520 dag OutOperandList = (outs ROWD:$wd);
1521 dag InOperandList = (ins ROWD:$wd_in, uimm6:$n, ROWS:$ws, uimmz:$n2);
1522 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[$n2]");
1523 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
1527 InstrItinClass Itinerary = itin;
1528 string Constraints = "$wd = $wd_in";
1531 class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1532 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1533 RegisterOperand ROWT = ROWD,
1534 InstrItinClass itin = NoItinerary> {
1535 dag OutOperandList = (outs ROWD:$wd);
1536 dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1537 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1538 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1539 InstrItinClass Itinerary = itin;
1542 class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm,
1543 RegisterOperand ROWD,
1544 RegisterOperand ROWS = ROWD,
1545 InstrItinClass itin = NoItinerary> {
1546 dag OutOperandList = (outs ROWD:$wd);
1547 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n);
1548 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1549 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws,
1551 InstrItinClass Itinerary = itin;
1554 class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD,
1555 RegisterOperand ROWS = ROWD,
1556 RegisterOperand ROWT = ROWD> :
1557 MSAPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt),
1558 [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>;
1560 class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>,
1562 class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>,
1564 class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>,
1566 class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>,
1569 class ADDS_A_B_DESC : MSA_3R_DESC_BASE<"adds_a.b", int_mips_adds_a_b,
1570 MSA128BOpnd>, IsCommutable;
1571 class ADDS_A_H_DESC : MSA_3R_DESC_BASE<"adds_a.h", int_mips_adds_a_h,
1572 MSA128HOpnd>, IsCommutable;
1573 class ADDS_A_W_DESC : MSA_3R_DESC_BASE<"adds_a.w", int_mips_adds_a_w,
1574 MSA128WOpnd>, IsCommutable;
1575 class ADDS_A_D_DESC : MSA_3R_DESC_BASE<"adds_a.d", int_mips_adds_a_d,
1576 MSA128DOpnd>, IsCommutable;
1578 class ADDS_S_B_DESC : MSA_3R_DESC_BASE<"adds_s.b", int_mips_adds_s_b,
1579 MSA128BOpnd>, IsCommutable;
1580 class ADDS_S_H_DESC : MSA_3R_DESC_BASE<"adds_s.h", int_mips_adds_s_h,
1581 MSA128HOpnd>, IsCommutable;
1582 class ADDS_S_W_DESC : MSA_3R_DESC_BASE<"adds_s.w", int_mips_adds_s_w,
1583 MSA128WOpnd>, IsCommutable;
1584 class ADDS_S_D_DESC : MSA_3R_DESC_BASE<"adds_s.d", int_mips_adds_s_d,
1585 MSA128DOpnd>, IsCommutable;
1587 class ADDS_U_B_DESC : MSA_3R_DESC_BASE<"adds_u.b", int_mips_adds_u_b,
1588 MSA128BOpnd>, IsCommutable;
1589 class ADDS_U_H_DESC : MSA_3R_DESC_BASE<"adds_u.h", int_mips_adds_u_h,
1590 MSA128HOpnd>, IsCommutable;
1591 class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w,
1592 MSA128WOpnd>, IsCommutable;
1593 class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d,
1594 MSA128DOpnd>, IsCommutable;
1596 class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable;
1597 class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable;
1598 class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable;
1599 class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable;
1601 class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5,
1603 class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5,
1605 class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5,
1607 class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5,
1610 class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>;
1611 class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128HOpnd>;
1612 class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128WOpnd>;
1613 class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128DOpnd>;
1615 class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8,
1618 class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b,
1620 class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h,
1622 class ASUB_S_W_DESC : MSA_3R_DESC_BASE<"asub_s.w", int_mips_asub_s_w,
1624 class ASUB_S_D_DESC : MSA_3R_DESC_BASE<"asub_s.d", int_mips_asub_s_d,
1627 class ASUB_U_B_DESC : MSA_3R_DESC_BASE<"asub_u.b", int_mips_asub_u_b,
1629 class ASUB_U_H_DESC : MSA_3R_DESC_BASE<"asub_u.h", int_mips_asub_u_h,
1631 class ASUB_U_W_DESC : MSA_3R_DESC_BASE<"asub_u.w", int_mips_asub_u_w,
1633 class ASUB_U_D_DESC : MSA_3R_DESC_BASE<"asub_u.d", int_mips_asub_u_d,
1636 class AVE_S_B_DESC : MSA_3R_DESC_BASE<"ave_s.b", int_mips_ave_s_b, MSA128BOpnd>,
1638 class AVE_S_H_DESC : MSA_3R_DESC_BASE<"ave_s.h", int_mips_ave_s_h, MSA128HOpnd>,
1640 class AVE_S_W_DESC : MSA_3R_DESC_BASE<"ave_s.w", int_mips_ave_s_w, MSA128WOpnd>,
1642 class AVE_S_D_DESC : MSA_3R_DESC_BASE<"ave_s.d", int_mips_ave_s_d, MSA128DOpnd>,
1645 class AVE_U_B_DESC : MSA_3R_DESC_BASE<"ave_u.b", int_mips_ave_u_b, MSA128BOpnd>,
1647 class AVE_U_H_DESC : MSA_3R_DESC_BASE<"ave_u.h", int_mips_ave_u_h, MSA128HOpnd>,
1649 class AVE_U_W_DESC : MSA_3R_DESC_BASE<"ave_u.w", int_mips_ave_u_w, MSA128WOpnd>,
1651 class AVE_U_D_DESC : MSA_3R_DESC_BASE<"ave_u.d", int_mips_ave_u_d, MSA128DOpnd>,
1654 class AVER_S_B_DESC : MSA_3R_DESC_BASE<"aver_s.b", int_mips_aver_s_b,
1655 MSA128BOpnd>, IsCommutable;
1656 class AVER_S_H_DESC : MSA_3R_DESC_BASE<"aver_s.h", int_mips_aver_s_h,
1657 MSA128HOpnd>, IsCommutable;
1658 class AVER_S_W_DESC : MSA_3R_DESC_BASE<"aver_s.w", int_mips_aver_s_w,
1659 MSA128WOpnd>, IsCommutable;
1660 class AVER_S_D_DESC : MSA_3R_DESC_BASE<"aver_s.d", int_mips_aver_s_d,
1661 MSA128DOpnd>, IsCommutable;
1663 class AVER_U_B_DESC : MSA_3R_DESC_BASE<"aver_u.b", int_mips_aver_u_b,
1664 MSA128BOpnd>, IsCommutable;
1665 class AVER_U_H_DESC : MSA_3R_DESC_BASE<"aver_u.h", int_mips_aver_u_h,
1666 MSA128HOpnd>, IsCommutable;
1667 class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w,
1668 MSA128WOpnd>, IsCommutable;
1669 class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d,
1670 MSA128DOpnd>, IsCommutable;
1672 class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", vbclr_b, MSA128BOpnd>;
1673 class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", vbclr_h, MSA128HOpnd>;
1674 class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", vbclr_w, MSA128WOpnd>;
1675 class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", vbclr_d, MSA128DOpnd>;
1677 class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", and, vsplat_uimm_inv_pow2,
1679 class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", and, vsplat_uimm_inv_pow2,
1681 class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", and, vsplat_uimm_inv_pow2,
1683 class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", and, vsplat_uimm_inv_pow2,
1686 class BINSL_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.b", int_mips_binsl_b,
1688 class BINSL_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.h", int_mips_binsl_h,
1690 class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w,
1692 class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d,
1695 class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, MSA128BOpnd>;
1696 class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, MSA128HOpnd>;
1697 class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, MSA128WOpnd>;
1698 class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, MSA128DOpnd>;
1700 class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b,
1702 class BINSR_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.h", int_mips_binsr_h,
1704 class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w,
1706 class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d,
1709 class BINSRI_B_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, MSA128BOpnd>;
1710 class BINSRI_H_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, MSA128HOpnd>;
1711 class BINSRI_W_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, MSA128WOpnd>;
1712 class BINSRI_D_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, MSA128DOpnd>;
1715 dag OutOperandList = (outs MSA128BOpnd:$wd);
1716 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1718 string AsmString = "bmnz.v\t$wd, $ws, $wt";
1719 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
1721 MSA128BOpnd:$wd_in))];
1722 InstrItinClass Itinerary = NoItinerary;
1723 string Constraints = "$wd = $wd_in";
1726 class BMNZI_B_DESC {
1727 dag OutOperandList = (outs MSA128BOpnd:$wd);
1728 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1730 string AsmString = "bmnzi.b\t$wd, $ws, $u8";
1731 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
1733 MSA128BOpnd:$wd_in))];
1734 InstrItinClass Itinerary = NoItinerary;
1735 string Constraints = "$wd = $wd_in";
1739 dag OutOperandList = (outs MSA128BOpnd:$wd);
1740 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1742 string AsmString = "bmz.v\t$wd, $ws, $wt";
1743 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
1746 InstrItinClass Itinerary = NoItinerary;
1747 string Constraints = "$wd = $wd_in";
1751 dag OutOperandList = (outs MSA128BOpnd:$wd);
1752 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1754 string AsmString = "bmzi.b\t$wd, $ws, $u8";
1755 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
1758 InstrItinClass Itinerary = NoItinerary;
1759 string Constraints = "$wd = $wd_in";
1762 class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg_b, MSA128BOpnd>;
1763 class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg_h, MSA128HOpnd>;
1764 class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg_w, MSA128WOpnd>;
1765 class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg_d, MSA128DOpnd>;
1767 class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", xor, vsplat_uimm_pow2,
1769 class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", xor, vsplat_uimm_pow2,
1771 class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", xor, vsplat_uimm_pow2,
1773 class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", xor, vsplat_uimm_pow2,
1776 class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>;
1777 class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>;
1778 class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>;
1779 class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>;
1781 class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>;
1784 dag OutOperandList = (outs MSA128BOpnd:$wd);
1785 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1787 string AsmString = "bsel.v\t$wd, $ws, $wt";
1788 // Note that vselect and BSEL_V treat the condition operand the opposite way
1790 // (vselect cond, if_set, if_clear)
1791 // (BSEL_V cond, if_clear, if_set)
1792 list<dag> Pattern = [(set MSA128BOpnd:$wd,
1793 (vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$wt,
1795 InstrItinClass Itinerary = NoItinerary;
1796 string Constraints = "$wd = $wd_in";
1799 class BSELI_B_DESC {
1800 dag OutOperandList = (outs MSA128BOpnd:$wd);
1801 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1803 string AsmString = "bseli.b\t$wd, $ws, $u8";
1804 // Note that vselect and BSEL_V treat the condition operand the opposite way
1806 // (vselect cond, if_set, if_clear)
1807 // (BSEL_V cond, if_clear, if_set)
1808 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in,
1811 InstrItinClass Itinerary = NoItinerary;
1812 string Constraints = "$wd = $wd_in";
1815 class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", vbset_b, MSA128BOpnd>;
1816 class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", vbset_h, MSA128HOpnd>;
1817 class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", vbset_w, MSA128WOpnd>;
1818 class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", vbset_d, MSA128DOpnd>;
1820 class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", or, vsplat_uimm_pow2,
1822 class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", or, vsplat_uimm_pow2,
1824 class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", or, vsplat_uimm_pow2,
1826 class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", or, vsplat_uimm_pow2,
1829 class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>;
1830 class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>;
1831 class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>;
1832 class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>;
1834 class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>;
1836 class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>,
1838 class CEQ_H_DESC : MSA_3R_DESC_BASE<"ceq.h", vseteq_v8i16, MSA128HOpnd>,
1840 class CEQ_W_DESC : MSA_3R_DESC_BASE<"ceq.w", vseteq_v4i32, MSA128WOpnd>,
1842 class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq.d", vseteq_v2i64, MSA128DOpnd>,
1845 class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5,
1847 class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5,
1849 class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5,
1851 class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5,
1855 dag OutOperandList = (outs GPR32Opnd:$rd);
1856 dag InOperandList = (ins MSA128CROpnd:$cs);
1857 string AsmString = "cfcmsa\t$rd, $cs";
1858 InstrItinClass Itinerary = NoItinerary;
1859 bit hasSideEffects = 1;
1862 class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>;
1863 class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", vsetle_v8i16, MSA128HOpnd>;
1864 class CLE_S_W_DESC : MSA_3R_DESC_BASE<"cle_s.w", vsetle_v4i32, MSA128WOpnd>;
1865 class CLE_S_D_DESC : MSA_3R_DESC_BASE<"cle_s.d", vsetle_v2i64, MSA128DOpnd>;
1867 class CLE_U_B_DESC : MSA_3R_DESC_BASE<"cle_u.b", vsetule_v16i8, MSA128BOpnd>;
1868 class CLE_U_H_DESC : MSA_3R_DESC_BASE<"cle_u.h", vsetule_v8i16, MSA128HOpnd>;
1869 class CLE_U_W_DESC : MSA_3R_DESC_BASE<"cle_u.w", vsetule_v4i32, MSA128WOpnd>;
1870 class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>;
1872 class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8,
1873 vsplati8_simm5, MSA128BOpnd>;
1874 class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16,
1875 vsplati16_simm5, MSA128HOpnd>;
1876 class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32,
1877 vsplati32_simm5, MSA128WOpnd>;
1878 class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64,
1879 vsplati64_simm5, MSA128DOpnd>;
1881 class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8,
1882 vsplati8_uimm5, MSA128BOpnd>;
1883 class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16,
1884 vsplati16_uimm5, MSA128HOpnd>;
1885 class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32,
1886 vsplati32_uimm5, MSA128WOpnd>;
1887 class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64,
1888 vsplati64_uimm5, MSA128DOpnd>;
1890 class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>;
1891 class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>;
1892 class CLT_S_W_DESC : MSA_3R_DESC_BASE<"clt_s.w", vsetlt_v4i32, MSA128WOpnd>;
1893 class CLT_S_D_DESC : MSA_3R_DESC_BASE<"clt_s.d", vsetlt_v2i64, MSA128DOpnd>;
1895 class CLT_U_B_DESC : MSA_3R_DESC_BASE<"clt_u.b", vsetult_v16i8, MSA128BOpnd>;
1896 class CLT_U_H_DESC : MSA_3R_DESC_BASE<"clt_u.h", vsetult_v8i16, MSA128HOpnd>;
1897 class CLT_U_W_DESC : MSA_3R_DESC_BASE<"clt_u.w", vsetult_v4i32, MSA128WOpnd>;
1898 class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>;
1900 class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8,
1901 vsplati8_simm5, MSA128BOpnd>;
1902 class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16,
1903 vsplati16_simm5, MSA128HOpnd>;
1904 class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32,
1905 vsplati32_simm5, MSA128WOpnd>;
1906 class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64,
1907 vsplati64_simm5, MSA128DOpnd>;
1909 class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8,
1910 vsplati8_uimm5, MSA128BOpnd>;
1911 class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16,
1912 vsplati16_uimm5, MSA128HOpnd>;
1913 class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32,
1914 vsplati32_uimm5, MSA128WOpnd>;
1915 class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64,
1916 vsplati64_uimm5, MSA128DOpnd>;
1918 class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8,
1919 GPR32Opnd, MSA128BOpnd>;
1920 class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16,
1921 GPR32Opnd, MSA128HOpnd>;
1922 class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32,
1923 GPR32Opnd, MSA128WOpnd>;
1924 class COPY_S_D_DESC : MSA_COPY_DESC_BASE<"copy_s.d", vextract_sext_i64, v2i64,
1925 GPR64Opnd, MSA128DOpnd>;
1927 class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8,
1928 GPR32Opnd, MSA128BOpnd>;
1929 class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16,
1930 GPR32Opnd, MSA128HOpnd>;
1931 class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32,
1932 GPR32Opnd, MSA128WOpnd>;
1933 class COPY_U_D_DESC : MSA_COPY_DESC_BASE<"copy_u.d", vextract_zext_i64, v2i64,
1934 GPR64Opnd, MSA128DOpnd>;
1936 class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, FGR32,
1938 class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64, FGR64,
1942 dag OutOperandList = (outs);
1943 dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs);
1944 string AsmString = "ctcmsa\t$cd, $rs";
1945 InstrItinClass Itinerary = NoItinerary;
1946 bit hasSideEffects = 1;
1949 class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>;
1950 class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128HOpnd>;
1951 class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128WOpnd>;
1952 class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128DOpnd>;
1954 class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128BOpnd>;
1955 class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128HOpnd>;
1956 class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128WOpnd>;
1957 class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128DOpnd>;
1959 class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h,
1960 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1962 class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w,
1963 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1965 class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d,
1966 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1969 class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h,
1970 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1972 class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w,
1973 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1975 class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d,
1976 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1979 class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h,
1980 MSA128HOpnd, MSA128BOpnd,
1981 MSA128BOpnd>, IsCommutable;
1982 class DPADD_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.w", int_mips_dpadd_s_w,
1983 MSA128WOpnd, MSA128HOpnd,
1984 MSA128HOpnd>, IsCommutable;
1985 class DPADD_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.d", int_mips_dpadd_s_d,
1986 MSA128DOpnd, MSA128WOpnd,
1987 MSA128WOpnd>, IsCommutable;
1989 class DPADD_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.h", int_mips_dpadd_u_h,
1990 MSA128HOpnd, MSA128BOpnd,
1991 MSA128BOpnd>, IsCommutable;
1992 class DPADD_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.w", int_mips_dpadd_u_w,
1993 MSA128WOpnd, MSA128HOpnd,
1994 MSA128HOpnd>, IsCommutable;
1995 class DPADD_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.d", int_mips_dpadd_u_d,
1996 MSA128DOpnd, MSA128WOpnd,
1997 MSA128WOpnd>, IsCommutable;
1999 class DPSUB_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.h", int_mips_dpsub_s_h,
2000 MSA128HOpnd, MSA128BOpnd,
2002 class DPSUB_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.w", int_mips_dpsub_s_w,
2003 MSA128WOpnd, MSA128HOpnd,
2005 class DPSUB_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.d", int_mips_dpsub_s_d,
2006 MSA128DOpnd, MSA128WOpnd,
2009 class DPSUB_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.h", int_mips_dpsub_u_h,
2010 MSA128HOpnd, MSA128BOpnd,
2012 class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w,
2013 MSA128WOpnd, MSA128HOpnd,
2015 class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d,
2016 MSA128DOpnd, MSA128WOpnd,
2019 class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>,
2021 class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>,
2024 class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>,
2026 class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>,
2029 class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>,
2031 class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>,
2034 class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w,
2036 class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d,
2039 class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>;
2040 class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>;
2042 class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>;
2043 class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>;
2045 class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>,
2047 class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>,
2050 class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>,
2052 class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>,
2055 class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>,
2057 class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>,
2060 class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>,
2062 class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>,
2065 class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>,
2067 class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>,
2070 class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>,
2072 class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>,
2075 class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>,
2077 class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>,
2080 class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>;
2081 class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>;
2083 class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h,
2084 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
2085 class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w,
2086 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
2088 // The fexp2.df instruction multiplies the first operand by 2 to the power of
2089 // the second operand. We therefore need a pseudo-insn in order to invent the
2090 // 1.0 when we only need to match ISD::FEXP2.
2091 class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>;
2092 class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>;
2093 let usesCustomInserter = 1 in {
2094 class FEXP2_W_1_PSEUDO_DESC :
2095 MSAPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws),
2096 [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>;
2097 class FEXP2_D_1_PSEUDO_DESC :
2098 MSAPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws),
2099 [(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>;
2102 class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w,
2103 MSA128WOpnd, MSA128HOpnd>;
2104 class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d,
2105 MSA128DOpnd, MSA128WOpnd>;
2107 class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w,
2108 MSA128WOpnd, MSA128HOpnd>;
2109 class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d,
2110 MSA128DOpnd, MSA128WOpnd>;
2112 class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>;
2113 class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>;
2115 class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>;
2116 class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>;
2118 class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w,
2119 MSA128WOpnd, MSA128HOpnd>;
2120 class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d,
2121 MSA128DOpnd, MSA128WOpnd>;
2123 class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w,
2124 MSA128WOpnd, MSA128HOpnd>;
2125 class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d,
2126 MSA128DOpnd, MSA128WOpnd>;
2128 class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8,
2129 MSA128BOpnd, GPR32Opnd>;
2130 class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16,
2131 MSA128HOpnd, GPR32Opnd>;
2132 class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32,
2133 MSA128WOpnd, GPR32Opnd>;
2134 class FILL_D_DESC : MSA_2R_FILL_DESC_BASE<"fill.d", v2i64, vsplati64,
2135 MSA128DOpnd, GPR64Opnd>;
2137 class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v4f32, vsplatf32, MSA128W,
2139 class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v2f64, vsplatf64, MSA128D,
2142 class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>;
2143 class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>;
2145 class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>;
2146 class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>;
2148 class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>;
2149 class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>;
2151 class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w,
2153 class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d,
2156 class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>;
2157 class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>;
2159 class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w,
2161 class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d,
2164 class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", fms, MSA128WOpnd>;
2165 class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", fms, MSA128DOpnd>;
2167 class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>;
2168 class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>;
2170 class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>;
2171 class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>;
2173 class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>;
2174 class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>;
2176 class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w,
2178 class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d,
2181 class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>;
2182 class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>;
2184 class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>;
2185 class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>;
2187 class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>;
2188 class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>;
2190 class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>;
2191 class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>;
2193 class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>;
2194 class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>;
2196 class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>;
2197 class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>;
2199 class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>;
2200 class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>;
2202 class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>;
2203 class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>;
2205 class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w,
2207 class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d,
2210 class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w,
2212 class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d,
2215 class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w,
2217 class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d,
2220 class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w,
2222 class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d,
2225 class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w,
2227 class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d,
2230 class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w,
2232 class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d,
2235 class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w,
2237 class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d,
2240 class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h,
2241 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
2242 class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w,
2243 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
2245 class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint,
2247 class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint,
2250 class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint,
2252 class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint,
2255 class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h,
2256 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2257 class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w,
2258 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2259 class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d,
2260 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2262 class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h,
2263 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2264 class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w,
2265 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2266 class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d,
2267 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2269 class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h,
2270 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2271 class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w,
2272 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2273 class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d,
2274 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2276 class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h,
2277 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2278 class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w,
2279 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2280 class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d,
2281 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2283 class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", MipsILVEV, MSA128BOpnd>;
2284 class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", MipsILVEV, MSA128HOpnd>;
2285 class ILVEV_W_DESC : MSA_3R_DESC_BASE<"ilvev.w", MipsILVEV, MSA128WOpnd>;
2286 class ILVEV_D_DESC : MSA_3R_DESC_BASE<"ilvev.d", MipsILVEV, MSA128DOpnd>;
2288 class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>;
2289 class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>;
2290 class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>;
2291 class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>;
2293 class ILVOD_B_DESC : MSA_3R_DESC_BASE<"ilvod.b", MipsILVOD, MSA128BOpnd>;
2294 class ILVOD_H_DESC : MSA_3R_DESC_BASE<"ilvod.h", MipsILVOD, MSA128HOpnd>;
2295 class ILVOD_W_DESC : MSA_3R_DESC_BASE<"ilvod.w", MipsILVOD, MSA128WOpnd>;
2296 class ILVOD_D_DESC : MSA_3R_DESC_BASE<"ilvod.d", MipsILVOD, MSA128DOpnd>;
2298 class ILVR_B_DESC : MSA_3R_DESC_BASE<"ilvr.b", MipsILVR, MSA128BOpnd>;
2299 class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>;
2300 class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>;
2301 class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>;
2303 class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8,
2304 MSA128BOpnd, GPR32Opnd>;
2305 class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16,
2306 MSA128HOpnd, GPR32Opnd>;
2307 class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32,
2308 MSA128WOpnd, GPR32Opnd>;
2309 class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64,
2310 MSA128DOpnd, GPR64Opnd>;
2312 class INSERT_B_VIDX_PSEUDO_DESC :
2313 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd>;
2314 class INSERT_H_VIDX_PSEUDO_DESC :
2315 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd>;
2316 class INSERT_W_VIDX_PSEUDO_DESC :
2317 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd>;
2318 class INSERT_D_VIDX_PSEUDO_DESC :
2319 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd>;
2321 class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32,
2322 MSA128WOpnd, FGR32Opnd>;
2323 class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64,
2324 MSA128DOpnd, FGR64Opnd>;
2326 class INSERT_FW_VIDX_PSEUDO_DESC :
2327 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd>;
2328 class INSERT_FD_VIDX_PSEUDO_DESC :
2329 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd>;
2331 class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8,
2333 class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", insve_v8i16,
2335 class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", insve_v4i32,
2337 class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64,
2340 class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2341 ValueType TyNode, RegisterOperand ROWD,
2342 Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10,
2343 InstrItinClass itin = NoItinerary> {
2344 dag OutOperandList = (outs ROWD:$wd);
2345 dag InOperandList = (ins MemOpnd:$addr);
2346 string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2347 list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))];
2348 InstrItinClass Itinerary = itin;
2349 string DecoderMethod = "DecodeMSA128Mem";
2352 class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd>;
2353 class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd>;
2354 class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd>;
2355 class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd>;
2357 class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>;
2358 class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>;
2359 class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>;
2360 class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>;
2362 class LSA_DESC_BASE<string instr_asm, RegisterOperand RORD,
2363 RegisterOperand RORS = RORD, RegisterOperand RORT = RORD,
2364 InstrItinClass itin = NoItinerary > {
2365 dag OutOperandList = (outs RORD:$rd);
2366 dag InOperandList = (ins RORS:$rs, RORT:$rt, LSAImm:$sa);
2367 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $sa");
2368 list<dag> Pattern = [(set RORD:$rd, (add RORT:$rt,
2370 immZExt2Lsa:$sa)))];
2371 InstrItinClass Itinerary = itin;
2374 class LSA_DESC : LSA_DESC_BASE<"lsa", GPR32Opnd>;
2375 class DLSA_DESC : LSA_DESC_BASE<"dlsa", GPR64Opnd>;
2377 class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h,
2379 class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w,
2382 class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h,
2384 class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w,
2387 class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", muladd, MSA128BOpnd>;
2388 class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", muladd, MSA128HOpnd>;
2389 class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", muladd, MSA128WOpnd>;
2390 class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", muladd, MSA128DOpnd>;
2392 class MAX_A_B_DESC : MSA_3R_DESC_BASE<"max_a.b", int_mips_max_a_b, MSA128BOpnd>;
2393 class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>;
2394 class MAX_A_W_DESC : MSA_3R_DESC_BASE<"max_a.w", int_mips_max_a_w, MSA128WOpnd>;
2395 class MAX_A_D_DESC : MSA_3R_DESC_BASE<"max_a.d", int_mips_max_a_d, MSA128DOpnd>;
2397 class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", MipsVSMax, MSA128BOpnd>;
2398 class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", MipsVSMax, MSA128HOpnd>;
2399 class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", MipsVSMax, MSA128WOpnd>;
2400 class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", MipsVSMax, MSA128DOpnd>;
2402 class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", MipsVUMax, MSA128BOpnd>;
2403 class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", MipsVUMax, MSA128HOpnd>;
2404 class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", MipsVUMax, MSA128WOpnd>;
2405 class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", MipsVUMax, MSA128DOpnd>;
2407 class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", MipsVSMax, vsplati8_simm5,
2409 class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", MipsVSMax, vsplati16_simm5,
2411 class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", MipsVSMax, vsplati32_simm5,
2413 class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", MipsVSMax, vsplati64_simm5,
2416 class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", MipsVUMax, vsplati8_uimm5,
2418 class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", MipsVUMax, vsplati16_uimm5,
2420 class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", MipsVUMax, vsplati32_uimm5,
2422 class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", MipsVUMax, vsplati64_uimm5,
2425 class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>;
2426 class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>;
2427 class MIN_A_W_DESC : MSA_3R_DESC_BASE<"min_a.w", int_mips_min_a_w, MSA128WOpnd>;
2428 class MIN_A_D_DESC : MSA_3R_DESC_BASE<"min_a.d", int_mips_min_a_d, MSA128DOpnd>;
2430 class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", MipsVSMin, MSA128BOpnd>;
2431 class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", MipsVSMin, MSA128HOpnd>;
2432 class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", MipsVSMin, MSA128WOpnd>;
2433 class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", MipsVSMin, MSA128DOpnd>;
2435 class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", MipsVUMin, MSA128BOpnd>;
2436 class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", MipsVUMin, MSA128HOpnd>;
2437 class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", MipsVUMin, MSA128WOpnd>;
2438 class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", MipsVUMin, MSA128DOpnd>;
2440 class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", MipsVSMin, vsplati8_simm5,
2442 class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", MipsVSMin, vsplati16_simm5,
2444 class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", MipsVSMin, vsplati32_simm5,
2446 class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", MipsVSMin, vsplati64_simm5,
2449 class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", MipsVUMin, vsplati8_uimm5,
2451 class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", MipsVUMin, vsplati16_uimm5,
2453 class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", MipsVUMin, vsplati32_uimm5,
2455 class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", MipsVUMin, vsplati64_uimm5,
2458 class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", srem, MSA128BOpnd>;
2459 class MOD_S_H_DESC : MSA_3R_DESC_BASE<"mod_s.h", srem, MSA128HOpnd>;
2460 class MOD_S_W_DESC : MSA_3R_DESC_BASE<"mod_s.w", srem, MSA128WOpnd>;
2461 class MOD_S_D_DESC : MSA_3R_DESC_BASE<"mod_s.d", srem, MSA128DOpnd>;
2463 class MOD_U_B_DESC : MSA_3R_DESC_BASE<"mod_u.b", urem, MSA128BOpnd>;
2464 class MOD_U_H_DESC : MSA_3R_DESC_BASE<"mod_u.h", urem, MSA128HOpnd>;
2465 class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", urem, MSA128WOpnd>;
2466 class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", urem, MSA128DOpnd>;
2469 dag OutOperandList = (outs MSA128BOpnd:$wd);
2470 dag InOperandList = (ins MSA128BOpnd:$ws);
2471 string AsmString = "move.v\t$wd, $ws";
2472 list<dag> Pattern = [];
2473 InstrItinClass Itinerary = NoItinerary;
2476 class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h,
2478 class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w,
2481 class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h,
2483 class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w,
2486 class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", mulsub, MSA128BOpnd>;
2487 class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", mulsub, MSA128HOpnd>;
2488 class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", mulsub, MSA128WOpnd>;
2489 class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", mulsub, MSA128DOpnd>;
2491 class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h,
2493 class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w,
2496 class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h,
2498 class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w,
2501 class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128BOpnd>;
2502 class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128HOpnd>;
2503 class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", mul, MSA128WOpnd>;
2504 class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", mul, MSA128DOpnd>;
2506 class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>;
2507 class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>;
2508 class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>;
2509 class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>;
2511 class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", ctlz, MSA128BOpnd>;
2512 class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128HOpnd>;
2513 class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128WOpnd>;
2514 class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128DOpnd>;
2516 class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128BOpnd>;
2517 class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128HOpnd>;
2518 class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128WOpnd>;
2519 class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128DOpnd>;
2521 class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8,
2524 class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128BOpnd>;
2525 class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128HOpnd>;
2526 class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128WOpnd>;
2527 class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128DOpnd>;
2529 class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>;
2531 class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128BOpnd>;
2532 class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128HOpnd>;
2533 class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", MipsPCKEV, MSA128WOpnd>;
2534 class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", MipsPCKEV, MSA128DOpnd>;
2536 class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", MipsPCKOD, MSA128BOpnd>;
2537 class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", MipsPCKOD, MSA128HOpnd>;
2538 class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>;
2539 class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>;
2541 class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>;
2542 class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>;
2543 class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>;
2544 class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>;
2546 class SAT_S_B_DESC : MSA_BIT_B_X_DESC_BASE<"sat_s.b", int_mips_sat_s_b,
2548 class SAT_S_H_DESC : MSA_BIT_H_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h,
2550 class SAT_S_W_DESC : MSA_BIT_W_X_DESC_BASE<"sat_s.w", int_mips_sat_s_w,
2552 class SAT_S_D_DESC : MSA_BIT_D_X_DESC_BASE<"sat_s.d", int_mips_sat_s_d,
2555 class SAT_U_B_DESC : MSA_BIT_B_X_DESC_BASE<"sat_u.b", int_mips_sat_u_b,
2557 class SAT_U_H_DESC : MSA_BIT_H_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h,
2559 class SAT_U_W_DESC : MSA_BIT_W_X_DESC_BASE<"sat_u.w", int_mips_sat_u_w,
2561 class SAT_U_D_DESC : MSA_BIT_D_X_DESC_BASE<"sat_u.d", int_mips_sat_u_d,
2564 class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>;
2565 class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>;
2566 class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>;
2568 class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>;
2569 class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>;
2570 class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>;
2571 class SLD_D_DESC : MSA_3R_SLD_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>;
2573 class SLDI_B_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.b", int_mips_sldi_b,
2575 class SLDI_H_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.h", int_mips_sldi_h,
2577 class SLDI_W_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.w", int_mips_sldi_w,
2579 class SLDI_D_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.d", int_mips_sldi_d,
2582 class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128BOpnd>;
2583 class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128HOpnd>;
2584 class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>;
2585 class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>;
2587 class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3,
2589 class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4,
2591 class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5,
2593 class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6,
2596 class SPLAT_B_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.b", vsplati8_elt,
2598 class SPLAT_H_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.h", vsplati16_elt,
2600 class SPLAT_W_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.w", vsplati32_elt,
2602 class SPLAT_D_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.d", vsplati64_elt,
2605 class SPLATI_B_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.b", vsplati8_uimm4,
2607 class SPLATI_H_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.h", vsplati16_uimm3,
2609 class SPLATI_W_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.w", vsplati32_uimm2,
2611 class SPLATI_D_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.d", vsplati64_uimm1,
2614 class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>;
2615 class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>;
2616 class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>;
2617 class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>;
2619 class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3,
2621 class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4,
2623 class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5,
2625 class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6,
2628 class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>;
2629 class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>;
2630 class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>;
2631 class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>;
2633 class SRARI_B_DESC : MSA_BIT_B_X_DESC_BASE<"srari.b", int_mips_srari_b,
2635 class SRARI_H_DESC : MSA_BIT_H_X_DESC_BASE<"srari.h", int_mips_srari_h,
2637 class SRARI_W_DESC : MSA_BIT_W_X_DESC_BASE<"srari.w", int_mips_srari_w,
2639 class SRARI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srari.d", int_mips_srari_d,
2642 class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>;
2643 class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>;
2644 class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>;
2645 class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>;
2647 class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3,
2649 class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4,
2651 class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5,
2653 class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6,
2656 class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>;
2657 class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>;
2658 class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>;
2659 class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>;
2661 class SRLRI_B_DESC : MSA_BIT_B_X_DESC_BASE<"srlri.b", int_mips_srlri_b,
2663 class SRLRI_H_DESC : MSA_BIT_H_X_DESC_BASE<"srlri.h", int_mips_srlri_h,
2665 class SRLRI_W_DESC : MSA_BIT_W_X_DESC_BASE<"srlri.w", int_mips_srlri_w,
2667 class SRLRI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srlri.d", int_mips_srlri_d,
2670 class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2671 ValueType TyNode, RegisterOperand ROWD,
2672 Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10,
2673 InstrItinClass itin = NoItinerary> {
2674 dag OutOperandList = (outs);
2675 dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr);
2676 string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2677 list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)];
2678 InstrItinClass Itinerary = itin;
2679 string DecoderMethod = "DecodeMSA128Mem";
2682 class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd>;
2683 class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd>;
2684 class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd>;
2685 class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd>;
2687 class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b,
2689 class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h,
2691 class SUBS_S_W_DESC : MSA_3R_DESC_BASE<"subs_s.w", int_mips_subs_s_w,
2693 class SUBS_S_D_DESC : MSA_3R_DESC_BASE<"subs_s.d", int_mips_subs_s_d,
2696 class SUBS_U_B_DESC : MSA_3R_DESC_BASE<"subs_u.b", int_mips_subs_u_b,
2698 class SUBS_U_H_DESC : MSA_3R_DESC_BASE<"subs_u.h", int_mips_subs_u_h,
2700 class SUBS_U_W_DESC : MSA_3R_DESC_BASE<"subs_u.w", int_mips_subs_u_w,
2702 class SUBS_U_D_DESC : MSA_3R_DESC_BASE<"subs_u.d", int_mips_subs_u_d,
2705 class SUBSUS_U_B_DESC : MSA_3R_DESC_BASE<"subsus_u.b", int_mips_subsus_u_b,
2707 class SUBSUS_U_H_DESC : MSA_3R_DESC_BASE<"subsus_u.h", int_mips_subsus_u_h,
2709 class SUBSUS_U_W_DESC : MSA_3R_DESC_BASE<"subsus_u.w", int_mips_subsus_u_w,
2711 class SUBSUS_U_D_DESC : MSA_3R_DESC_BASE<"subsus_u.d", int_mips_subsus_u_d,
2714 class SUBSUU_S_B_DESC : MSA_3R_DESC_BASE<"subsuu_s.b", int_mips_subsuu_s_b,
2716 class SUBSUU_S_H_DESC : MSA_3R_DESC_BASE<"subsuu_s.h", int_mips_subsuu_s_h,
2718 class SUBSUU_S_W_DESC : MSA_3R_DESC_BASE<"subsuu_s.w", int_mips_subsuu_s_w,
2720 class SUBSUU_S_D_DESC : MSA_3R_DESC_BASE<"subsuu_s.d", int_mips_subsuu_s_d,
2723 class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", sub, MSA128BOpnd>;
2724 class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", sub, MSA128HOpnd>;
2725 class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128WOpnd>;
2726 class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128DOpnd>;
2728 class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5,
2730 class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5,
2732 class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5,
2734 class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5,
2737 class VSHF_B_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.b", MSA128BOpnd>;
2738 class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>;
2739 class VSHF_W_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.w", MSA128WOpnd>;
2740 class VSHF_D_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.d", MSA128DOpnd>;
2742 class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128BOpnd>;
2743 class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128HOpnd>;
2744 class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128WOpnd>;
2745 class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128DOpnd>;
2747 class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8,
2750 // Instruction defs.
2751 def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC;
2752 def ADD_A_H : ADD_A_H_ENC, ADD_A_H_DESC;
2753 def ADD_A_W : ADD_A_W_ENC, ADD_A_W_DESC;
2754 def ADD_A_D : ADD_A_D_ENC, ADD_A_D_DESC;
2756 def ADDS_A_B : ADDS_A_B_ENC, ADDS_A_B_DESC;
2757 def ADDS_A_H : ADDS_A_H_ENC, ADDS_A_H_DESC;
2758 def ADDS_A_W : ADDS_A_W_ENC, ADDS_A_W_DESC;
2759 def ADDS_A_D : ADDS_A_D_ENC, ADDS_A_D_DESC;
2761 def ADDS_S_B : ADDS_S_B_ENC, ADDS_S_B_DESC;
2762 def ADDS_S_H : ADDS_S_H_ENC, ADDS_S_H_DESC;
2763 def ADDS_S_W : ADDS_S_W_ENC, ADDS_S_W_DESC;
2764 def ADDS_S_D : ADDS_S_D_ENC, ADDS_S_D_DESC;
2766 def ADDS_U_B : ADDS_U_B_ENC, ADDS_U_B_DESC;
2767 def ADDS_U_H : ADDS_U_H_ENC, ADDS_U_H_DESC;
2768 def ADDS_U_W : ADDS_U_W_ENC, ADDS_U_W_DESC;
2769 def ADDS_U_D : ADDS_U_D_ENC, ADDS_U_D_DESC;
2771 def ADDV_B : ADDV_B_ENC, ADDV_B_DESC;
2772 def ADDV_H : ADDV_H_ENC, ADDV_H_DESC;
2773 def ADDV_W : ADDV_W_ENC, ADDV_W_DESC;
2774 def ADDV_D : ADDV_D_ENC, ADDV_D_DESC;
2776 def ADDVI_B : ADDVI_B_ENC, ADDVI_B_DESC;
2777 def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC;
2778 def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC;
2779 def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC;
2781 def AND_V : AND_V_ENC, AND_V_DESC;
2782 def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC,
2783 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2786 def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC,
2787 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2790 def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC,
2791 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2795 def ANDI_B : ANDI_B_ENC, ANDI_B_DESC;
2797 def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC;
2798 def ASUB_S_H : ASUB_S_H_ENC, ASUB_S_H_DESC;
2799 def ASUB_S_W : ASUB_S_W_ENC, ASUB_S_W_DESC;
2800 def ASUB_S_D : ASUB_S_D_ENC, ASUB_S_D_DESC;
2802 def ASUB_U_B : ASUB_U_B_ENC, ASUB_U_B_DESC;
2803 def ASUB_U_H : ASUB_U_H_ENC, ASUB_U_H_DESC;
2804 def ASUB_U_W : ASUB_U_W_ENC, ASUB_U_W_DESC;
2805 def ASUB_U_D : ASUB_U_D_ENC, ASUB_U_D_DESC;
2807 def AVE_S_B : AVE_S_B_ENC, AVE_S_B_DESC;
2808 def AVE_S_H : AVE_S_H_ENC, AVE_S_H_DESC;
2809 def AVE_S_W : AVE_S_W_ENC, AVE_S_W_DESC;
2810 def AVE_S_D : AVE_S_D_ENC, AVE_S_D_DESC;
2812 def AVE_U_B : AVE_U_B_ENC, AVE_U_B_DESC;
2813 def AVE_U_H : AVE_U_H_ENC, AVE_U_H_DESC;
2814 def AVE_U_W : AVE_U_W_ENC, AVE_U_W_DESC;
2815 def AVE_U_D : AVE_U_D_ENC, AVE_U_D_DESC;
2817 def AVER_S_B : AVER_S_B_ENC, AVER_S_B_DESC;
2818 def AVER_S_H : AVER_S_H_ENC, AVER_S_H_DESC;
2819 def AVER_S_W : AVER_S_W_ENC, AVER_S_W_DESC;
2820 def AVER_S_D : AVER_S_D_ENC, AVER_S_D_DESC;
2822 def AVER_U_B : AVER_U_B_ENC, AVER_U_B_DESC;
2823 def AVER_U_H : AVER_U_H_ENC, AVER_U_H_DESC;
2824 def AVER_U_W : AVER_U_W_ENC, AVER_U_W_DESC;
2825 def AVER_U_D : AVER_U_D_ENC, AVER_U_D_DESC;
2827 def BCLR_B : BCLR_B_ENC, BCLR_B_DESC;
2828 def BCLR_H : BCLR_H_ENC, BCLR_H_DESC;
2829 def BCLR_W : BCLR_W_ENC, BCLR_W_DESC;
2830 def BCLR_D : BCLR_D_ENC, BCLR_D_DESC;
2832 def BCLRI_B : BCLRI_B_ENC, BCLRI_B_DESC;
2833 def BCLRI_H : BCLRI_H_ENC, BCLRI_H_DESC;
2834 def BCLRI_W : BCLRI_W_ENC, BCLRI_W_DESC;
2835 def BCLRI_D : BCLRI_D_ENC, BCLRI_D_DESC;
2837 def BINSL_B : BINSL_B_ENC, BINSL_B_DESC;
2838 def BINSL_H : BINSL_H_ENC, BINSL_H_DESC;
2839 def BINSL_W : BINSL_W_ENC, BINSL_W_DESC;
2840 def BINSL_D : BINSL_D_ENC, BINSL_D_DESC;
2842 def BINSLI_B : BINSLI_B_ENC, BINSLI_B_DESC;
2843 def BINSLI_H : BINSLI_H_ENC, BINSLI_H_DESC;
2844 def BINSLI_W : BINSLI_W_ENC, BINSLI_W_DESC;
2845 def BINSLI_D : BINSLI_D_ENC, BINSLI_D_DESC;
2847 def BINSR_B : BINSR_B_ENC, BINSR_B_DESC;
2848 def BINSR_H : BINSR_H_ENC, BINSR_H_DESC;
2849 def BINSR_W : BINSR_W_ENC, BINSR_W_DESC;
2850 def BINSR_D : BINSR_D_ENC, BINSR_D_DESC;
2852 def BINSRI_B : BINSRI_B_ENC, BINSRI_B_DESC;
2853 def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC;
2854 def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC;
2855 def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC;
2857 def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC;
2859 def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC;
2861 def BMZ_V : BMZ_V_ENC, BMZ_V_DESC;
2863 def BMZI_B : BMZI_B_ENC, BMZI_B_DESC;
2865 def BNEG_B : BNEG_B_ENC, BNEG_B_DESC;
2866 def BNEG_H : BNEG_H_ENC, BNEG_H_DESC;
2867 def BNEG_W : BNEG_W_ENC, BNEG_W_DESC;
2868 def BNEG_D : BNEG_D_ENC, BNEG_D_DESC;
2870 def BNEGI_B : BNEGI_B_ENC, BNEGI_B_DESC;
2871 def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC;
2872 def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC;
2873 def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC;
2875 def BNZ_B : BNZ_B_ENC, BNZ_B_DESC;
2876 def BNZ_H : BNZ_H_ENC, BNZ_H_DESC;
2877 def BNZ_W : BNZ_W_ENC, BNZ_W_DESC;
2878 def BNZ_D : BNZ_D_ENC, BNZ_D_DESC;
2880 def BNZ_V : BNZ_V_ENC, BNZ_V_DESC;
2882 def BSEL_V : BSEL_V_ENC, BSEL_V_DESC;
2884 class MSA_BSEL_PSEUDO_BASE<RegisterOperand RO, ValueType Ty> :
2885 MSAPseudo<(outs RO:$wd), (ins RO:$wd_in, RO:$ws, RO:$wt),
2886 [(set RO:$wd, (Ty (vselect RO:$wd_in, RO:$wt, RO:$ws)))]>,
2887 // Note that vselect and BSEL_V treat the condition operand the opposite way
2889 // (vselect cond, if_set, if_clear)
2890 // (BSEL_V cond, if_clear, if_set)
2891 PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in,
2892 MSA128BOpnd:$ws, MSA128BOpnd:$wt)> {
2893 let Constraints = "$wd_in = $wd";
2896 def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128HOpnd, v8i16>;
2897 def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4i32>;
2898 def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2i64>;
2899 def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4f32>;
2900 def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2f64>;
2902 def BSELI_B : BSELI_B_ENC, BSELI_B_DESC;
2904 def BSET_B : BSET_B_ENC, BSET_B_DESC;
2905 def BSET_H : BSET_H_ENC, BSET_H_DESC;
2906 def BSET_W : BSET_W_ENC, BSET_W_DESC;
2907 def BSET_D : BSET_D_ENC, BSET_D_DESC;
2909 def BSETI_B : BSETI_B_ENC, BSETI_B_DESC;
2910 def BSETI_H : BSETI_H_ENC, BSETI_H_DESC;
2911 def BSETI_W : BSETI_W_ENC, BSETI_W_DESC;
2912 def BSETI_D : BSETI_D_ENC, BSETI_D_DESC;
2914 def BZ_B : BZ_B_ENC, BZ_B_DESC;
2915 def BZ_H : BZ_H_ENC, BZ_H_DESC;
2916 def BZ_W : BZ_W_ENC, BZ_W_DESC;
2917 def BZ_D : BZ_D_ENC, BZ_D_DESC;
2919 def BZ_V : BZ_V_ENC, BZ_V_DESC;
2921 def CEQ_B : CEQ_B_ENC, CEQ_B_DESC;
2922 def CEQ_H : CEQ_H_ENC, CEQ_H_DESC;
2923 def CEQ_W : CEQ_W_ENC, CEQ_W_DESC;
2924 def CEQ_D : CEQ_D_ENC, CEQ_D_DESC;
2926 def CEQI_B : CEQI_B_ENC, CEQI_B_DESC;
2927 def CEQI_H : CEQI_H_ENC, CEQI_H_DESC;
2928 def CEQI_W : CEQI_W_ENC, CEQI_W_DESC;
2929 def CEQI_D : CEQI_D_ENC, CEQI_D_DESC;
2931 def CFCMSA : CFCMSA_ENC, CFCMSA_DESC;
2933 def CLE_S_B : CLE_S_B_ENC, CLE_S_B_DESC;
2934 def CLE_S_H : CLE_S_H_ENC, CLE_S_H_DESC;
2935 def CLE_S_W : CLE_S_W_ENC, CLE_S_W_DESC;
2936 def CLE_S_D : CLE_S_D_ENC, CLE_S_D_DESC;
2938 def CLE_U_B : CLE_U_B_ENC, CLE_U_B_DESC;
2939 def CLE_U_H : CLE_U_H_ENC, CLE_U_H_DESC;
2940 def CLE_U_W : CLE_U_W_ENC, CLE_U_W_DESC;
2941 def CLE_U_D : CLE_U_D_ENC, CLE_U_D_DESC;
2943 def CLEI_S_B : CLEI_S_B_ENC, CLEI_S_B_DESC;
2944 def CLEI_S_H : CLEI_S_H_ENC, CLEI_S_H_DESC;
2945 def CLEI_S_W : CLEI_S_W_ENC, CLEI_S_W_DESC;
2946 def CLEI_S_D : CLEI_S_D_ENC, CLEI_S_D_DESC;
2948 def CLEI_U_B : CLEI_U_B_ENC, CLEI_U_B_DESC;
2949 def CLEI_U_H : CLEI_U_H_ENC, CLEI_U_H_DESC;
2950 def CLEI_U_W : CLEI_U_W_ENC, CLEI_U_W_DESC;
2951 def CLEI_U_D : CLEI_U_D_ENC, CLEI_U_D_DESC;
2953 def CLT_S_B : CLT_S_B_ENC, CLT_S_B_DESC;
2954 def CLT_S_H : CLT_S_H_ENC, CLT_S_H_DESC;
2955 def CLT_S_W : CLT_S_W_ENC, CLT_S_W_DESC;
2956 def CLT_S_D : CLT_S_D_ENC, CLT_S_D_DESC;
2958 def CLT_U_B : CLT_U_B_ENC, CLT_U_B_DESC;
2959 def CLT_U_H : CLT_U_H_ENC, CLT_U_H_DESC;
2960 def CLT_U_W : CLT_U_W_ENC, CLT_U_W_DESC;
2961 def CLT_U_D : CLT_U_D_ENC, CLT_U_D_DESC;
2963 def CLTI_S_B : CLTI_S_B_ENC, CLTI_S_B_DESC;
2964 def CLTI_S_H : CLTI_S_H_ENC, CLTI_S_H_DESC;
2965 def CLTI_S_W : CLTI_S_W_ENC, CLTI_S_W_DESC;
2966 def CLTI_S_D : CLTI_S_D_ENC, CLTI_S_D_DESC;
2968 def CLTI_U_B : CLTI_U_B_ENC, CLTI_U_B_DESC;
2969 def CLTI_U_H : CLTI_U_H_ENC, CLTI_U_H_DESC;
2970 def CLTI_U_W : CLTI_U_W_ENC, CLTI_U_W_DESC;
2971 def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC;
2973 def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC;
2974 def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC;
2975 def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC;
2976 def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC;
2978 def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC;
2979 def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC;
2980 def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC;
2981 def COPY_U_D : COPY_U_D_ENC, COPY_U_D_DESC;
2983 def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC;
2984 def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC;
2986 def CTCMSA : CTCMSA_ENC, CTCMSA_DESC;
2988 def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC;
2989 def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC;
2990 def DIV_S_W : DIV_S_W_ENC, DIV_S_W_DESC;
2991 def DIV_S_D : DIV_S_D_ENC, DIV_S_D_DESC;
2993 def DIV_U_B : DIV_U_B_ENC, DIV_U_B_DESC;
2994 def DIV_U_H : DIV_U_H_ENC, DIV_U_H_DESC;
2995 def DIV_U_W : DIV_U_W_ENC, DIV_U_W_DESC;
2996 def DIV_U_D : DIV_U_D_ENC, DIV_U_D_DESC;
2998 def DOTP_S_H : DOTP_S_H_ENC, DOTP_S_H_DESC;
2999 def DOTP_S_W : DOTP_S_W_ENC, DOTP_S_W_DESC;
3000 def DOTP_S_D : DOTP_S_D_ENC, DOTP_S_D_DESC;
3002 def DOTP_U_H : DOTP_U_H_ENC, DOTP_U_H_DESC;
3003 def DOTP_U_W : DOTP_U_W_ENC, DOTP_U_W_DESC;
3004 def DOTP_U_D : DOTP_U_D_ENC, DOTP_U_D_DESC;
3006 def DPADD_S_H : DPADD_S_H_ENC, DPADD_S_H_DESC;
3007 def DPADD_S_W : DPADD_S_W_ENC, DPADD_S_W_DESC;
3008 def DPADD_S_D : DPADD_S_D_ENC, DPADD_S_D_DESC;
3010 def DPADD_U_H : DPADD_U_H_ENC, DPADD_U_H_DESC;
3011 def DPADD_U_W : DPADD_U_W_ENC, DPADD_U_W_DESC;
3012 def DPADD_U_D : DPADD_U_D_ENC, DPADD_U_D_DESC;
3014 def DPSUB_S_H : DPSUB_S_H_ENC, DPSUB_S_H_DESC;
3015 def DPSUB_S_W : DPSUB_S_W_ENC, DPSUB_S_W_DESC;
3016 def DPSUB_S_D : DPSUB_S_D_ENC, DPSUB_S_D_DESC;
3018 def DPSUB_U_H : DPSUB_U_H_ENC, DPSUB_U_H_DESC;
3019 def DPSUB_U_W : DPSUB_U_W_ENC, DPSUB_U_W_DESC;
3020 def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC;
3022 def FADD_W : FADD_W_ENC, FADD_W_DESC;
3023 def FADD_D : FADD_D_ENC, FADD_D_DESC;
3025 def FCAF_W : FCAF_W_ENC, FCAF_W_DESC;
3026 def FCAF_D : FCAF_D_ENC, FCAF_D_DESC;
3028 def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC;
3029 def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC;
3031 def FCLE_W : FCLE_W_ENC, FCLE_W_DESC;
3032 def FCLE_D : FCLE_D_ENC, FCLE_D_DESC;
3034 def FCLT_W : FCLT_W_ENC, FCLT_W_DESC;
3035 def FCLT_D : FCLT_D_ENC, FCLT_D_DESC;
3037 def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC;
3038 def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC;
3040 def FCNE_W : FCNE_W_ENC, FCNE_W_DESC;
3041 def FCNE_D : FCNE_D_ENC, FCNE_D_DESC;
3043 def FCOR_W : FCOR_W_ENC, FCOR_W_DESC;
3044 def FCOR_D : FCOR_D_ENC, FCOR_D_DESC;
3046 def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC;
3047 def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC;
3049 def FCULE_W : FCULE_W_ENC, FCULE_W_DESC;
3050 def FCULE_D : FCULE_D_ENC, FCULE_D_DESC;
3052 def FCULT_W : FCULT_W_ENC, FCULT_W_DESC;
3053 def FCULT_D : FCULT_D_ENC, FCULT_D_DESC;
3055 def FCUN_W : FCUN_W_ENC, FCUN_W_DESC;
3056 def FCUN_D : FCUN_D_ENC, FCUN_D_DESC;
3058 def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC;
3059 def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC;
3061 def FDIV_W : FDIV_W_ENC, FDIV_W_DESC;
3062 def FDIV_D : FDIV_D_ENC, FDIV_D_DESC;
3064 def FEXDO_H : FEXDO_H_ENC, FEXDO_H_DESC;
3065 def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC;
3067 def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC;
3068 def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC;
3069 def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC;
3070 def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC;
3072 def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC;
3073 def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC;
3075 def FEXUPR_W : FEXUPR_W_ENC, FEXUPR_W_DESC;
3076 def FEXUPR_D : FEXUPR_D_ENC, FEXUPR_D_DESC;
3078 def FFINT_S_W : FFINT_S_W_ENC, FFINT_S_W_DESC;
3079 def FFINT_S_D : FFINT_S_D_ENC, FFINT_S_D_DESC;
3081 def FFINT_U_W : FFINT_U_W_ENC, FFINT_U_W_DESC;
3082 def FFINT_U_D : FFINT_U_D_ENC, FFINT_U_D_DESC;
3084 def FFQL_W : FFQL_W_ENC, FFQL_W_DESC;
3085 def FFQL_D : FFQL_D_ENC, FFQL_D_DESC;
3087 def FFQR_W : FFQR_W_ENC, FFQR_W_DESC;
3088 def FFQR_D : FFQR_D_ENC, FFQR_D_DESC;
3090 def FILL_B : FILL_B_ENC, FILL_B_DESC;
3091 def FILL_H : FILL_H_ENC, FILL_H_DESC;
3092 def FILL_W : FILL_W_ENC, FILL_W_DESC;
3093 def FILL_D : FILL_D_ENC, FILL_D_DESC;
3094 def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC;
3095 def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC;
3097 def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC;
3098 def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC;
3100 def FMADD_W : FMADD_W_ENC, FMADD_W_DESC;
3101 def FMADD_D : FMADD_D_ENC, FMADD_D_DESC;
3103 def FMAX_W : FMAX_W_ENC, FMAX_W_DESC;
3104 def FMAX_D : FMAX_D_ENC, FMAX_D_DESC;
3106 def FMAX_A_W : FMAX_A_W_ENC, FMAX_A_W_DESC;
3107 def FMAX_A_D : FMAX_A_D_ENC, FMAX_A_D_DESC;
3109 def FMIN_W : FMIN_W_ENC, FMIN_W_DESC;
3110 def FMIN_D : FMIN_D_ENC, FMIN_D_DESC;
3112 def FMIN_A_W : FMIN_A_W_ENC, FMIN_A_W_DESC;
3113 def FMIN_A_D : FMIN_A_D_ENC, FMIN_A_D_DESC;
3115 def FMSUB_W : FMSUB_W_ENC, FMSUB_W_DESC;
3116 def FMSUB_D : FMSUB_D_ENC, FMSUB_D_DESC;
3118 def FMUL_W : FMUL_W_ENC, FMUL_W_DESC;
3119 def FMUL_D : FMUL_D_ENC, FMUL_D_DESC;
3121 def FRINT_W : FRINT_W_ENC, FRINT_W_DESC;
3122 def FRINT_D : FRINT_D_ENC, FRINT_D_DESC;
3124 def FRCP_W : FRCP_W_ENC, FRCP_W_DESC;
3125 def FRCP_D : FRCP_D_ENC, FRCP_D_DESC;
3127 def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC;
3128 def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC;
3130 def FSAF_W : FSAF_W_ENC, FSAF_W_DESC;
3131 def FSAF_D : FSAF_D_ENC, FSAF_D_DESC;
3133 def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC;
3134 def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC;
3136 def FSLE_W : FSLE_W_ENC, FSLE_W_DESC;
3137 def FSLE_D : FSLE_D_ENC, FSLE_D_DESC;
3139 def FSLT_W : FSLT_W_ENC, FSLT_W_DESC;
3140 def FSLT_D : FSLT_D_ENC, FSLT_D_DESC;
3142 def FSNE_W : FSNE_W_ENC, FSNE_W_DESC;
3143 def FSNE_D : FSNE_D_ENC, FSNE_D_DESC;
3145 def FSOR_W : FSOR_W_ENC, FSOR_W_DESC;
3146 def FSOR_D : FSOR_D_ENC, FSOR_D_DESC;
3148 def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC;
3149 def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC;
3151 def FSUB_W : FSUB_W_ENC, FSUB_W_DESC;
3152 def FSUB_D : FSUB_D_ENC, FSUB_D_DESC;
3154 def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC;
3155 def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC;
3157 def FSULE_W : FSULE_W_ENC, FSULE_W_DESC;
3158 def FSULE_D : FSULE_D_ENC, FSULE_D_DESC;
3160 def FSULT_W : FSULT_W_ENC, FSULT_W_DESC;
3161 def FSULT_D : FSULT_D_ENC, FSULT_D_DESC;
3163 def FSUN_W : FSUN_W_ENC, FSUN_W_DESC;
3164 def FSUN_D : FSUN_D_ENC, FSUN_D_DESC;
3166 def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC;
3167 def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC;
3169 def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC;
3170 def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC;
3172 def FTINT_U_W : FTINT_U_W_ENC, FTINT_U_W_DESC;
3173 def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC;
3175 def FTQ_H : FTQ_H_ENC, FTQ_H_DESC;
3176 def FTQ_W : FTQ_W_ENC, FTQ_W_DESC;
3178 def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC;
3179 def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC;
3181 def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC;
3182 def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC;
3184 def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC;
3185 def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC;
3186 def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC;
3188 def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC;
3189 def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC;
3190 def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC;
3192 def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC;
3193 def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC;
3194 def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC;
3196 def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC;
3197 def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC;
3198 def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC;
3200 def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC;
3201 def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC;
3202 def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC;
3203 def ILVEV_D : ILVEV_D_ENC, ILVEV_D_DESC;
3205 def ILVL_B : ILVL_B_ENC, ILVL_B_DESC;
3206 def ILVL_H : ILVL_H_ENC, ILVL_H_DESC;
3207 def ILVL_W : ILVL_W_ENC, ILVL_W_DESC;
3208 def ILVL_D : ILVL_D_ENC, ILVL_D_DESC;
3210 def ILVOD_B : ILVOD_B_ENC, ILVOD_B_DESC;
3211 def ILVOD_H : ILVOD_H_ENC, ILVOD_H_DESC;
3212 def ILVOD_W : ILVOD_W_ENC, ILVOD_W_DESC;
3213 def ILVOD_D : ILVOD_D_ENC, ILVOD_D_DESC;
3215 def ILVR_B : ILVR_B_ENC, ILVR_B_DESC;
3216 def ILVR_H : ILVR_H_ENC, ILVR_H_DESC;
3217 def ILVR_W : ILVR_W_ENC, ILVR_W_DESC;
3218 def ILVR_D : ILVR_D_ENC, ILVR_D_DESC;
3220 def INSERT_B : INSERT_B_ENC, INSERT_B_DESC;
3221 def INSERT_H : INSERT_H_ENC, INSERT_H_DESC;
3222 def INSERT_W : INSERT_W_ENC, INSERT_W_DESC;
3223 def INSERT_D : INSERT_D_ENC, INSERT_D_DESC;
3225 // INSERT_FW_PSEUDO defined after INSVE_W
3226 // INSERT_FD_PSEUDO defined after INSVE_D
3228 // There is a fourth operand that is not present in the encoding. Use a
3229 // custom decoder to get a chance to add it.
3230 let DecoderMethod = "DecodeINSVE_DF" in {
3231 def INSVE_B : INSVE_B_ENC, INSVE_B_DESC;
3232 def INSVE_H : INSVE_H_ENC, INSVE_H_DESC;
3233 def INSVE_W : INSVE_W_ENC, INSVE_W_DESC;
3234 def INSVE_D : INSVE_D_ENC, INSVE_D_DESC;
3237 def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC;
3238 def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC;
3240 def INSERT_B_VIDX_PSEUDO : INSERT_B_VIDX_PSEUDO_DESC;
3241 def INSERT_H_VIDX_PSEUDO : INSERT_H_VIDX_PSEUDO_DESC;
3242 def INSERT_W_VIDX_PSEUDO : INSERT_W_VIDX_PSEUDO_DESC;
3243 def INSERT_D_VIDX_PSEUDO : INSERT_D_VIDX_PSEUDO_DESC;
3244 def INSERT_FW_VIDX_PSEUDO : INSERT_FW_VIDX_PSEUDO_DESC;
3245 def INSERT_FD_VIDX_PSEUDO : INSERT_FD_VIDX_PSEUDO_DESC;
3247 def LD_B: LD_B_ENC, LD_B_DESC;
3248 def LD_H: LD_H_ENC, LD_H_DESC;
3249 def LD_W: LD_W_ENC, LD_W_DESC;
3250 def LD_D: LD_D_ENC, LD_D_DESC;
3252 def LDI_B : LDI_B_ENC, LDI_B_DESC;
3253 def LDI_H : LDI_H_ENC, LDI_H_DESC;
3254 def LDI_W : LDI_W_ENC, LDI_W_DESC;
3255 def LDI_D : LDI_D_ENC, LDI_D_DESC;
3257 def LSA : LSA_ENC, LSA_DESC;
3258 def DLSA : DLSA_ENC, DLSA_DESC;
3260 def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC;
3261 def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC;
3263 def MADDR_Q_H : MADDR_Q_H_ENC, MADDR_Q_H_DESC;
3264 def MADDR_Q_W : MADDR_Q_W_ENC, MADDR_Q_W_DESC;
3266 def MADDV_B : MADDV_B_ENC, MADDV_B_DESC;
3267 def MADDV_H : MADDV_H_ENC, MADDV_H_DESC;
3268 def MADDV_W : MADDV_W_ENC, MADDV_W_DESC;
3269 def MADDV_D : MADDV_D_ENC, MADDV_D_DESC;
3271 def MAX_A_B : MAX_A_B_ENC, MAX_A_B_DESC;
3272 def MAX_A_H : MAX_A_H_ENC, MAX_A_H_DESC;
3273 def MAX_A_W : MAX_A_W_ENC, MAX_A_W_DESC;
3274 def MAX_A_D : MAX_A_D_ENC, MAX_A_D_DESC;
3276 def MAX_S_B : MAX_S_B_ENC, MAX_S_B_DESC;
3277 def MAX_S_H : MAX_S_H_ENC, MAX_S_H_DESC;
3278 def MAX_S_W : MAX_S_W_ENC, MAX_S_W_DESC;
3279 def MAX_S_D : MAX_S_D_ENC, MAX_S_D_DESC;
3281 def MAX_U_B : MAX_U_B_ENC, MAX_U_B_DESC;
3282 def MAX_U_H : MAX_U_H_ENC, MAX_U_H_DESC;
3283 def MAX_U_W : MAX_U_W_ENC, MAX_U_W_DESC;
3284 def MAX_U_D : MAX_U_D_ENC, MAX_U_D_DESC;
3286 def MAXI_S_B : MAXI_S_B_ENC, MAXI_S_B_DESC;
3287 def MAXI_S_H : MAXI_S_H_ENC, MAXI_S_H_DESC;
3288 def MAXI_S_W : MAXI_S_W_ENC, MAXI_S_W_DESC;
3289 def MAXI_S_D : MAXI_S_D_ENC, MAXI_S_D_DESC;
3291 def MAXI_U_B : MAXI_U_B_ENC, MAXI_U_B_DESC;
3292 def MAXI_U_H : MAXI_U_H_ENC, MAXI_U_H_DESC;
3293 def MAXI_U_W : MAXI_U_W_ENC, MAXI_U_W_DESC;
3294 def MAXI_U_D : MAXI_U_D_ENC, MAXI_U_D_DESC;
3296 def MIN_A_B : MIN_A_B_ENC, MIN_A_B_DESC;
3297 def MIN_A_H : MIN_A_H_ENC, MIN_A_H_DESC;
3298 def MIN_A_W : MIN_A_W_ENC, MIN_A_W_DESC;
3299 def MIN_A_D : MIN_A_D_ENC, MIN_A_D_DESC;
3301 def MIN_S_B : MIN_S_B_ENC, MIN_S_B_DESC;
3302 def MIN_S_H : MIN_S_H_ENC, MIN_S_H_DESC;
3303 def MIN_S_W : MIN_S_W_ENC, MIN_S_W_DESC;
3304 def MIN_S_D : MIN_S_D_ENC, MIN_S_D_DESC;
3306 def MIN_U_B : MIN_U_B_ENC, MIN_U_B_DESC;
3307 def MIN_U_H : MIN_U_H_ENC, MIN_U_H_DESC;
3308 def MIN_U_W : MIN_U_W_ENC, MIN_U_W_DESC;
3309 def MIN_U_D : MIN_U_D_ENC, MIN_U_D_DESC;
3311 def MINI_S_B : MINI_S_B_ENC, MINI_S_B_DESC;
3312 def MINI_S_H : MINI_S_H_ENC, MINI_S_H_DESC;
3313 def MINI_S_W : MINI_S_W_ENC, MINI_S_W_DESC;
3314 def MINI_S_D : MINI_S_D_ENC, MINI_S_D_DESC;
3316 def MINI_U_B : MINI_U_B_ENC, MINI_U_B_DESC;
3317 def MINI_U_H : MINI_U_H_ENC, MINI_U_H_DESC;
3318 def MINI_U_W : MINI_U_W_ENC, MINI_U_W_DESC;
3319 def MINI_U_D : MINI_U_D_ENC, MINI_U_D_DESC;
3321 def MOD_S_B : MOD_S_B_ENC, MOD_S_B_DESC;
3322 def MOD_S_H : MOD_S_H_ENC, MOD_S_H_DESC;
3323 def MOD_S_W : MOD_S_W_ENC, MOD_S_W_DESC;
3324 def MOD_S_D : MOD_S_D_ENC, MOD_S_D_DESC;
3326 def MOD_U_B : MOD_U_B_ENC, MOD_U_B_DESC;
3327 def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC;
3328 def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC;
3329 def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC;
3331 def MOVE_V : MOVE_V_ENC, MOVE_V_DESC;
3333 def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC;
3334 def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC;
3336 def MSUBR_Q_H : MSUBR_Q_H_ENC, MSUBR_Q_H_DESC;
3337 def MSUBR_Q_W : MSUBR_Q_W_ENC, MSUBR_Q_W_DESC;
3339 def MSUBV_B : MSUBV_B_ENC, MSUBV_B_DESC;
3340 def MSUBV_H : MSUBV_H_ENC, MSUBV_H_DESC;
3341 def MSUBV_W : MSUBV_W_ENC, MSUBV_W_DESC;
3342 def MSUBV_D : MSUBV_D_ENC, MSUBV_D_DESC;
3344 def MUL_Q_H : MUL_Q_H_ENC, MUL_Q_H_DESC;
3345 def MUL_Q_W : MUL_Q_W_ENC, MUL_Q_W_DESC;
3347 def MULR_Q_H : MULR_Q_H_ENC, MULR_Q_H_DESC;
3348 def MULR_Q_W : MULR_Q_W_ENC, MULR_Q_W_DESC;
3350 def MULV_B : MULV_B_ENC, MULV_B_DESC;
3351 def MULV_H : MULV_H_ENC, MULV_H_DESC;
3352 def MULV_W : MULV_W_ENC, MULV_W_DESC;
3353 def MULV_D : MULV_D_ENC, MULV_D_DESC;
3355 def NLOC_B : NLOC_B_ENC, NLOC_B_DESC;
3356 def NLOC_H : NLOC_H_ENC, NLOC_H_DESC;
3357 def NLOC_W : NLOC_W_ENC, NLOC_W_DESC;
3358 def NLOC_D : NLOC_D_ENC, NLOC_D_DESC;
3360 def NLZC_B : NLZC_B_ENC, NLZC_B_DESC;
3361 def NLZC_H : NLZC_H_ENC, NLZC_H_DESC;
3362 def NLZC_W : NLZC_W_ENC, NLZC_W_DESC;
3363 def NLZC_D : NLZC_D_ENC, NLZC_D_DESC;
3365 def NOR_V : NOR_V_ENC, NOR_V_DESC;
3366 def NOR_V_H_PSEUDO : NOR_V_H_PSEUDO_DESC,
3367 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3370 def NOR_V_W_PSEUDO : NOR_V_W_PSEUDO_DESC,
3371 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3374 def NOR_V_D_PSEUDO : NOR_V_D_PSEUDO_DESC,
3375 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3379 def NORI_B : NORI_B_ENC, NORI_B_DESC;
3381 def OR_V : OR_V_ENC, OR_V_DESC;
3382 def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC,
3383 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3386 def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC,
3387 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3390 def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC,
3391 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3395 def ORI_B : ORI_B_ENC, ORI_B_DESC;
3397 def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC;
3398 def PCKEV_H : PCKEV_H_ENC, PCKEV_H_DESC;
3399 def PCKEV_W : PCKEV_W_ENC, PCKEV_W_DESC;
3400 def PCKEV_D : PCKEV_D_ENC, PCKEV_D_DESC;
3402 def PCKOD_B : PCKOD_B_ENC, PCKOD_B_DESC;
3403 def PCKOD_H : PCKOD_H_ENC, PCKOD_H_DESC;
3404 def PCKOD_W : PCKOD_W_ENC, PCKOD_W_DESC;
3405 def PCKOD_D : PCKOD_D_ENC, PCKOD_D_DESC;
3407 def PCNT_B : PCNT_B_ENC, PCNT_B_DESC;
3408 def PCNT_H : PCNT_H_ENC, PCNT_H_DESC;
3409 def PCNT_W : PCNT_W_ENC, PCNT_W_DESC;
3410 def PCNT_D : PCNT_D_ENC, PCNT_D_DESC;
3412 def SAT_S_B : SAT_S_B_ENC, SAT_S_B_DESC;
3413 def SAT_S_H : SAT_S_H_ENC, SAT_S_H_DESC;
3414 def SAT_S_W : SAT_S_W_ENC, SAT_S_W_DESC;
3415 def SAT_S_D : SAT_S_D_ENC, SAT_S_D_DESC;
3417 def SAT_U_B : SAT_U_B_ENC, SAT_U_B_DESC;
3418 def SAT_U_H : SAT_U_H_ENC, SAT_U_H_DESC;
3419 def SAT_U_W : SAT_U_W_ENC, SAT_U_W_DESC;
3420 def SAT_U_D : SAT_U_D_ENC, SAT_U_D_DESC;
3422 def SHF_B : SHF_B_ENC, SHF_B_DESC;
3423 def SHF_H : SHF_H_ENC, SHF_H_DESC;
3424 def SHF_W : SHF_W_ENC, SHF_W_DESC;
3426 def SLD_B : SLD_B_ENC, SLD_B_DESC;
3427 def SLD_H : SLD_H_ENC, SLD_H_DESC;
3428 def SLD_W : SLD_W_ENC, SLD_W_DESC;
3429 def SLD_D : SLD_D_ENC, SLD_D_DESC;
3431 def SLDI_B : SLDI_B_ENC, SLDI_B_DESC;
3432 def SLDI_H : SLDI_H_ENC, SLDI_H_DESC;
3433 def SLDI_W : SLDI_W_ENC, SLDI_W_DESC;
3434 def SLDI_D : SLDI_D_ENC, SLDI_D_DESC;
3436 def SLL_B : SLL_B_ENC, SLL_B_DESC;
3437 def SLL_H : SLL_H_ENC, SLL_H_DESC;
3438 def SLL_W : SLL_W_ENC, SLL_W_DESC;
3439 def SLL_D : SLL_D_ENC, SLL_D_DESC;
3441 def SLLI_B : SLLI_B_ENC, SLLI_B_DESC;
3442 def SLLI_H : SLLI_H_ENC, SLLI_H_DESC;
3443 def SLLI_W : SLLI_W_ENC, SLLI_W_DESC;
3444 def SLLI_D : SLLI_D_ENC, SLLI_D_DESC;
3446 def SPLAT_B : SPLAT_B_ENC, SPLAT_B_DESC;
3447 def SPLAT_H : SPLAT_H_ENC, SPLAT_H_DESC;
3448 def SPLAT_W : SPLAT_W_ENC, SPLAT_W_DESC;
3449 def SPLAT_D : SPLAT_D_ENC, SPLAT_D_DESC;
3451 def SPLATI_B : SPLATI_B_ENC, SPLATI_B_DESC;
3452 def SPLATI_H : SPLATI_H_ENC, SPLATI_H_DESC;
3453 def SPLATI_W : SPLATI_W_ENC, SPLATI_W_DESC;
3454 def SPLATI_D : SPLATI_D_ENC, SPLATI_D_DESC;
3456 def SRA_B : SRA_B_ENC, SRA_B_DESC;
3457 def SRA_H : SRA_H_ENC, SRA_H_DESC;
3458 def SRA_W : SRA_W_ENC, SRA_W_DESC;
3459 def SRA_D : SRA_D_ENC, SRA_D_DESC;
3461 def SRAI_B : SRAI_B_ENC, SRAI_B_DESC;
3462 def SRAI_H : SRAI_H_ENC, SRAI_H_DESC;
3463 def SRAI_W : SRAI_W_ENC, SRAI_W_DESC;
3464 def SRAI_D : SRAI_D_ENC, SRAI_D_DESC;
3466 def SRAR_B : SRAR_B_ENC, SRAR_B_DESC;
3467 def SRAR_H : SRAR_H_ENC, SRAR_H_DESC;
3468 def SRAR_W : SRAR_W_ENC, SRAR_W_DESC;
3469 def SRAR_D : SRAR_D_ENC, SRAR_D_DESC;
3471 def SRARI_B : SRARI_B_ENC, SRARI_B_DESC;
3472 def SRARI_H : SRARI_H_ENC, SRARI_H_DESC;
3473 def SRARI_W : SRARI_W_ENC, SRARI_W_DESC;
3474 def SRARI_D : SRARI_D_ENC, SRARI_D_DESC;
3476 def SRL_B : SRL_B_ENC, SRL_B_DESC;
3477 def SRL_H : SRL_H_ENC, SRL_H_DESC;
3478 def SRL_W : SRL_W_ENC, SRL_W_DESC;
3479 def SRL_D : SRL_D_ENC, SRL_D_DESC;
3481 def SRLI_B : SRLI_B_ENC, SRLI_B_DESC;
3482 def SRLI_H : SRLI_H_ENC, SRLI_H_DESC;
3483 def SRLI_W : SRLI_W_ENC, SRLI_W_DESC;
3484 def SRLI_D : SRLI_D_ENC, SRLI_D_DESC;
3486 def SRLR_B : SRLR_B_ENC, SRLR_B_DESC;
3487 def SRLR_H : SRLR_H_ENC, SRLR_H_DESC;
3488 def SRLR_W : SRLR_W_ENC, SRLR_W_DESC;
3489 def SRLR_D : SRLR_D_ENC, SRLR_D_DESC;
3491 def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC;
3492 def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC;
3493 def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC;
3494 def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC;
3496 def ST_B: ST_B_ENC, ST_B_DESC;
3497 def ST_H: ST_H_ENC, ST_H_DESC;
3498 def ST_W: ST_W_ENC, ST_W_DESC;
3499 def ST_D: ST_D_ENC, ST_D_DESC;
3501 def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC;
3502 def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC;
3503 def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC;
3504 def SUBS_S_D : SUBS_S_D_ENC, SUBS_S_D_DESC;
3506 def SUBS_U_B : SUBS_U_B_ENC, SUBS_U_B_DESC;
3507 def SUBS_U_H : SUBS_U_H_ENC, SUBS_U_H_DESC;
3508 def SUBS_U_W : SUBS_U_W_ENC, SUBS_U_W_DESC;
3509 def SUBS_U_D : SUBS_U_D_ENC, SUBS_U_D_DESC;
3511 def SUBSUS_U_B : SUBSUS_U_B_ENC, SUBSUS_U_B_DESC;
3512 def SUBSUS_U_H : SUBSUS_U_H_ENC, SUBSUS_U_H_DESC;
3513 def SUBSUS_U_W : SUBSUS_U_W_ENC, SUBSUS_U_W_DESC;
3514 def SUBSUS_U_D : SUBSUS_U_D_ENC, SUBSUS_U_D_DESC;
3516 def SUBSUU_S_B : SUBSUU_S_B_ENC, SUBSUU_S_B_DESC;
3517 def SUBSUU_S_H : SUBSUU_S_H_ENC, SUBSUU_S_H_DESC;
3518 def SUBSUU_S_W : SUBSUU_S_W_ENC, SUBSUU_S_W_DESC;
3519 def SUBSUU_S_D : SUBSUU_S_D_ENC, SUBSUU_S_D_DESC;
3521 def SUBV_B : SUBV_B_ENC, SUBV_B_DESC;
3522 def SUBV_H : SUBV_H_ENC, SUBV_H_DESC;
3523 def SUBV_W : SUBV_W_ENC, SUBV_W_DESC;
3524 def SUBV_D : SUBV_D_ENC, SUBV_D_DESC;
3526 def SUBVI_B : SUBVI_B_ENC, SUBVI_B_DESC;
3527 def SUBVI_H : SUBVI_H_ENC, SUBVI_H_DESC;
3528 def SUBVI_W : SUBVI_W_ENC, SUBVI_W_DESC;
3529 def SUBVI_D : SUBVI_D_ENC, SUBVI_D_DESC;
3531 def VSHF_B : VSHF_B_ENC, VSHF_B_DESC;
3532 def VSHF_H : VSHF_H_ENC, VSHF_H_DESC;
3533 def VSHF_W : VSHF_W_ENC, VSHF_W_DESC;
3534 def VSHF_D : VSHF_D_ENC, VSHF_D_DESC;
3536 def XOR_V : XOR_V_ENC, XOR_V_DESC;
3537 def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC,
3538 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3541 def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC,
3542 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3545 def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC,
3546 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3550 def XORI_B : XORI_B_ENC, XORI_B_DESC;
3553 class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> :
3554 Pat<pattern, result>, Requires<pred>;
3556 def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx),
3557 (COPY_S_W MSA128W:$ws, immZExt4:$idx)>;
3559 def : MSAPat<(v8f16 (load addrimm10:$addr)), (LD_H addrimm10:$addr)>;
3560 def : MSAPat<(v4f32 (load addrimm10:$addr)), (LD_W addrimm10:$addr)>;
3561 def : MSAPat<(v2f64 (load addrimm10:$addr)), (LD_D addrimm10:$addr)>;
3563 def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10:$addr),
3564 (ST_H MSA128H:$ws, addrimm10:$addr)>;
3565 def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrimm10:$addr),
3566 (ST_W MSA128W:$ws, addrimm10:$addr)>;
3567 def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrimm10:$addr),
3568 (ST_D MSA128D:$ws, addrimm10:$addr)>;
3570 class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD,
3571 RegisterOperand ROWS = ROWD,
3572 InstrItinClass itin = NoItinerary> :
3573 MSAPseudo<(outs ROWD:$wd),
3575 [(set ROWD:$wd, (fabs ROWS:$ws))]> {
3576 InstrItinClass Itinerary = itin;
3578 def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>,
3579 PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws,
3581 def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128DOpnd>,
3582 PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws,
3585 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3586 RegisterClass DstRC, list<Predicate> preds = [HasMSA]> :
3587 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3588 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3590 // These are endian-independent because the element size doesnt change
3591 def : MSABitconvertPat<v8i16, v8f16, MSA128H>;
3592 def : MSABitconvertPat<v4i32, v4f32, MSA128W>;
3593 def : MSABitconvertPat<v2i64, v2f64, MSA128D>;
3594 def : MSABitconvertPat<v8f16, v8i16, MSA128H>;
3595 def : MSABitconvertPat<v4f32, v4i32, MSA128W>;
3596 def : MSABitconvertPat<v2f64, v2i64, MSA128D>;
3598 // Little endian bitcasts are always no-ops
3599 def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>;
3600 def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>;
3601 def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>;
3602 def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>;
3603 def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>;
3604 def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>;
3606 def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>;
3607 def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>;
3608 def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>;
3609 def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>;
3610 def : MSABitconvertPat<v8i16, v2f64, MSA128H, [HasMSA, IsLE]>;
3612 def : MSABitconvertPat<v4i32, v16i8, MSA128W, [HasMSA, IsLE]>;
3613 def : MSABitconvertPat<v4i32, v8i16, MSA128W, [HasMSA, IsLE]>;
3614 def : MSABitconvertPat<v4i32, v2i64, MSA128W, [HasMSA, IsLE]>;
3615 def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>;
3616 def : MSABitconvertPat<v4i32, v2f64, MSA128W, [HasMSA, IsLE]>;
3618 def : MSABitconvertPat<v2i64, v16i8, MSA128D, [HasMSA, IsLE]>;
3619 def : MSABitconvertPat<v2i64, v8i16, MSA128D, [HasMSA, IsLE]>;
3620 def : MSABitconvertPat<v2i64, v4i32, MSA128D, [HasMSA, IsLE]>;
3621 def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>;
3622 def : MSABitconvertPat<v2i64, v4f32, MSA128D, [HasMSA, IsLE]>;
3624 def : MSABitconvertPat<v4f32, v16i8, MSA128W, [HasMSA, IsLE]>;
3625 def : MSABitconvertPat<v4f32, v8i16, MSA128W, [HasMSA, IsLE]>;
3626 def : MSABitconvertPat<v4f32, v2i64, MSA128W, [HasMSA, IsLE]>;
3627 def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>;
3628 def : MSABitconvertPat<v4f32, v2f64, MSA128W, [HasMSA, IsLE]>;
3630 def : MSABitconvertPat<v2f64, v16i8, MSA128D, [HasMSA, IsLE]>;
3631 def : MSABitconvertPat<v2f64, v8i16, MSA128D, [HasMSA, IsLE]>;
3632 def : MSABitconvertPat<v2f64, v4i32, MSA128D, [HasMSA, IsLE]>;
3633 def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>;
3634 def : MSABitconvertPat<v2f64, v4f32, MSA128D, [HasMSA, IsLE]>;
3636 // Big endian bitcasts expand to shuffle instructions.
3637 // This is because bitcast is defined to be a store/load sequence and the
3638 // vector store/load instructions are mixed-endian with respect to the vector
3639 // as a whole (little endian with respect to element order, but big endian
3642 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3643 RegisterClass DstRC, MSAInst Insn,
3644 RegisterClass ViaRC> :
3645 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3646 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27),
3650 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3651 RegisterClass DstRC, MSAInst Insn,
3652 RegisterClass ViaRC> :
3653 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3654 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177),
3658 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
3659 RegisterClass DstRC> :
3660 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3662 class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
3663 RegisterClass DstRC> :
3664 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3666 class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT,
3667 RegisterClass DstRC> :
3668 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3672 (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27),
3677 class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT,
3678 RegisterClass DstRC> :
3679 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3681 class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT,
3682 RegisterClass DstRC> :
3683 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3685 class MSABitconvertReverseWInDPat<ValueType DstVT, ValueType SrcVT,
3686 RegisterClass DstRC> :
3687 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_W, MSA128W>;
3689 def : MSABitconvertReverseBInHPat<v8i16, v16i8, MSA128H>;
3690 def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>;
3691 def : MSABitconvertReverseBInWPat<v4i32, v16i8, MSA128W>;
3692 def : MSABitconvertReverseBInWPat<v4f32, v16i8, MSA128W>;
3693 def : MSABitconvertReverseBInDPat<v2i64, v16i8, MSA128D>;
3694 def : MSABitconvertReverseBInDPat<v2f64, v16i8, MSA128D>;
3696 def : MSABitconvertReverseBInHPat<v16i8, v8i16, MSA128B>;
3697 def : MSABitconvertReverseHInWPat<v4i32, v8i16, MSA128W>;
3698 def : MSABitconvertReverseHInWPat<v4f32, v8i16, MSA128W>;
3699 def : MSABitconvertReverseHInDPat<v2i64, v8i16, MSA128D>;
3700 def : MSABitconvertReverseHInDPat<v2f64, v8i16, MSA128D>;
3702 def : MSABitconvertReverseBInHPat<v16i8, v8f16, MSA128B>;
3703 def : MSABitconvertReverseHInWPat<v4i32, v8f16, MSA128W>;
3704 def : MSABitconvertReverseHInWPat<v4f32, v8f16, MSA128W>;
3705 def : MSABitconvertReverseHInDPat<v2i64, v8f16, MSA128D>;
3706 def : MSABitconvertReverseHInDPat<v2f64, v8f16, MSA128D>;
3708 def : MSABitconvertReverseBInWPat<v16i8, v4i32, MSA128B>;
3709 def : MSABitconvertReverseHInWPat<v8i16, v4i32, MSA128H>;
3710 def : MSABitconvertReverseHInWPat<v8f16, v4i32, MSA128H>;
3711 def : MSABitconvertReverseWInDPat<v2i64, v4i32, MSA128D>;
3712 def : MSABitconvertReverseWInDPat<v2f64, v4i32, MSA128D>;
3714 def : MSABitconvertReverseBInWPat<v16i8, v4f32, MSA128B>;
3715 def : MSABitconvertReverseHInWPat<v8i16, v4f32, MSA128H>;
3716 def : MSABitconvertReverseHInWPat<v8f16, v4f32, MSA128H>;
3717 def : MSABitconvertReverseWInDPat<v2i64, v4f32, MSA128D>;
3718 def : MSABitconvertReverseWInDPat<v2f64, v4f32, MSA128D>;
3720 def : MSABitconvertReverseBInDPat<v16i8, v2i64, MSA128B>;
3721 def : MSABitconvertReverseHInDPat<v8i16, v2i64, MSA128H>;
3722 def : MSABitconvertReverseHInDPat<v8f16, v2i64, MSA128H>;
3723 def : MSABitconvertReverseWInDPat<v4i32, v2i64, MSA128W>;
3724 def : MSABitconvertReverseWInDPat<v4f32, v2i64, MSA128W>;
3726 def : MSABitconvertReverseBInDPat<v16i8, v2f64, MSA128B>;
3727 def : MSABitconvertReverseHInDPat<v8i16, v2f64, MSA128H>;
3728 def : MSABitconvertReverseHInDPat<v8f16, v2f64, MSA128H>;
3729 def : MSABitconvertReverseWInDPat<v4i32, v2f64, MSA128W>;
3730 def : MSABitconvertReverseWInDPat<v4f32, v2f64, MSA128W>;
3732 // Pseudos used to implement BNZ.df, and BZ.df
3734 class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode,
3736 InstrItinClass itin = NoItinerary> :
3737 MipsPseudo<(outs GPR32:$dst),
3739 [(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> {
3740 bit usesCustomInserter = 1;
3743 def SNZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8,
3744 MSA128B, NoItinerary>;
3745 def SNZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16,
3746 MSA128H, NoItinerary>;
3747 def SNZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32,
3748 MSA128W, NoItinerary>;
3749 def SNZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64,
3750 MSA128D, NoItinerary>;
3751 def SNZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8,
3752 MSA128B, NoItinerary>;
3754 def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8,
3755 MSA128B, NoItinerary>;
3756 def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16,
3757 MSA128H, NoItinerary>;
3758 def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32,
3759 MSA128W, NoItinerary>;
3760 def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64,
3761 MSA128D, NoItinerary>;
3762 def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8,
3763 MSA128B, NoItinerary>;
3765 // Vector extraction with variable index
3766 def : MSAPat<(i32 (vextract_sext_i8 v16i8:$ws, i32:$idx)),
3767 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
3771 def : MSAPat<(i32 (vextract_sext_i16 v8i16:$ws, i32:$idx)),
3772 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
3776 def : MSAPat<(i32 (vextract_sext_i32 v4i32:$ws, i32:$idx)),
3777 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
3781 def : MSAPat<(i64 (vextract_sext_i64 v2i64:$ws, i32:$idx)),
3782 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
3785 GPR64), [HasMSA, IsGP64bit]>;
3787 def : MSAPat<(i32 (vextract_zext_i8 v16i8:$ws, i32:$idx)),
3788 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
3792 def : MSAPat<(i32 (vextract_zext_i16 v8i16:$ws, i32:$idx)),
3793 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
3797 def : MSAPat<(i32 (vextract_zext_i32 v4i32:$ws, i32:$idx)),
3798 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
3802 def : MSAPat<(i64 (vextract_zext_i64 v2i64:$ws, i32:$idx)),
3803 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
3806 GPR64), [HasMSA, IsGP64bit]>;
3808 def : MSAPat<(f32 (vector_extract v4f32:$ws, i32:$idx)),
3809 (f32 (EXTRACT_SUBREG (SPLAT_W v4f32:$ws,
3812 def : MSAPat<(f64 (vector_extract v2f64:$ws, i32:$idx)),
3813 (f64 (EXTRACT_SUBREG (SPLAT_D v2f64:$ws,