1 //===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips MSA ASE instructions.
12 //===----------------------------------------------------------------------===//
14 def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>;
15 def SDT_VSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
18 SDTCisVT<3, OtherVT>]>;
19 def SDT_VFSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
22 SDTCisVT<3, OtherVT>]>;
23 def SDT_VSHF : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>,
24 SDTCisInt<1>, SDTCisVec<1>,
25 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>;
26 def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
27 SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>;
28 def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
29 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
31 def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>;
32 def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>;
33 def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>;
34 def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>;
35 def MipsVSMax : SDNode<"MipsISD::VSMAX", SDTIntBinOp,
36 [SDNPCommutative, SDNPAssociative]>;
37 def MipsVSMin : SDNode<"MipsISD::VSMIN", SDTIntBinOp,
38 [SDNPCommutative, SDNPAssociative]>;
39 def MipsVUMax : SDNode<"MipsISD::VUMAX", SDTIntBinOp,
40 [SDNPCommutative, SDNPAssociative]>;
41 def MipsVUMin : SDNode<"MipsISD::VUMIN", SDTIntBinOp,
42 [SDNPCommutative, SDNPAssociative]>;
43 def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp,
44 [SDNPCommutative, SDNPAssociative]>;
45 def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>;
46 def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>;
47 def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>;
48 def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>;
49 def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>;
50 def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>;
51 def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>;
52 def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>;
54 def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>;
55 def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>;
57 def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT",
58 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
59 def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT",
60 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
64 def uimm2 : Operand<i32> {
65 let PrintMethod = "printUnsignedImm";
68 def uimm3 : Operand<i32> {
69 let PrintMethod = "printUnsignedImm";
72 def uimm4 : Operand<i32> {
73 let PrintMethod = "printUnsignedImm";
76 def uimm8 : Operand<i32> {
77 let PrintMethod = "printUnsignedImm";
80 def simm5 : Operand<i32>;
82 def simm10 : Operand<i32>;
84 def vsplat_uimm1 : Operand<vAny> {
85 let PrintMethod = "printUnsignedImm8";
88 def vsplat_uimm2 : Operand<vAny> {
89 let PrintMethod = "printUnsignedImm8";
92 def vsplat_uimm3 : Operand<vAny> {
93 let PrintMethod = "printUnsignedImm";
96 def vsplat_uimm4 : Operand<vAny> {
97 let PrintMethod = "printUnsignedImm";
100 def vsplat_uimm5 : Operand<vAny> {
101 let PrintMethod = "printUnsignedImm";
104 def vsplat_uimm6 : Operand<vAny> {
105 let PrintMethod = "printUnsignedImm";
108 def vsplat_uimm8 : Operand<vAny> {
109 let PrintMethod = "printUnsignedImm";
112 def vsplat_simm5 : Operand<vAny>;
114 def vsplat_simm10 : Operand<vAny>;
116 def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>;
119 def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx),
120 (MipsVExtractSExt node:$vec, node:$idx, i8)>;
121 def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx),
122 (MipsVExtractSExt node:$vec, node:$idx, i16)>;
123 def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx),
124 (MipsVExtractSExt node:$vec, node:$idx, i32)>;
126 def vextract_zext_i8 : PatFrag<(ops node:$vec, node:$idx),
127 (MipsVExtractZExt node:$vec, node:$idx, i8)>;
128 def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx),
129 (MipsVExtractZExt node:$vec, node:$idx, i16)>;
130 def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx),
131 (MipsVExtractZExt node:$vec, node:$idx, i32)>;
133 def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx),
134 (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>;
135 def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx),
136 (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>;
137 def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx),
138 (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>;
140 class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> :
141 PatFrag<(ops node:$lhs, node:$rhs),
142 (ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>;
144 // ISD::SETFALSE cannot occur
145 def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>;
146 def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>;
147 def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>;
148 def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>;
149 def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>;
150 def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>;
151 def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>;
152 def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>;
153 def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>;
154 def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>;
155 def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>;
156 def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>;
157 def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>;
158 def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>;
159 def vfsetun_v4f32 : vfsetcc_type<v4i32, v4f32, SETUO>;
160 def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>;
161 def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>;
162 def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>;
163 def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>;
164 def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>;
165 def vfsetugt_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGT>;
166 def vfsetugt_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGT>;
167 def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>;
168 def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>;
169 def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>;
170 def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>;
171 def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>;
172 def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>;
173 // ISD::SETTRUE cannot occur
174 // ISD::SETFALSE2 cannot occur
175 // ISD::SETTRUE2 cannot occur
177 class vsetcc_type<ValueType ResTy, CondCode CC> :
178 PatFrag<(ops node:$lhs, node:$rhs),
179 (ResTy (vsetcc node:$lhs, node:$rhs, CC))>;
181 def vseteq_v16i8 : vsetcc_type<v16i8, SETEQ>;
182 def vseteq_v8i16 : vsetcc_type<v8i16, SETEQ>;
183 def vseteq_v4i32 : vsetcc_type<v4i32, SETEQ>;
184 def vseteq_v2i64 : vsetcc_type<v2i64, SETEQ>;
185 def vsetle_v16i8 : vsetcc_type<v16i8, SETLE>;
186 def vsetle_v8i16 : vsetcc_type<v8i16, SETLE>;
187 def vsetle_v4i32 : vsetcc_type<v4i32, SETLE>;
188 def vsetle_v2i64 : vsetcc_type<v2i64, SETLE>;
189 def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>;
190 def vsetlt_v8i16 : vsetcc_type<v8i16, SETLT>;
191 def vsetlt_v4i32 : vsetcc_type<v4i32, SETLT>;
192 def vsetlt_v2i64 : vsetcc_type<v2i64, SETLT>;
193 def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>;
194 def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>;
195 def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>;
196 def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>;
197 def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>;
198 def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>;
199 def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>;
200 def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>;
202 def vsplati8 : PatFrag<(ops node:$e0),
203 (v16i8 (build_vector node:$e0, node:$e0,
210 node:$e0, node:$e0))>;
211 def vsplati16 : PatFrag<(ops node:$e0),
212 (v8i16 (build_vector node:$e0, node:$e0,
215 node:$e0, node:$e0))>;
216 def vsplati32 : PatFrag<(ops node:$e0),
217 (v4i32 (build_vector node:$e0, node:$e0,
218 node:$e0, node:$e0))>;
219 def vsplati64 : PatFrag<(ops node:$e0),
220 (v2i64 (build_vector:$v0 node:$e0, node:$e0))>;
221 def vsplatf32 : PatFrag<(ops node:$e0),
222 (v4f32 (build_vector node:$e0, node:$e0,
223 node:$e0, node:$e0))>;
224 def vsplatf64 : PatFrag<(ops node:$e0),
225 (v2f64 (build_vector node:$e0, node:$e0))>;
227 def vsplati8_elt : PatFrag<(ops node:$v, node:$i),
228 (MipsVSHF (vsplati8 node:$i), node:$v, node:$v)>;
229 def vsplati16_elt : PatFrag<(ops node:$v, node:$i),
230 (MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>;
231 def vsplati32_elt : PatFrag<(ops node:$v, node:$i),
232 (MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>;
233 def vsplati64_elt : PatFrag<(ops node:$v, node:$i),
234 (MipsVSHF (vsplati64 node:$i), node:$v, node:$v)>;
236 class SplatPatLeaf<Operand opclass, dag frag, code pred = [{}],
237 SDNodeXForm xform = NOOP_SDNodeXForm>
238 : PatLeaf<frag, pred, xform> {
239 Operand OpClass = opclass;
242 class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn,
243 list<SDNode> roots = [],
244 list<SDNodeProperty> props = []> :
245 ComplexPattern<ty, numops, fn, roots, props> {
246 Operand OpClass = opclass;
249 def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1,
251 [build_vector, bitconvert]>;
253 def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1,
255 [build_vector, bitconvert]>;
257 def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1,
259 [build_vector, bitconvert]>;
261 def vsplati8_uimm8 : SplatComplexPattern<vsplat_uimm8, v16i8, 1,
263 [build_vector, bitconvert]>;
265 def vsplati8_simm5 : SplatComplexPattern<vsplat_simm5, v16i8, 1,
267 [build_vector, bitconvert]>;
269 def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1,
271 [build_vector, bitconvert]>;
273 def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1,
275 [build_vector, bitconvert]>;
277 def vsplati16_uimm5 : SplatComplexPattern<vsplat_uimm5, v8i16, 1,
279 [build_vector, bitconvert]>;
281 def vsplati16_simm5 : SplatComplexPattern<vsplat_simm5, v8i16, 1,
283 [build_vector, bitconvert]>;
285 def vsplati32_uimm2 : SplatComplexPattern<vsplat_uimm2, v4i32, 1,
287 [build_vector, bitconvert]>;
289 def vsplati32_uimm5 : SplatComplexPattern<vsplat_uimm5, v4i32, 1,
291 [build_vector, bitconvert]>;
293 def vsplati32_simm5 : SplatComplexPattern<vsplat_simm5, v4i32, 1,
295 [build_vector, bitconvert]>;
297 def vsplati64_uimm1 : SplatComplexPattern<vsplat_uimm1, v2i64, 1,
299 [build_vector, bitconvert]>;
301 def vsplati64_uimm5 : SplatComplexPattern<vsplat_uimm5, v2i64, 1,
303 [build_vector, bitconvert]>;
305 def vsplati64_uimm6 : SplatComplexPattern<vsplat_uimm6, v2i64, 1,
307 [build_vector, bitconvert]>;
309 def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1,
311 [build_vector, bitconvert]>;
313 // Any build_vector that is a constant splat with a value that is an exact
315 def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2",
316 [build_vector, bitconvert]>;
318 // Any build_vector that is a constant splat with only a consecutive sequence
319 // of left-most bits set.
320 def vsplat_maskl_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1,
322 [build_vector, bitconvert]>;
324 // Any build_vector that is a constant splat with only a consecutive sequence
325 // of right-most bits set.
326 def vsplat_maskr_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1,
328 [build_vector, bitconvert]>;
330 // Any build_vector that is a constant splat with a value that equals 1
331 // FIXME: This should be a ComplexPattern but we can't use them because the
332 // ISel generator requires the uses to have a name, but providing a name
333 // causes other errors ("used in pattern but not operand list")
334 def vsplat_imm_eq_1 : PatLeaf<(build_vector), [{
336 EVT EltTy = N->getValueType(0).getVectorElementType();
338 return selectVSplat (N, Imm) &&
339 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1;
342 def vsplati64_imm_eq_1 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{
344 SDNode *BV = N->getOperand(0).getNode();
345 EVT EltTy = N->getValueType(0).getVectorElementType();
347 return selectVSplat (BV, Imm) &&
348 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1;
351 def vbneg_b : PatFrag<(ops node:$ws, node:$wt),
352 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
353 def vbneg_h : PatFrag<(ops node:$ws, node:$wt),
354 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
355 def vbneg_w : PatFrag<(ops node:$ws, node:$wt),
356 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
357 def vbneg_d : PatFrag<(ops node:$ws, node:$wt),
358 (xor node:$ws, (shl (v2i64 vsplati64_imm_eq_1),
361 def vbset_b : PatFrag<(ops node:$ws, node:$wt),
362 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
363 def vbset_h : PatFrag<(ops node:$ws, node:$wt),
364 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
365 def vbset_w : PatFrag<(ops node:$ws, node:$wt),
366 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
367 def vbset_d : PatFrag<(ops node:$ws, node:$wt),
368 (or node:$ws, (shl (v2i64 vsplati64_imm_eq_1),
371 def fms : PatFrag<(ops node:$wd, node:$ws, node:$wt),
372 (fsub node:$wd, (fmul node:$ws, node:$wt))>;
374 def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt),
375 (add node:$wd, (mul node:$ws, node:$wt))>;
377 def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt),
378 (sub node:$wd, (mul node:$ws, node:$wt))>;
380 def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt),
381 (fmul node:$ws, (fexp2 node:$wt))>;
384 def immSExt5 : ImmLeaf<i32, [{return isInt<5>(Imm);}]>;
385 def immSExt10: ImmLeaf<i32, [{return isInt<10>(Imm);}]>;
387 // Instruction encoding.
388 class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>;
389 class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>;
390 class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>;
391 class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>;
393 class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>;
394 class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>;
395 class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>;
396 class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>;
398 class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>;
399 class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>;
400 class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>;
401 class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>;
403 class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>;
404 class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>;
405 class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>;
406 class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>;
408 class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>;
409 class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>;
410 class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>;
411 class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>;
413 class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>;
414 class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>;
415 class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>;
416 class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>;
418 class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>;
420 class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>;
422 class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>;
423 class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>;
424 class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>;
425 class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>;
427 class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>;
428 class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>;
429 class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>;
430 class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>;
432 class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>;
433 class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>;
434 class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>;
435 class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>;
437 class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>;
438 class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>;
439 class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>;
440 class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>;
442 class AVER_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010000>;
443 class AVER_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010000>;
444 class AVER_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010000>;
445 class AVER_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010000>;
447 class AVER_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010000>;
448 class AVER_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010000>;
449 class AVER_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010000>;
450 class AVER_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010000>;
452 class BCLR_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001101>;
453 class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>;
454 class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>;
455 class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>;
457 class BCLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001001>;
458 class BCLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001001>;
459 class BCLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001001>;
460 class BCLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001001>;
462 class BINSL_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001101>;
463 class BINSL_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001101>;
464 class BINSL_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001101>;
465 class BINSL_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001101>;
467 class BINSLI_B_ENC : MSA_BIT_B_FMT<0b110, 0b001001>;
468 class BINSLI_H_ENC : MSA_BIT_H_FMT<0b110, 0b001001>;
469 class BINSLI_W_ENC : MSA_BIT_W_FMT<0b110, 0b001001>;
470 class BINSLI_D_ENC : MSA_BIT_D_FMT<0b110, 0b001001>;
472 class BINSR_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001101>;
473 class BINSR_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001101>;
474 class BINSR_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001101>;
475 class BINSR_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001101>;
477 class BINSRI_B_ENC : MSA_BIT_B_FMT<0b111, 0b001001>;
478 class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>;
479 class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>;
480 class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>;
482 class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>;
484 class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>;
486 class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>;
488 class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>;
490 class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>;
491 class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>;
492 class BNEG_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001101>;
493 class BNEG_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001101>;
495 class BNEGI_B_ENC : MSA_BIT_B_FMT<0b101, 0b001001>;
496 class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>;
497 class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>;
498 class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>;
500 class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>;
501 class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>;
502 class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>;
503 class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>;
505 class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01000>;
507 class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>;
509 class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>;
511 class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>;
512 class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>;
513 class BSET_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001101>;
514 class BSET_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001101>;
516 class BSETI_B_ENC : MSA_BIT_B_FMT<0b100, 0b001001>;
517 class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>;
518 class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>;
519 class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>;
521 class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>;
522 class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>;
523 class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>;
524 class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>;
526 class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>;
528 class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>;
529 class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>;
530 class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>;
531 class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>;
533 class CEQI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000111>;
534 class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>;
535 class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>;
536 class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>;
538 class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>;
540 class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>;
541 class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>;
542 class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>;
543 class CLE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001111>;
545 class CLE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001111>;
546 class CLE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001111>;
547 class CLE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001111>;
548 class CLE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001111>;
550 class CLEI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000111>;
551 class CLEI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000111>;
552 class CLEI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000111>;
553 class CLEI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000111>;
555 class CLEI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000111>;
556 class CLEI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000111>;
557 class CLEI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000111>;
558 class CLEI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000111>;
560 class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>;
561 class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>;
562 class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>;
563 class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>;
565 class CLT_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001111>;
566 class CLT_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001111>;
567 class CLT_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001111>;
568 class CLT_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001111>;
570 class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>;
571 class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>;
572 class CLTI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000111>;
573 class CLTI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000111>;
575 class CLTI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000111>;
576 class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>;
577 class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>;
578 class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>;
580 class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>;
581 class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>;
582 class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>;
584 class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>;
585 class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>;
586 class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>;
588 class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>;
590 class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>;
591 class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>;
592 class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>;
593 class DIV_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010010>;
595 class DIV_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010010>;
596 class DIV_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010010>;
597 class DIV_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010010>;
598 class DIV_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010010>;
600 class DOTP_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010011>;
601 class DOTP_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010011>;
602 class DOTP_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010011>;
604 class DOTP_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010011>;
605 class DOTP_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010011>;
606 class DOTP_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010011>;
608 class DPADD_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010011>;
609 class DPADD_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010011>;
610 class DPADD_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010011>;
612 class DPADD_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010011>;
613 class DPADD_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010011>;
614 class DPADD_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010011>;
616 class DPSUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010011>;
617 class DPSUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010011>;
618 class DPSUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010011>;
620 class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>;
621 class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>;
622 class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>;
624 class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>;
625 class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>;
627 class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>;
628 class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>;
630 class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>;
631 class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>;
633 class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>;
634 class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>;
636 class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>;
637 class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>;
639 class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>;
640 class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>;
642 class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>;
643 class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>;
645 class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>;
646 class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>;
648 class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>;
649 class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>;
651 class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>;
652 class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>;
654 class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>;
655 class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>;
657 class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>;
658 class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>;
660 class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>;
661 class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>;
663 class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>;
664 class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>;
666 class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>;
667 class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>;
669 class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>;
670 class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>;
672 class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>;
673 class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>;
675 class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>;
676 class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>;
678 class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>;
679 class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>;
681 class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>;
682 class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>;
684 class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>;
685 class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>;
687 class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>;
688 class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>;
690 class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>;
691 class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>;
692 class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>;
694 class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>;
695 class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>;
697 class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>;
698 class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>;
700 class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>;
701 class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>;
703 class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>;
704 class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>;
706 class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>;
707 class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>;
709 class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>;
710 class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>;
712 class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>;
713 class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>;
715 class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>;
716 class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>;
718 class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>;
719 class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>;
721 class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>;
722 class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>;
724 class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>;
725 class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>;
727 class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>;
728 class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>;
730 class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>;
731 class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>;
733 class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>;
734 class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>;
736 class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>;
737 class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>;
739 class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>;
740 class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>;
742 class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>;
743 class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>;
745 class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>;
746 class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>;
748 class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>;
749 class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>;
751 class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>;
752 class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>;
754 class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>;
755 class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>;
757 class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>;
758 class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>;
760 class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>;
761 class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>;
763 class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>;
764 class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>;
766 class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>;
767 class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>;
769 class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>;
770 class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>;
772 class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>;
773 class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>;
775 class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>;
776 class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>;
778 class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>;
779 class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>;
781 class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>;
782 class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>;
783 class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>;
785 class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>;
786 class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>;
787 class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>;
789 class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>;
790 class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>;
791 class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>;
793 class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>;
794 class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>;
795 class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>;
797 class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>;
798 class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>;
799 class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>;
800 class ILVEV_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010100>;
802 class ILVL_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010100>;
803 class ILVL_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010100>;
804 class ILVL_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010100>;
805 class ILVL_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010100>;
807 class ILVOD_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010100>;
808 class ILVOD_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010100>;
809 class ILVOD_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010100>;
810 class ILVOD_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010100>;
812 class ILVR_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010100>;
813 class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>;
814 class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>;
815 class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>;
817 class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>;
818 class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>;
819 class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>;
821 class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>;
822 class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>;
823 class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>;
824 class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>;
826 class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>;
827 class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>;
828 class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>;
829 class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>;
831 class LDI_B_ENC : MSA_I10_FMT<0b110, 0b00, 0b000111>;
832 class LDI_H_ENC : MSA_I10_FMT<0b110, 0b01, 0b000111>;
833 class LDI_W_ENC : MSA_I10_FMT<0b110, 0b10, 0b000111>;
834 class LDI_D_ENC : MSA_I10_FMT<0b110, 0b11, 0b000111>;
836 class LSA_ENC : SPECIAL_LSA_FMT<0b000101>;
838 class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>;
839 class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>;
841 class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>;
842 class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>;
844 class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>;
845 class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>;
846 class MADDV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010010>;
847 class MADDV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010010>;
849 class MAX_A_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001110>;
850 class MAX_A_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001110>;
851 class MAX_A_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001110>;
852 class MAX_A_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001110>;
854 class MAX_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001110>;
855 class MAX_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001110>;
856 class MAX_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001110>;
857 class MAX_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001110>;
859 class MAX_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001110>;
860 class MAX_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001110>;
861 class MAX_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001110>;
862 class MAX_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001110>;
864 class MAXI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000110>;
865 class MAXI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000110>;
866 class MAXI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000110>;
867 class MAXI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000110>;
869 class MAXI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000110>;
870 class MAXI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000110>;
871 class MAXI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000110>;
872 class MAXI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000110>;
874 class MIN_A_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001110>;
875 class MIN_A_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001110>;
876 class MIN_A_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001110>;
877 class MIN_A_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001110>;
879 class MIN_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001110>;
880 class MIN_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001110>;
881 class MIN_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001110>;
882 class MIN_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001110>;
884 class MIN_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001110>;
885 class MIN_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001110>;
886 class MIN_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001110>;
887 class MIN_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001110>;
889 class MINI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000110>;
890 class MINI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000110>;
891 class MINI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000110>;
892 class MINI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000110>;
894 class MINI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000110>;
895 class MINI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000110>;
896 class MINI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000110>;
897 class MINI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000110>;
899 class MOD_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010010>;
900 class MOD_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010010>;
901 class MOD_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010010>;
902 class MOD_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010010>;
904 class MOD_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010010>;
905 class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>;
906 class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>;
907 class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>;
909 class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>;
911 class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>;
912 class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>;
914 class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>;
915 class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>;
917 class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>;
918 class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>;
919 class MSUBV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010010>;
920 class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>;
922 class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>;
923 class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>;
925 class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>;
926 class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>;
928 class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>;
929 class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>;
930 class MULV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010010>;
931 class MULV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010010>;
933 class NLOC_B_ENC : MSA_2R_FMT<0b11000010, 0b00, 0b011110>;
934 class NLOC_H_ENC : MSA_2R_FMT<0b11000010, 0b01, 0b011110>;
935 class NLOC_W_ENC : MSA_2R_FMT<0b11000010, 0b10, 0b011110>;
936 class NLOC_D_ENC : MSA_2R_FMT<0b11000010, 0b11, 0b011110>;
938 class NLZC_B_ENC : MSA_2R_FMT<0b11000011, 0b00, 0b011110>;
939 class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>;
940 class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>;
941 class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>;
943 class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>;
945 class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>;
947 class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>;
949 class ORI_B_ENC : MSA_I8_FMT<0b01, 0b000000>;
951 class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>;
952 class PCKEV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010100>;
953 class PCKEV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010100>;
954 class PCKEV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010100>;
956 class PCKOD_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010100>;
957 class PCKOD_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010100>;
958 class PCKOD_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010100>;
959 class PCKOD_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010100>;
961 class PCNT_B_ENC : MSA_2R_FMT<0b11000001, 0b00, 0b011110>;
962 class PCNT_H_ENC : MSA_2R_FMT<0b11000001, 0b01, 0b011110>;
963 class PCNT_W_ENC : MSA_2R_FMT<0b11000001, 0b10, 0b011110>;
964 class PCNT_D_ENC : MSA_2R_FMT<0b11000001, 0b11, 0b011110>;
966 class SAT_S_B_ENC : MSA_BIT_B_FMT<0b000, 0b001010>;
967 class SAT_S_H_ENC : MSA_BIT_H_FMT<0b000, 0b001010>;
968 class SAT_S_W_ENC : MSA_BIT_W_FMT<0b000, 0b001010>;
969 class SAT_S_D_ENC : MSA_BIT_D_FMT<0b000, 0b001010>;
971 class SAT_U_B_ENC : MSA_BIT_B_FMT<0b001, 0b001010>;
972 class SAT_U_H_ENC : MSA_BIT_H_FMT<0b001, 0b001010>;
973 class SAT_U_W_ENC : MSA_BIT_W_FMT<0b001, 0b001010>;
974 class SAT_U_D_ENC : MSA_BIT_D_FMT<0b001, 0b001010>;
976 class SHF_B_ENC : MSA_I8_FMT<0b00, 0b000010>;
977 class SHF_H_ENC : MSA_I8_FMT<0b01, 0b000010>;
978 class SHF_W_ENC : MSA_I8_FMT<0b10, 0b000010>;
980 class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>;
981 class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>;
982 class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>;
983 class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>;
985 class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>;
986 class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>;
987 class SLDI_W_ENC : MSA_ELM_W_FMT<0b0000, 0b011001>;
988 class SLDI_D_ENC : MSA_ELM_D_FMT<0b0000, 0b011001>;
990 class SLL_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001101>;
991 class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>;
992 class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>;
993 class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>;
995 class SLLI_B_ENC : MSA_BIT_B_FMT<0b000, 0b001001>;
996 class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>;
997 class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>;
998 class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>;
1000 class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>;
1001 class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>;
1002 class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>;
1003 class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>;
1005 class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>;
1006 class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>;
1007 class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>;
1008 class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>;
1010 class SRA_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001101>;
1011 class SRA_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001101>;
1012 class SRA_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001101>;
1013 class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>;
1015 class SRAI_B_ENC : MSA_BIT_B_FMT<0b001, 0b001001>;
1016 class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>;
1017 class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>;
1018 class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>;
1020 class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>;
1021 class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>;
1022 class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>;
1023 class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>;
1025 class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>;
1026 class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>;
1027 class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>;
1028 class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>;
1030 class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>;
1031 class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>;
1032 class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>;
1033 class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>;
1035 class SRLI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001001>;
1036 class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>;
1037 class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>;
1038 class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>;
1040 class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>;
1041 class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>;
1042 class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>;
1043 class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>;
1045 class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>;
1046 class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>;
1047 class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>;
1048 class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>;
1050 class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>;
1051 class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>;
1052 class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>;
1053 class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>;
1055 class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>;
1056 class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>;
1057 class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>;
1058 class SUBS_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010001>;
1060 class SUBS_U_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010001>;
1061 class SUBS_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010001>;
1062 class SUBS_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010001>;
1063 class SUBS_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010001>;
1065 class SUBSUS_U_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010001>;
1066 class SUBSUS_U_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010001>;
1067 class SUBSUS_U_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010001>;
1068 class SUBSUS_U_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010001>;
1070 class SUBSUU_S_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010001>;
1071 class SUBSUU_S_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010001>;
1072 class SUBSUU_S_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010001>;
1073 class SUBSUU_S_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010001>;
1075 class SUBV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001110>;
1076 class SUBV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001110>;
1077 class SUBV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001110>;
1078 class SUBV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001110>;
1080 class SUBVI_B_ENC : MSA_I5_FMT<0b001, 0b00, 0b000110>;
1081 class SUBVI_H_ENC : MSA_I5_FMT<0b001, 0b01, 0b000110>;
1082 class SUBVI_W_ENC : MSA_I5_FMT<0b001, 0b10, 0b000110>;
1083 class SUBVI_D_ENC : MSA_I5_FMT<0b001, 0b11, 0b000110>;
1085 class VSHF_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010101>;
1086 class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>;
1087 class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>;
1088 class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>;
1090 class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>;
1092 class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>;
1094 // Instruction desc.
1095 class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1096 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1097 InstrItinClass itin = NoItinerary> {
1098 dag OutOperandList = (outs ROWD:$wd);
1099 dag InOperandList = (ins ROWS:$ws, vsplat_uimm3:$m);
1100 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1101 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, vsplat_uimm_pow2:$m))];
1102 InstrItinClass Itinerary = itin;
1105 class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1106 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1107 InstrItinClass itin = NoItinerary> {
1108 dag OutOperandList = (outs ROWD:$wd);
1109 dag InOperandList = (ins ROWS:$ws, vsplat_uimm4:$m);
1110 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1111 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, vsplat_uimm_pow2:$m))];
1112 InstrItinClass Itinerary = itin;
1115 class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1116 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1117 InstrItinClass itin = NoItinerary> {
1118 dag OutOperandList = (outs ROWD:$wd);
1119 dag InOperandList = (ins ROWS:$ws, vsplat_uimm5:$m);
1120 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1121 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, vsplat_uimm_pow2:$m))];
1122 InstrItinClass Itinerary = itin;
1125 class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1126 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1127 InstrItinClass itin = NoItinerary> {
1128 dag OutOperandList = (outs ROWD:$wd);
1129 dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m);
1130 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1131 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, vsplat_uimm_pow2:$m))];
1132 InstrItinClass Itinerary = itin;
1135 // This class is deprecated and will be removed soon.
1136 class MSA_BIT_B_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1137 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1138 InstrItinClass itin = NoItinerary> {
1139 dag OutOperandList = (outs ROWD:$wd);
1140 dag InOperandList = (ins ROWS:$ws, uimm3:$m);
1141 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1142 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt3:$m))];
1143 InstrItinClass Itinerary = itin;
1146 // This class is deprecated and will be removed soon.
1147 class MSA_BIT_H_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1148 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1149 InstrItinClass itin = NoItinerary> {
1150 dag OutOperandList = (outs ROWD:$wd);
1151 dag InOperandList = (ins ROWS:$ws, uimm4:$m);
1152 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1153 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt4:$m))];
1154 InstrItinClass Itinerary = itin;
1157 // This class is deprecated and will be removed soon.
1158 class MSA_BIT_W_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1159 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1160 InstrItinClass itin = NoItinerary> {
1161 dag OutOperandList = (outs ROWD:$wd);
1162 dag InOperandList = (ins ROWS:$ws, uimm5:$m);
1163 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1164 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt5:$m))];
1165 InstrItinClass Itinerary = itin;
1168 // This class is deprecated and will be removed soon.
1169 class MSA_BIT_D_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1170 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1171 InstrItinClass itin = NoItinerary> {
1172 dag OutOperandList = (outs ROWD:$wd);
1173 dag InOperandList = (ins ROWS:$ws, uimm6:$m);
1174 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1175 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt6:$m))];
1176 InstrItinClass Itinerary = itin;
1179 class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty,
1180 ComplexPattern Mask, RegisterOperand ROWD,
1181 RegisterOperand ROWS = ROWD,
1182 InstrItinClass itin = NoItinerary> {
1183 dag OutOperandList = (outs ROWD:$wd);
1184 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, vsplat_uimm8:$m);
1185 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1186 list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$wd_in),
1188 InstrItinClass Itinerary = itin;
1189 string Constraints = "$wd = $wd_in";
1192 class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty,
1193 RegisterOperand ROWD,
1194 RegisterOperand ROWS = ROWD,
1195 InstrItinClass itin = NoItinerary> :
1196 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskl_bits, ROWD, ROWS, itin>;
1198 class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty,
1199 RegisterOperand ROWD,
1200 RegisterOperand ROWS = ROWD,
1201 InstrItinClass itin = NoItinerary> :
1202 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskr_bits, ROWD, ROWS, itin>;
1204 class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1205 SplatComplexPattern SplatImm,
1206 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1207 InstrItinClass itin = NoItinerary> {
1208 dag OutOperandList = (outs ROWD:$wd);
1209 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m);
1210 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1211 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))];
1212 InstrItinClass Itinerary = itin;
1215 class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1216 ValueType VecTy, RegisterOperand ROD,
1217 RegisterOperand ROWS,
1218 InstrItinClass itin = NoItinerary> {
1219 dag OutOperandList = (outs ROD:$rd);
1220 dag InOperandList = (ins ROWS:$ws, uimm4:$n);
1221 string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]");
1222 list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), immZExt4:$n))];
1223 InstrItinClass Itinerary = itin;
1226 class MSA_ELM_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1227 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1228 InstrItinClass itin = NoItinerary> {
1229 dag OutOperandList = (outs ROWD:$wd);
1230 dag InOperandList = (ins ROWS:$ws, uimm4:$n);
1231 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1232 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt4:$n))];
1233 InstrItinClass Itinerary = itin;
1236 class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy,
1237 RegisterClass RCD, RegisterClass RCWS> :
1238 MipsPseudo<(outs RCD:$wd), (ins RCWS:$ws, uimm4:$n),
1239 [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), immZExt4:$n))]> {
1240 bit usesCustomInserter = 1;
1243 class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1244 SplatComplexPattern SplatImm, RegisterOperand ROWD,
1245 RegisterOperand ROWS = ROWD,
1246 InstrItinClass itin = NoItinerary> {
1247 dag OutOperandList = (outs ROWD:$wd);
1248 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm);
1249 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm");
1250 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))];
1251 InstrItinClass Itinerary = itin;
1254 class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1255 SplatComplexPattern SplatImm, RegisterOperand ROWD,
1256 RegisterOperand ROWS = ROWD,
1257 InstrItinClass itin = NoItinerary> {
1258 dag OutOperandList = (outs ROWD:$wd);
1259 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8);
1260 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1261 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))];
1262 InstrItinClass Itinerary = itin;
1265 // This class is deprecated and will be removed in the next few patches
1266 class MSA_I8_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1267 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1268 InstrItinClass itin = NoItinerary> {
1269 dag OutOperandList = (outs ROWD:$wd);
1270 dag InOperandList = (ins ROWS:$ws, uimm8:$u8);
1271 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1272 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt8:$u8))];
1273 InstrItinClass Itinerary = itin;
1276 class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1277 RegisterOperand ROWS = ROWD,
1278 InstrItinClass itin = NoItinerary> {
1279 dag OutOperandList = (outs ROWD:$wd);
1280 dag InOperandList = (ins ROWS:$ws, uimm8:$u8);
1281 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1282 list<dag> Pattern = [(set ROWD:$wd, (MipsSHF immZExt8:$u8, ROWS:$ws))];
1283 InstrItinClass Itinerary = itin;
1286 class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1287 InstrItinClass itin = NoItinerary> {
1288 dag OutOperandList = (outs ROWD:$wd);
1289 dag InOperandList = (ins vsplat_simm10:$s10);
1290 string AsmString = !strconcat(instr_asm, "\t$wd, $s10");
1291 // LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp
1292 list<dag> Pattern = [];
1293 bit hasSideEffects = 0;
1294 InstrItinClass Itinerary = itin;
1297 class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1298 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1299 InstrItinClass itin = NoItinerary> {
1300 dag OutOperandList = (outs ROWD:$wd);
1301 dag InOperandList = (ins ROWS:$ws);
1302 string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1303 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1304 InstrItinClass Itinerary = itin;
1307 class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT,
1308 SDPatternOperator OpNode, RegisterOperand ROWD,
1309 RegisterOperand ROS = ROWD,
1310 InstrItinClass itin = NoItinerary> {
1311 dag OutOperandList = (outs ROWD:$wd);
1312 dag InOperandList = (ins ROS:$rs);
1313 string AsmString = !strconcat(instr_asm, "\t$wd, $rs");
1314 list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))];
1315 InstrItinClass Itinerary = itin;
1318 class MSA_2R_FILL_PSEUDO_BASE<ValueType VT, SDPatternOperator OpNode,
1319 RegisterClass RCWD, RegisterClass RCWS = RCWD> :
1320 MipsPseudo<(outs RCWD:$wd), (ins RCWS:$fs),
1321 [(set RCWD:$wd, (OpNode RCWS:$fs))]> {
1322 let usesCustomInserter = 1;
1325 class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1326 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1327 InstrItinClass itin = NoItinerary> {
1328 dag OutOperandList = (outs ROWD:$wd);
1329 dag InOperandList = (ins ROWS:$ws);
1330 string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1331 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1332 InstrItinClass Itinerary = itin;
1335 class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1336 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1337 RegisterOperand ROWT = ROWD,
1338 InstrItinClass itin = NoItinerary> {
1339 dag OutOperandList = (outs ROWD:$wd);
1340 dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1341 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1342 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1343 InstrItinClass Itinerary = itin;
1346 class MSA_3R_BINSX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1347 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1348 RegisterOperand ROWT = ROWD,
1349 InstrItinClass itin = NoItinerary> {
1350 dag OutOperandList = (outs ROWD:$wd);
1351 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1352 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1353 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1355 string Constraints = "$wd = $wd_in";
1356 InstrItinClass Itinerary = itin;
1359 class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1360 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1361 InstrItinClass itin = NoItinerary> {
1362 dag OutOperandList = (outs ROWD:$wd);
1363 dag InOperandList = (ins ROWS:$ws, GPR32:$rt);
1364 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1365 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32:$rt))];
1366 InstrItinClass Itinerary = itin;
1369 class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1370 RegisterOperand ROWS = ROWD,
1371 RegisterOperand ROWT = ROWD,
1372 InstrItinClass itin = NoItinerary> {
1373 dag OutOperandList = (outs ROWD:$wd);
1374 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1375 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1376 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws,
1378 string Constraints = "$wd = $wd_in";
1379 InstrItinClass Itinerary = itin;
1382 class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1383 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1384 InstrItinClass itin = NoItinerary> {
1385 dag OutOperandList = (outs ROWD:$wd);
1386 dag InOperandList = (ins ROWS:$ws, GPR32:$rt);
1387 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1388 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32:$rt))];
1389 InstrItinClass Itinerary = itin;
1392 class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1393 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1394 RegisterOperand ROWT = ROWD,
1395 InstrItinClass itin = NoItinerary> {
1396 dag OutOperandList = (outs ROWD:$wd);
1397 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1398 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1399 list<dag> Pattern = [(set ROWD:$wd,
1400 (OpNode ROWD:$wd_in, ROWS:$ws, ROWT:$wt))];
1401 InstrItinClass Itinerary = itin;
1402 string Constraints = "$wd = $wd_in";
1405 class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1406 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1407 RegisterOperand ROWT = ROWD,
1408 InstrItinClass itin = NoItinerary> :
1409 MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1411 class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1412 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1413 RegisterOperand ROWT = ROWD,
1414 InstrItinClass itin = NoItinerary> :
1415 MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1417 class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> {
1418 dag OutOperandList = (outs);
1419 dag InOperandList = (ins ROWD:$wt, brtarget:$offset);
1420 string AsmString = !strconcat(instr_asm, "\t$wt, $offset");
1421 list<dag> Pattern = [];
1422 InstrItinClass Itinerary = IIBranch;
1424 bit isTerminator = 1;
1425 bit hasDelaySlot = 1;
1426 list<Register> Defs = [AT];
1429 class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1430 RegisterOperand ROWD, RegisterOperand ROS,
1431 InstrItinClass itin = NoItinerary> {
1432 dag OutOperandList = (outs ROWD:$wd);
1433 dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, uimm6:$n);
1434 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs");
1435 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
1438 InstrItinClass Itinerary = itin;
1439 string Constraints = "$wd = $wd_in";
1442 class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
1443 RegisterOperand ROWD, RegisterOperand ROFS> :
1444 MipsPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, uimm6:$n, ROFS:$fs),
1445 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs,
1447 bit usesCustomInserter = 1;
1448 string Constraints = "$wd = $wd_in";
1451 class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1452 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1453 InstrItinClass itin = NoItinerary> {
1454 dag OutOperandList = (outs ROWD:$wd);
1455 dag InOperandList = (ins ROWD:$wd_in, uimm6:$n, ROWS:$ws);
1456 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[0]");
1457 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
1460 InstrItinClass Itinerary = itin;
1461 string Constraints = "$wd = $wd_in";
1464 class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1465 RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1466 RegisterOperand ROWT = ROWD,
1467 InstrItinClass itin = NoItinerary> {
1468 dag OutOperandList = (outs ROWD:$wd);
1469 dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1470 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1471 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1472 InstrItinClass Itinerary = itin;
1475 class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm,
1476 RegisterOperand ROWD,
1477 RegisterOperand ROWS = ROWD,
1478 InstrItinClass itin = NoItinerary> {
1479 dag OutOperandList = (outs ROWD:$wd);
1480 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n);
1481 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1482 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws,
1484 InstrItinClass Itinerary = itin;
1487 class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD,
1488 RegisterOperand ROWS = ROWD,
1489 RegisterOperand ROWT = ROWD> :
1490 MipsPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt),
1491 [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>;
1493 class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>,
1495 class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>,
1497 class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>,
1499 class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>,
1502 class ADDS_A_B_DESC : MSA_3R_DESC_BASE<"adds_a.b", int_mips_adds_a_b,
1503 MSA128BOpnd>, IsCommutable;
1504 class ADDS_A_H_DESC : MSA_3R_DESC_BASE<"adds_a.h", int_mips_adds_a_h,
1505 MSA128HOpnd>, IsCommutable;
1506 class ADDS_A_W_DESC : MSA_3R_DESC_BASE<"adds_a.w", int_mips_adds_a_w,
1507 MSA128WOpnd>, IsCommutable;
1508 class ADDS_A_D_DESC : MSA_3R_DESC_BASE<"adds_a.d", int_mips_adds_a_d,
1509 MSA128DOpnd>, IsCommutable;
1511 class ADDS_S_B_DESC : MSA_3R_DESC_BASE<"adds_s.b", int_mips_adds_s_b,
1512 MSA128BOpnd>, IsCommutable;
1513 class ADDS_S_H_DESC : MSA_3R_DESC_BASE<"adds_s.h", int_mips_adds_s_h,
1514 MSA128HOpnd>, IsCommutable;
1515 class ADDS_S_W_DESC : MSA_3R_DESC_BASE<"adds_s.w", int_mips_adds_s_w,
1516 MSA128WOpnd>, IsCommutable;
1517 class ADDS_S_D_DESC : MSA_3R_DESC_BASE<"adds_s.d", int_mips_adds_s_d,
1518 MSA128DOpnd>, IsCommutable;
1520 class ADDS_U_B_DESC : MSA_3R_DESC_BASE<"adds_u.b", int_mips_adds_u_b,
1521 MSA128BOpnd>, IsCommutable;
1522 class ADDS_U_H_DESC : MSA_3R_DESC_BASE<"adds_u.h", int_mips_adds_u_h,
1523 MSA128HOpnd>, IsCommutable;
1524 class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w,
1525 MSA128WOpnd>, IsCommutable;
1526 class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d,
1527 MSA128DOpnd>, IsCommutable;
1529 class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable;
1530 class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable;
1531 class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable;
1532 class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable;
1534 class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5,
1536 class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5,
1538 class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5,
1540 class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5,
1543 class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>;
1544 class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128HOpnd>;
1545 class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128WOpnd>;
1546 class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128DOpnd>;
1548 class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8,
1551 class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b,
1553 class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h,
1555 class ASUB_S_W_DESC : MSA_3R_DESC_BASE<"asub_s.w", int_mips_asub_s_w,
1557 class ASUB_S_D_DESC : MSA_3R_DESC_BASE<"asub_s.d", int_mips_asub_s_d,
1560 class ASUB_U_B_DESC : MSA_3R_DESC_BASE<"asub_u.b", int_mips_asub_u_b,
1562 class ASUB_U_H_DESC : MSA_3R_DESC_BASE<"asub_u.h", int_mips_asub_u_h,
1564 class ASUB_U_W_DESC : MSA_3R_DESC_BASE<"asub_u.w", int_mips_asub_u_w,
1566 class ASUB_U_D_DESC : MSA_3R_DESC_BASE<"asub_u.d", int_mips_asub_u_d,
1569 class AVE_S_B_DESC : MSA_3R_DESC_BASE<"ave_s.b", int_mips_ave_s_b, MSA128BOpnd>,
1571 class AVE_S_H_DESC : MSA_3R_DESC_BASE<"ave_s.h", int_mips_ave_s_h, MSA128HOpnd>,
1573 class AVE_S_W_DESC : MSA_3R_DESC_BASE<"ave_s.w", int_mips_ave_s_w, MSA128WOpnd>,
1575 class AVE_S_D_DESC : MSA_3R_DESC_BASE<"ave_s.d", int_mips_ave_s_d, MSA128DOpnd>,
1578 class AVE_U_B_DESC : MSA_3R_DESC_BASE<"ave_u.b", int_mips_ave_u_b, MSA128BOpnd>,
1580 class AVE_U_H_DESC : MSA_3R_DESC_BASE<"ave_u.h", int_mips_ave_u_h, MSA128HOpnd>,
1582 class AVE_U_W_DESC : MSA_3R_DESC_BASE<"ave_u.w", int_mips_ave_u_w, MSA128WOpnd>,
1584 class AVE_U_D_DESC : MSA_3R_DESC_BASE<"ave_u.d", int_mips_ave_u_d, MSA128DOpnd>,
1587 class AVER_S_B_DESC : MSA_3R_DESC_BASE<"aver_s.b", int_mips_aver_s_b,
1588 MSA128BOpnd>, IsCommutable;
1589 class AVER_S_H_DESC : MSA_3R_DESC_BASE<"aver_s.h", int_mips_aver_s_h,
1590 MSA128HOpnd>, IsCommutable;
1591 class AVER_S_W_DESC : MSA_3R_DESC_BASE<"aver_s.w", int_mips_aver_s_w,
1592 MSA128WOpnd>, IsCommutable;
1593 class AVER_S_D_DESC : MSA_3R_DESC_BASE<"aver_s.d", int_mips_aver_s_d,
1594 MSA128DOpnd>, IsCommutable;
1596 class AVER_U_B_DESC : MSA_3R_DESC_BASE<"aver_u.b", int_mips_aver_u_b,
1597 MSA128BOpnd>, IsCommutable;
1598 class AVER_U_H_DESC : MSA_3R_DESC_BASE<"aver_u.h", int_mips_aver_u_h,
1599 MSA128HOpnd>, IsCommutable;
1600 class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w,
1601 MSA128WOpnd>, IsCommutable;
1602 class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d,
1603 MSA128DOpnd>, IsCommutable;
1605 class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", int_mips_bclr_b, MSA128BOpnd>;
1606 class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", int_mips_bclr_h, MSA128HOpnd>;
1607 class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", int_mips_bclr_w, MSA128WOpnd>;
1608 class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", int_mips_bclr_d, MSA128DOpnd>;
1610 class BCLRI_B_DESC : MSA_BIT_B_X_DESC_BASE<"bclri.b", int_mips_bclri_b,
1612 class BCLRI_H_DESC : MSA_BIT_H_X_DESC_BASE<"bclri.h", int_mips_bclri_h,
1614 class BCLRI_W_DESC : MSA_BIT_W_X_DESC_BASE<"bclri.w", int_mips_bclri_w,
1616 class BCLRI_D_DESC : MSA_BIT_D_X_DESC_BASE<"bclri.d", int_mips_bclri_d,
1619 class BINSL_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.b", int_mips_binsl_b,
1621 class BINSL_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.h", int_mips_binsl_h,
1623 class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w,
1625 class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d,
1628 class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, MSA128BOpnd>;
1629 class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, MSA128HOpnd>;
1630 class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, MSA128WOpnd>;
1631 class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, MSA128DOpnd>;
1633 class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b,
1635 class BINSR_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.h", int_mips_binsr_h,
1637 class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w,
1639 class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d,
1642 class BINSRI_B_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, MSA128BOpnd>;
1643 class BINSRI_H_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, MSA128HOpnd>;
1644 class BINSRI_W_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, MSA128WOpnd>;
1645 class BINSRI_D_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, MSA128DOpnd>;
1648 dag OutOperandList = (outs MSA128BOpnd:$wd);
1649 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1651 string AsmString = "bmnz.v\t$wd, $ws, $wt";
1652 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
1654 MSA128BOpnd:$wd_in))];
1655 InstrItinClass Itinerary = NoItinerary;
1656 string Constraints = "$wd = $wd_in";
1659 class BMNZI_B_DESC {
1660 dag OutOperandList = (outs MSA128BOpnd:$wd);
1661 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1663 string AsmString = "bmnzi.b\t$wd, $ws, $u8";
1664 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
1666 MSA128BOpnd:$wd_in))];
1667 InstrItinClass Itinerary = NoItinerary;
1668 string Constraints = "$wd = $wd_in";
1672 dag OutOperandList = (outs MSA128BOpnd:$wd);
1673 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1675 string AsmString = "bmz.v\t$wd, $ws, $wt";
1676 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
1679 InstrItinClass Itinerary = NoItinerary;
1680 string Constraints = "$wd = $wd_in";
1684 dag OutOperandList = (outs MSA128BOpnd:$wd);
1685 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1687 string AsmString = "bmzi.b\t$wd, $ws, $u8";
1688 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
1691 InstrItinClass Itinerary = NoItinerary;
1692 string Constraints = "$wd = $wd_in";
1695 class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg_b, MSA128BOpnd>;
1696 class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg_h, MSA128HOpnd>;
1697 class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg_w, MSA128WOpnd>;
1698 class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg_d, MSA128DOpnd>;
1700 class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", xor, MSA128BOpnd>;
1701 class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", xor, MSA128HOpnd>;
1702 class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", xor, MSA128WOpnd>;
1703 class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", xor, MSA128DOpnd>;
1705 class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>;
1706 class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>;
1707 class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>;
1708 class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>;
1710 class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>;
1713 dag OutOperandList = (outs MSA128BOpnd:$wd);
1714 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1716 string AsmString = "bsel.v\t$wd, $ws, $wt";
1717 list<dag> Pattern = [(set MSA128BOpnd:$wd,
1718 (vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1720 InstrItinClass Itinerary = NoItinerary;
1721 string Constraints = "$wd = $wd_in";
1724 class BSELI_B_DESC {
1725 dag OutOperandList = (outs MSA128BOpnd:$wd);
1726 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1728 string AsmString = "bseli.b\t$wd, $ws, $u8";
1729 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in,
1731 vsplati8_uimm8:$u8))];
1732 InstrItinClass Itinerary = NoItinerary;
1733 string Constraints = "$wd = $wd_in";
1736 class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", vbset_b, MSA128BOpnd>;
1737 class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", vbset_h, MSA128HOpnd>;
1738 class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", vbset_w, MSA128WOpnd>;
1739 class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", vbset_d, MSA128DOpnd>;
1741 class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", or, MSA128BOpnd>;
1742 class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", or, MSA128HOpnd>;
1743 class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", or, MSA128WOpnd>;
1744 class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", or, MSA128DOpnd>;
1746 class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>;
1747 class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>;
1748 class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>;
1749 class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>;
1751 class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>;
1753 class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>,
1755 class CEQ_H_DESC : MSA_3R_DESC_BASE<"ceq.h", vseteq_v8i16, MSA128HOpnd>,
1757 class CEQ_W_DESC : MSA_3R_DESC_BASE<"ceq.w", vseteq_v4i32, MSA128WOpnd>,
1759 class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq.d", vseteq_v2i64, MSA128DOpnd>,
1762 class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5,
1764 class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5,
1766 class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5,
1768 class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5,
1772 dag OutOperandList = (outs GPR32Opnd:$rd);
1773 dag InOperandList = (ins MSA128CROpnd:$cs);
1774 string AsmString = "cfcmsa\t$rd, $cs";
1775 InstrItinClass Itinerary = NoItinerary;
1776 bit hasSideEffects = 1;
1779 class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>;
1780 class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", vsetle_v8i16, MSA128HOpnd>;
1781 class CLE_S_W_DESC : MSA_3R_DESC_BASE<"cle_s.w", vsetle_v4i32, MSA128WOpnd>;
1782 class CLE_S_D_DESC : MSA_3R_DESC_BASE<"cle_s.d", vsetle_v2i64, MSA128DOpnd>;
1784 class CLE_U_B_DESC : MSA_3R_DESC_BASE<"cle_u.b", vsetule_v16i8, MSA128BOpnd>;
1785 class CLE_U_H_DESC : MSA_3R_DESC_BASE<"cle_u.h", vsetule_v8i16, MSA128HOpnd>;
1786 class CLE_U_W_DESC : MSA_3R_DESC_BASE<"cle_u.w", vsetule_v4i32, MSA128WOpnd>;
1787 class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>;
1789 class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8,
1790 vsplati8_simm5, MSA128BOpnd>;
1791 class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16,
1792 vsplati16_simm5, MSA128HOpnd>;
1793 class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32,
1794 vsplati32_simm5, MSA128WOpnd>;
1795 class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64,
1796 vsplati64_simm5, MSA128DOpnd>;
1798 class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8,
1799 vsplati8_uimm5, MSA128BOpnd>;
1800 class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16,
1801 vsplati16_uimm5, MSA128HOpnd>;
1802 class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32,
1803 vsplati32_uimm5, MSA128WOpnd>;
1804 class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64,
1805 vsplati64_uimm5, MSA128DOpnd>;
1807 class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>;
1808 class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>;
1809 class CLT_S_W_DESC : MSA_3R_DESC_BASE<"clt_s.w", vsetlt_v4i32, MSA128WOpnd>;
1810 class CLT_S_D_DESC : MSA_3R_DESC_BASE<"clt_s.d", vsetlt_v2i64, MSA128DOpnd>;
1812 class CLT_U_B_DESC : MSA_3R_DESC_BASE<"clt_u.b", vsetult_v16i8, MSA128BOpnd>;
1813 class CLT_U_H_DESC : MSA_3R_DESC_BASE<"clt_u.h", vsetult_v8i16, MSA128HOpnd>;
1814 class CLT_U_W_DESC : MSA_3R_DESC_BASE<"clt_u.w", vsetult_v4i32, MSA128WOpnd>;
1815 class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>;
1817 class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8,
1818 vsplati8_simm5, MSA128BOpnd>;
1819 class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16,
1820 vsplati16_simm5, MSA128HOpnd>;
1821 class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32,
1822 vsplati32_simm5, MSA128WOpnd>;
1823 class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64,
1824 vsplati64_simm5, MSA128DOpnd>;
1826 class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8,
1827 vsplati8_uimm5, MSA128BOpnd>;
1828 class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16,
1829 vsplati16_uimm5, MSA128HOpnd>;
1830 class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32,
1831 vsplati32_uimm5, MSA128WOpnd>;
1832 class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64,
1833 vsplati64_uimm5, MSA128DOpnd>;
1835 class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8,
1836 GPR32Opnd, MSA128BOpnd>;
1837 class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16,
1838 GPR32Opnd, MSA128HOpnd>;
1839 class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32,
1840 GPR32Opnd, MSA128WOpnd>;
1842 class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8,
1843 GPR32Opnd, MSA128BOpnd>;
1844 class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16,
1845 GPR32Opnd, MSA128HOpnd>;
1846 class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32,
1847 GPR32Opnd, MSA128WOpnd>;
1849 class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, FGR32,
1851 class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64, FGR64,
1855 dag OutOperandList = (outs);
1856 dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs);
1857 string AsmString = "ctcmsa\t$cd, $rs";
1858 InstrItinClass Itinerary = NoItinerary;
1859 bit hasSideEffects = 1;
1862 class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>;
1863 class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128HOpnd>;
1864 class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128WOpnd>;
1865 class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128DOpnd>;
1867 class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128BOpnd>;
1868 class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128HOpnd>;
1869 class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128WOpnd>;
1870 class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128DOpnd>;
1872 class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h,
1873 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1875 class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w,
1876 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1878 class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d,
1879 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1882 class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h,
1883 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1885 class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w,
1886 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1888 class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d,
1889 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1892 class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h,
1893 MSA128HOpnd, MSA128BOpnd,
1894 MSA128BOpnd>, IsCommutable;
1895 class DPADD_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.w", int_mips_dpadd_s_w,
1896 MSA128WOpnd, MSA128HOpnd,
1897 MSA128HOpnd>, IsCommutable;
1898 class DPADD_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.d", int_mips_dpadd_s_d,
1899 MSA128DOpnd, MSA128WOpnd,
1900 MSA128WOpnd>, IsCommutable;
1902 class DPADD_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.h", int_mips_dpadd_u_h,
1903 MSA128HOpnd, MSA128BOpnd,
1904 MSA128BOpnd>, IsCommutable;
1905 class DPADD_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.w", int_mips_dpadd_u_w,
1906 MSA128WOpnd, MSA128HOpnd,
1907 MSA128HOpnd>, IsCommutable;
1908 class DPADD_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.d", int_mips_dpadd_u_d,
1909 MSA128DOpnd, MSA128WOpnd,
1910 MSA128WOpnd>, IsCommutable;
1912 class DPSUB_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.h", int_mips_dpsub_s_h,
1913 MSA128HOpnd, MSA128BOpnd,
1915 class DPSUB_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.w", int_mips_dpsub_s_w,
1916 MSA128WOpnd, MSA128HOpnd,
1918 class DPSUB_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.d", int_mips_dpsub_s_d,
1919 MSA128DOpnd, MSA128WOpnd,
1922 class DPSUB_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.h", int_mips_dpsub_u_h,
1923 MSA128HOpnd, MSA128BOpnd,
1925 class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w,
1926 MSA128WOpnd, MSA128HOpnd,
1928 class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d,
1929 MSA128DOpnd, MSA128WOpnd,
1932 class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>,
1934 class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>,
1937 class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>,
1939 class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>,
1942 class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>,
1944 class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>,
1947 class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w,
1949 class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d,
1952 class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>;
1953 class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>;
1955 class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>;
1956 class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>;
1958 class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>,
1960 class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>,
1963 class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>,
1965 class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>,
1968 class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>,
1970 class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>,
1973 class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>,
1975 class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>,
1978 class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>,
1980 class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>,
1983 class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>,
1985 class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>,
1988 class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>,
1990 class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>,
1993 class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>;
1994 class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>;
1996 class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h,
1997 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
1998 class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w,
1999 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
2001 // The fexp2.df instruction multiplies the first operand by 2 to the power of
2002 // the second operand. We therefore need a pseudo-insn in order to invent the
2003 // 1.0 when we only need to match ISD::FEXP2.
2004 class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>;
2005 class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>;
2006 let usesCustomInserter = 1 in {
2007 class FEXP2_W_1_PSEUDO_DESC :
2008 MipsPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws),
2009 [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>;
2010 class FEXP2_D_1_PSEUDO_DESC :
2011 MipsPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws),
2012 [(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>;
2015 class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w,
2016 MSA128WOpnd, MSA128HOpnd>;
2017 class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d,
2018 MSA128DOpnd, MSA128WOpnd>;
2020 class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w,
2021 MSA128WOpnd, MSA128HOpnd>;
2022 class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d,
2023 MSA128DOpnd, MSA128WOpnd>;
2025 class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>;
2026 class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>;
2028 class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>;
2029 class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>;
2031 class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w,
2032 MSA128WOpnd, MSA128HOpnd>;
2033 class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d,
2034 MSA128DOpnd, MSA128WOpnd>;
2036 class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w,
2037 MSA128WOpnd, MSA128HOpnd>;
2038 class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d,
2039 MSA128DOpnd, MSA128WOpnd>;
2041 class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8,
2042 MSA128BOpnd, GPR32Opnd>;
2043 class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16,
2044 MSA128HOpnd, GPR32Opnd>;
2045 class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32,
2046 MSA128WOpnd, GPR32Opnd>;
2048 class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v4f32, vsplatf32, MSA128W,
2050 class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v2f64, vsplatf64, MSA128D,
2053 class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>;
2054 class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>;
2056 class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>;
2057 class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>;
2059 class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>;
2060 class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>;
2062 class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w,
2064 class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d,
2067 class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>;
2068 class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>;
2070 class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w,
2072 class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d,
2075 class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", fms, MSA128WOpnd>;
2076 class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", fms, MSA128DOpnd>;
2078 class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>;
2079 class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>;
2081 class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>;
2082 class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>;
2084 class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>;
2085 class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>;
2087 class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w,
2089 class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d,
2092 class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>;
2093 class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>;
2095 class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>;
2096 class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>;
2098 class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>;
2099 class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>;
2101 class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>;
2102 class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>;
2104 class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>;
2105 class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>;
2107 class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>;
2108 class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>;
2110 class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>;
2111 class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>;
2113 class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>;
2114 class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>;
2116 class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w,
2118 class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d,
2121 class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w,
2123 class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d,
2126 class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w,
2128 class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d,
2131 class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w,
2133 class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d,
2136 class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w,
2138 class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d,
2141 class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w,
2143 class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d,
2146 class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w,
2148 class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d,
2151 class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h,
2152 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
2153 class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w,
2154 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
2156 class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint,
2158 class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint,
2161 class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint,
2163 class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint,
2166 class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h,
2167 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2168 class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w,
2169 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2170 class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d,
2171 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2173 class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h,
2174 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2175 class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w,
2176 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2177 class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d,
2178 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2180 class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h,
2181 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2182 class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w,
2183 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2184 class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d,
2185 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2187 class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h,
2188 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2189 class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w,
2190 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2191 class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d,
2192 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2194 class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", MipsILVEV, MSA128BOpnd>;
2195 class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", MipsILVEV, MSA128HOpnd>;
2196 class ILVEV_W_DESC : MSA_3R_DESC_BASE<"ilvev.w", MipsILVEV, MSA128WOpnd>;
2197 class ILVEV_D_DESC : MSA_3R_DESC_BASE<"ilvev.d", MipsILVEV, MSA128DOpnd>;
2199 class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>;
2200 class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>;
2201 class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>;
2202 class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>;
2204 class ILVOD_B_DESC : MSA_3R_DESC_BASE<"ilvod.b", MipsILVOD, MSA128BOpnd>;
2205 class ILVOD_H_DESC : MSA_3R_DESC_BASE<"ilvod.h", MipsILVOD, MSA128HOpnd>;
2206 class ILVOD_W_DESC : MSA_3R_DESC_BASE<"ilvod.w", MipsILVOD, MSA128WOpnd>;
2207 class ILVOD_D_DESC : MSA_3R_DESC_BASE<"ilvod.d", MipsILVOD, MSA128DOpnd>;
2209 class ILVR_B_DESC : MSA_3R_DESC_BASE<"ilvr.b", MipsILVR, MSA128BOpnd>;
2210 class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>;
2211 class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>;
2212 class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>;
2214 class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8,
2215 MSA128BOpnd, GPR32Opnd>;
2216 class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16,
2217 MSA128HOpnd, GPR32Opnd>;
2218 class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32,
2219 MSA128WOpnd, GPR32Opnd>;
2221 class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32,
2222 MSA128WOpnd, FGR32Opnd>;
2223 class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64,
2224 MSA128DOpnd, FGR64Opnd>;
2226 class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", int_mips_insve_b,
2228 class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", int_mips_insve_h,
2230 class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", int_mips_insve_w,
2232 class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", int_mips_insve_d,
2235 class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2236 ValueType TyNode, RegisterOperand ROWD,
2237 Operand MemOpnd = mem, ComplexPattern Addr = addrRegImm,
2238 InstrItinClass itin = NoItinerary> {
2239 dag OutOperandList = (outs ROWD:$wd);
2240 dag InOperandList = (ins MemOpnd:$addr);
2241 string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2242 list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))];
2243 InstrItinClass Itinerary = itin;
2244 string DecoderMethod = "DecodeMSA128Mem";
2247 class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd>;
2248 class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd>;
2249 class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd>;
2250 class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd>;
2252 class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>;
2253 class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>;
2254 class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>;
2255 class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>;
2258 dag OutOperandList = (outs GPR32Opnd:$rd);
2259 dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, uimm2:$sa);
2260 string AsmString = "lsa\t$rd, $rs, $rt, $sa";
2261 list<dag> Pattern = [(set GPR32Opnd:$rd, (add GPR32Opnd:$rs,
2263 immZExt2Lsa:$sa)))];
2264 InstrItinClass Itinerary = NoItinerary;
2267 class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h,
2269 class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w,
2272 class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h,
2274 class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w,
2277 class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", muladd, MSA128BOpnd>;
2278 class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", muladd, MSA128HOpnd>;
2279 class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", muladd, MSA128WOpnd>;
2280 class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", muladd, MSA128DOpnd>;
2282 class MAX_A_B_DESC : MSA_3R_DESC_BASE<"max_a.b", int_mips_max_a_b, MSA128BOpnd>;
2283 class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>;
2284 class MAX_A_W_DESC : MSA_3R_DESC_BASE<"max_a.w", int_mips_max_a_w, MSA128WOpnd>;
2285 class MAX_A_D_DESC : MSA_3R_DESC_BASE<"max_a.d", int_mips_max_a_d, MSA128DOpnd>;
2287 class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", MipsVSMax, MSA128BOpnd>;
2288 class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", MipsVSMax, MSA128HOpnd>;
2289 class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", MipsVSMax, MSA128WOpnd>;
2290 class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", MipsVSMax, MSA128DOpnd>;
2292 class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", MipsVUMax, MSA128BOpnd>;
2293 class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", MipsVUMax, MSA128HOpnd>;
2294 class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", MipsVUMax, MSA128WOpnd>;
2295 class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", MipsVUMax, MSA128DOpnd>;
2297 class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", MipsVSMax, vsplati8_simm5,
2299 class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", MipsVSMax, vsplati16_simm5,
2301 class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", MipsVSMax, vsplati32_simm5,
2303 class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", MipsVSMax, vsplati64_simm5,
2306 class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", MipsVUMax, vsplati8_uimm5,
2308 class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", MipsVUMax, vsplati16_uimm5,
2310 class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", MipsVUMax, vsplati32_uimm5,
2312 class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", MipsVUMax, vsplati64_uimm5,
2315 class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>;
2316 class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>;
2317 class MIN_A_W_DESC : MSA_3R_DESC_BASE<"min_a.w", int_mips_min_a_w, MSA128WOpnd>;
2318 class MIN_A_D_DESC : MSA_3R_DESC_BASE<"min_a.d", int_mips_min_a_d, MSA128DOpnd>;
2320 class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", MipsVSMin, MSA128BOpnd>;
2321 class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", MipsVSMin, MSA128HOpnd>;
2322 class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", MipsVSMin, MSA128WOpnd>;
2323 class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", MipsVSMin, MSA128DOpnd>;
2325 class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", MipsVUMin, MSA128BOpnd>;
2326 class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", MipsVUMin, MSA128HOpnd>;
2327 class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", MipsVUMin, MSA128WOpnd>;
2328 class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", MipsVUMin, MSA128DOpnd>;
2330 class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", MipsVSMin, vsplati8_simm5,
2332 class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", MipsVSMin, vsplati16_simm5,
2334 class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", MipsVSMin, vsplati32_simm5,
2336 class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", MipsVSMin, vsplati64_simm5,
2339 class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", MipsVUMin, vsplati8_uimm5,
2341 class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", MipsVUMin, vsplati16_uimm5,
2343 class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", MipsVUMin, vsplati32_uimm5,
2345 class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", MipsVUMin, vsplati64_uimm5,
2348 class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", srem, MSA128BOpnd>;
2349 class MOD_S_H_DESC : MSA_3R_DESC_BASE<"mod_s.h", srem, MSA128HOpnd>;
2350 class MOD_S_W_DESC : MSA_3R_DESC_BASE<"mod_s.w", srem, MSA128WOpnd>;
2351 class MOD_S_D_DESC : MSA_3R_DESC_BASE<"mod_s.d", srem, MSA128DOpnd>;
2353 class MOD_U_B_DESC : MSA_3R_DESC_BASE<"mod_u.b", urem, MSA128BOpnd>;
2354 class MOD_U_H_DESC : MSA_3R_DESC_BASE<"mod_u.h", urem, MSA128HOpnd>;
2355 class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", urem, MSA128WOpnd>;
2356 class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", urem, MSA128DOpnd>;
2359 dag OutOperandList = (outs MSA128BOpnd:$wd);
2360 dag InOperandList = (ins MSA128BOpnd:$ws);
2361 string AsmString = "move.v\t$wd, $ws";
2362 list<dag> Pattern = [];
2363 InstrItinClass Itinerary = NoItinerary;
2366 class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h,
2368 class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w,
2371 class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h,
2373 class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w,
2376 class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", mulsub, MSA128BOpnd>;
2377 class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", mulsub, MSA128HOpnd>;
2378 class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", mulsub, MSA128WOpnd>;
2379 class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", mulsub, MSA128DOpnd>;
2381 class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h,
2383 class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w,
2386 class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h,
2388 class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w,
2391 class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128BOpnd>;
2392 class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128HOpnd>;
2393 class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", mul, MSA128WOpnd>;
2394 class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", mul, MSA128DOpnd>;
2396 class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>;
2397 class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>;
2398 class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>;
2399 class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>;
2401 class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", ctlz, MSA128BOpnd>;
2402 class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128HOpnd>;
2403 class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128WOpnd>;
2404 class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128DOpnd>;
2406 class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128BOpnd>;
2407 class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128HOpnd>;
2408 class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128WOpnd>;
2409 class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128DOpnd>;
2411 class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8,
2414 class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128BOpnd>;
2415 class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128HOpnd>;
2416 class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128WOpnd>;
2417 class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128DOpnd>;
2419 class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>;
2421 class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128BOpnd>;
2422 class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128HOpnd>;
2423 class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", MipsPCKEV, MSA128WOpnd>;
2424 class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", MipsPCKEV, MSA128DOpnd>;
2426 class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", MipsPCKOD, MSA128BOpnd>;
2427 class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", MipsPCKOD, MSA128HOpnd>;
2428 class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>;
2429 class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>;
2431 class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>;
2432 class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>;
2433 class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>;
2434 class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>;
2436 class SAT_S_B_DESC : MSA_BIT_B_X_DESC_BASE<"sat_s.b", int_mips_sat_s_b,
2438 class SAT_S_H_DESC : MSA_BIT_H_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h,
2440 class SAT_S_W_DESC : MSA_BIT_W_X_DESC_BASE<"sat_s.w", int_mips_sat_s_w,
2442 class SAT_S_D_DESC : MSA_BIT_D_X_DESC_BASE<"sat_s.d", int_mips_sat_s_d,
2445 class SAT_U_B_DESC : MSA_BIT_B_X_DESC_BASE<"sat_u.b", int_mips_sat_u_b,
2447 class SAT_U_H_DESC : MSA_BIT_H_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h,
2449 class SAT_U_W_DESC : MSA_BIT_W_X_DESC_BASE<"sat_u.w", int_mips_sat_u_w,
2451 class SAT_U_D_DESC : MSA_BIT_D_X_DESC_BASE<"sat_u.d", int_mips_sat_u_d,
2454 class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>;
2455 class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>;
2456 class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>;
2458 class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>;
2459 class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>;
2460 class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>;
2461 class SLD_D_DESC : MSA_3R_SLD_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>;
2463 class SLDI_B_DESC : MSA_ELM_DESC_BASE<"sldi.b", int_mips_sldi_b, MSA128BOpnd>;
2464 class SLDI_H_DESC : MSA_ELM_DESC_BASE<"sldi.h", int_mips_sldi_h, MSA128HOpnd>;
2465 class SLDI_W_DESC : MSA_ELM_DESC_BASE<"sldi.w", int_mips_sldi_w, MSA128WOpnd>;
2466 class SLDI_D_DESC : MSA_ELM_DESC_BASE<"sldi.d", int_mips_sldi_d, MSA128DOpnd>;
2468 class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128BOpnd>;
2469 class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128HOpnd>;
2470 class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>;
2471 class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>;
2473 class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3,
2475 class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4,
2477 class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5,
2479 class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6,
2482 class SPLAT_B_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.b", vsplati8_elt,
2484 class SPLAT_H_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.h", vsplati16_elt,
2486 class SPLAT_W_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.w", vsplati32_elt,
2488 class SPLAT_D_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.d", vsplati64_elt,
2491 class SPLATI_B_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.b", vsplati8_uimm4,
2493 class SPLATI_H_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.h", vsplati16_uimm3,
2495 class SPLATI_W_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.w", vsplati32_uimm2,
2497 class SPLATI_D_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.d", vsplati64_uimm1,
2500 class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>;
2501 class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>;
2502 class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>;
2503 class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>;
2505 class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3,
2507 class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4,
2509 class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5,
2511 class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6,
2514 class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>;
2515 class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>;
2516 class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>;
2517 class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>;
2519 class SRARI_B_DESC : MSA_BIT_B_X_DESC_BASE<"srari.b", int_mips_srari_b,
2521 class SRARI_H_DESC : MSA_BIT_H_X_DESC_BASE<"srari.h", int_mips_srari_h,
2523 class SRARI_W_DESC : MSA_BIT_W_X_DESC_BASE<"srari.w", int_mips_srari_w,
2525 class SRARI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srari.d", int_mips_srari_d,
2528 class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>;
2529 class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>;
2530 class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>;
2531 class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>;
2533 class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3,
2535 class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4,
2537 class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5,
2539 class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6,
2542 class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>;
2543 class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>;
2544 class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>;
2545 class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>;
2547 class SRLRI_B_DESC : MSA_BIT_B_X_DESC_BASE<"srlri.b", int_mips_srlri_b,
2549 class SRLRI_H_DESC : MSA_BIT_H_X_DESC_BASE<"srlri.h", int_mips_srlri_h,
2551 class SRLRI_W_DESC : MSA_BIT_W_X_DESC_BASE<"srlri.w", int_mips_srlri_w,
2553 class SRLRI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srlri.d", int_mips_srlri_d,
2556 class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2557 ValueType TyNode, RegisterOperand ROWD,
2558 Operand MemOpnd = mem, ComplexPattern Addr = addrRegImm,
2559 InstrItinClass itin = NoItinerary> {
2560 dag OutOperandList = (outs);
2561 dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr);
2562 string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2563 list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)];
2564 InstrItinClass Itinerary = itin;
2565 string DecoderMethod = "DecodeMSA128Mem";
2568 class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd>;
2569 class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd>;
2570 class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd>;
2571 class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd>;
2573 class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b,
2575 class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h,
2577 class SUBS_S_W_DESC : MSA_3R_DESC_BASE<"subs_s.w", int_mips_subs_s_w,
2579 class SUBS_S_D_DESC : MSA_3R_DESC_BASE<"subs_s.d", int_mips_subs_s_d,
2582 class SUBS_U_B_DESC : MSA_3R_DESC_BASE<"subs_u.b", int_mips_subs_u_b,
2584 class SUBS_U_H_DESC : MSA_3R_DESC_BASE<"subs_u.h", int_mips_subs_u_h,
2586 class SUBS_U_W_DESC : MSA_3R_DESC_BASE<"subs_u.w", int_mips_subs_u_w,
2588 class SUBS_U_D_DESC : MSA_3R_DESC_BASE<"subs_u.d", int_mips_subs_u_d,
2591 class SUBSUS_U_B_DESC : MSA_3R_DESC_BASE<"subsus_u.b", int_mips_subsus_u_b,
2593 class SUBSUS_U_H_DESC : MSA_3R_DESC_BASE<"subsus_u.h", int_mips_subsus_u_h,
2595 class SUBSUS_U_W_DESC : MSA_3R_DESC_BASE<"subsus_u.w", int_mips_subsus_u_w,
2597 class SUBSUS_U_D_DESC : MSA_3R_DESC_BASE<"subsus_u.d", int_mips_subsus_u_d,
2600 class SUBSUU_S_B_DESC : MSA_3R_DESC_BASE<"subsuu_s.b", int_mips_subsuu_s_b,
2602 class SUBSUU_S_H_DESC : MSA_3R_DESC_BASE<"subsuu_s.h", int_mips_subsuu_s_h,
2604 class SUBSUU_S_W_DESC : MSA_3R_DESC_BASE<"subsuu_s.w", int_mips_subsuu_s_w,
2606 class SUBSUU_S_D_DESC : MSA_3R_DESC_BASE<"subsuu_s.d", int_mips_subsuu_s_d,
2609 class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", sub, MSA128BOpnd>;
2610 class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", sub, MSA128HOpnd>;
2611 class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128WOpnd>;
2612 class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128DOpnd>;
2614 class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5,
2616 class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5,
2618 class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5,
2620 class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5,
2623 class VSHF_B_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.b", MSA128BOpnd>;
2624 class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>;
2625 class VSHF_W_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.w", MSA128WOpnd>;
2626 class VSHF_D_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.d", MSA128DOpnd>;
2628 class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128BOpnd>;
2629 class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128HOpnd>;
2630 class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128WOpnd>;
2631 class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128DOpnd>;
2633 class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8,
2636 // Instruction defs.
2637 def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC;
2638 def ADD_A_H : ADD_A_H_ENC, ADD_A_H_DESC;
2639 def ADD_A_W : ADD_A_W_ENC, ADD_A_W_DESC;
2640 def ADD_A_D : ADD_A_D_ENC, ADD_A_D_DESC;
2642 def ADDS_A_B : ADDS_A_B_ENC, ADDS_A_B_DESC;
2643 def ADDS_A_H : ADDS_A_H_ENC, ADDS_A_H_DESC;
2644 def ADDS_A_W : ADDS_A_W_ENC, ADDS_A_W_DESC;
2645 def ADDS_A_D : ADDS_A_D_ENC, ADDS_A_D_DESC;
2647 def ADDS_S_B : ADDS_S_B_ENC, ADDS_S_B_DESC;
2648 def ADDS_S_H : ADDS_S_H_ENC, ADDS_S_H_DESC;
2649 def ADDS_S_W : ADDS_S_W_ENC, ADDS_S_W_DESC;
2650 def ADDS_S_D : ADDS_S_D_ENC, ADDS_S_D_DESC;
2652 def ADDS_U_B : ADDS_U_B_ENC, ADDS_U_B_DESC;
2653 def ADDS_U_H : ADDS_U_H_ENC, ADDS_U_H_DESC;
2654 def ADDS_U_W : ADDS_U_W_ENC, ADDS_U_W_DESC;
2655 def ADDS_U_D : ADDS_U_D_ENC, ADDS_U_D_DESC;
2657 def ADDV_B : ADDV_B_ENC, ADDV_B_DESC;
2658 def ADDV_H : ADDV_H_ENC, ADDV_H_DESC;
2659 def ADDV_W : ADDV_W_ENC, ADDV_W_DESC;
2660 def ADDV_D : ADDV_D_ENC, ADDV_D_DESC;
2662 def ADDVI_B : ADDVI_B_ENC, ADDVI_B_DESC;
2663 def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC;
2664 def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC;
2665 def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC;
2667 def AND_V : AND_V_ENC, AND_V_DESC;
2668 def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC,
2669 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2672 def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC,
2673 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2676 def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC,
2677 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2681 def ANDI_B : ANDI_B_ENC, ANDI_B_DESC;
2683 def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC;
2684 def ASUB_S_H : ASUB_S_H_ENC, ASUB_S_H_DESC;
2685 def ASUB_S_W : ASUB_S_W_ENC, ASUB_S_W_DESC;
2686 def ASUB_S_D : ASUB_S_D_ENC, ASUB_S_D_DESC;
2688 def ASUB_U_B : ASUB_U_B_ENC, ASUB_U_B_DESC;
2689 def ASUB_U_H : ASUB_U_H_ENC, ASUB_U_H_DESC;
2690 def ASUB_U_W : ASUB_U_W_ENC, ASUB_U_W_DESC;
2691 def ASUB_U_D : ASUB_U_D_ENC, ASUB_U_D_DESC;
2693 def AVE_S_B : AVE_S_B_ENC, AVE_S_B_DESC;
2694 def AVE_S_H : AVE_S_H_ENC, AVE_S_H_DESC;
2695 def AVE_S_W : AVE_S_W_ENC, AVE_S_W_DESC;
2696 def AVE_S_D : AVE_S_D_ENC, AVE_S_D_DESC;
2698 def AVE_U_B : AVE_U_B_ENC, AVE_U_B_DESC;
2699 def AVE_U_H : AVE_U_H_ENC, AVE_U_H_DESC;
2700 def AVE_U_W : AVE_U_W_ENC, AVE_U_W_DESC;
2701 def AVE_U_D : AVE_U_D_ENC, AVE_U_D_DESC;
2703 def AVER_S_B : AVER_S_B_ENC, AVER_S_B_DESC;
2704 def AVER_S_H : AVER_S_H_ENC, AVER_S_H_DESC;
2705 def AVER_S_W : AVER_S_W_ENC, AVER_S_W_DESC;
2706 def AVER_S_D : AVER_S_D_ENC, AVER_S_D_DESC;
2708 def AVER_U_B : AVER_U_B_ENC, AVER_U_B_DESC;
2709 def AVER_U_H : AVER_U_H_ENC, AVER_U_H_DESC;
2710 def AVER_U_W : AVER_U_W_ENC, AVER_U_W_DESC;
2711 def AVER_U_D : AVER_U_D_ENC, AVER_U_D_DESC;
2713 def BCLR_B : BCLR_B_ENC, BCLR_B_DESC;
2714 def BCLR_H : BCLR_H_ENC, BCLR_H_DESC;
2715 def BCLR_W : BCLR_W_ENC, BCLR_W_DESC;
2716 def BCLR_D : BCLR_D_ENC, BCLR_D_DESC;
2718 def BCLRI_B : BCLRI_B_ENC, BCLRI_B_DESC;
2719 def BCLRI_H : BCLRI_H_ENC, BCLRI_H_DESC;
2720 def BCLRI_W : BCLRI_W_ENC, BCLRI_W_DESC;
2721 def BCLRI_D : BCLRI_D_ENC, BCLRI_D_DESC;
2723 def BINSL_B : BINSL_B_ENC, BINSL_B_DESC;
2724 def BINSL_H : BINSL_H_ENC, BINSL_H_DESC;
2725 def BINSL_W : BINSL_W_ENC, BINSL_W_DESC;
2726 def BINSL_D : BINSL_D_ENC, BINSL_D_DESC;
2728 def BINSLI_B : BINSLI_B_ENC, BINSLI_B_DESC;
2729 def BINSLI_H : BINSLI_H_ENC, BINSLI_H_DESC;
2730 def BINSLI_W : BINSLI_W_ENC, BINSLI_W_DESC;
2731 def BINSLI_D : BINSLI_D_ENC, BINSLI_D_DESC;
2733 def BINSR_B : BINSR_B_ENC, BINSR_B_DESC;
2734 def BINSR_H : BINSR_H_ENC, BINSR_H_DESC;
2735 def BINSR_W : BINSR_W_ENC, BINSR_W_DESC;
2736 def BINSR_D : BINSR_D_ENC, BINSR_D_DESC;
2738 def BINSRI_B : BINSRI_B_ENC, BINSRI_B_DESC;
2739 def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC;
2740 def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC;
2741 def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC;
2743 def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC;
2745 def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC;
2747 def BMZ_V : BMZ_V_ENC, BMZ_V_DESC;
2749 def BMZI_B : BMZI_B_ENC, BMZI_B_DESC;
2751 def BNEG_B : BNEG_B_ENC, BNEG_B_DESC;
2752 def BNEG_H : BNEG_H_ENC, BNEG_H_DESC;
2753 def BNEG_W : BNEG_W_ENC, BNEG_W_DESC;
2754 def BNEG_D : BNEG_D_ENC, BNEG_D_DESC;
2756 def BNEGI_B : BNEGI_B_ENC, BNEGI_B_DESC;
2757 def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC;
2758 def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC;
2759 def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC;
2761 def BNZ_B : BNZ_B_ENC, BNZ_B_DESC;
2762 def BNZ_H : BNZ_H_ENC, BNZ_H_DESC;
2763 def BNZ_W : BNZ_W_ENC, BNZ_W_DESC;
2764 def BNZ_D : BNZ_D_ENC, BNZ_D_DESC;
2766 def BNZ_V : BNZ_V_ENC, BNZ_V_DESC;
2768 def BSEL_V : BSEL_V_ENC, BSEL_V_DESC;
2770 class MSA_BSEL_PSEUDO_BASE<RegisterOperand RO, ValueType Ty> :
2771 MipsPseudo<(outs RO:$wd), (ins RO:$wd_in, RO:$ws, RO:$wt),
2772 [(set RO:$wd, (Ty (vselect RO:$wd_in, RO:$ws, RO:$wt)))]>,
2773 PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in,
2774 MSA128BOpnd:$ws, MSA128BOpnd:$wt)> {
2775 let Constraints = "$wd_in = $wd";
2778 def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128HOpnd, v8i16>;
2779 def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4i32>;
2780 def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2i64>;
2781 def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4f32>;
2782 def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2f64>;
2784 def BSELI_B : BSELI_B_ENC, BSELI_B_DESC;
2786 def BSET_B : BSET_B_ENC, BSET_B_DESC;
2787 def BSET_H : BSET_H_ENC, BSET_H_DESC;
2788 def BSET_W : BSET_W_ENC, BSET_W_DESC;
2789 def BSET_D : BSET_D_ENC, BSET_D_DESC;
2791 def BSETI_B : BSETI_B_ENC, BSETI_B_DESC;
2792 def BSETI_H : BSETI_H_ENC, BSETI_H_DESC;
2793 def BSETI_W : BSETI_W_ENC, BSETI_W_DESC;
2794 def BSETI_D : BSETI_D_ENC, BSETI_D_DESC;
2796 def BZ_B : BZ_B_ENC, BZ_B_DESC;
2797 def BZ_H : BZ_H_ENC, BZ_H_DESC;
2798 def BZ_W : BZ_W_ENC, BZ_W_DESC;
2799 def BZ_D : BZ_D_ENC, BZ_D_DESC;
2801 def BZ_V : BZ_V_ENC, BZ_V_DESC;
2803 def CEQ_B : CEQ_B_ENC, CEQ_B_DESC;
2804 def CEQ_H : CEQ_H_ENC, CEQ_H_DESC;
2805 def CEQ_W : CEQ_W_ENC, CEQ_W_DESC;
2806 def CEQ_D : CEQ_D_ENC, CEQ_D_DESC;
2808 def CEQI_B : CEQI_B_ENC, CEQI_B_DESC;
2809 def CEQI_H : CEQI_H_ENC, CEQI_H_DESC;
2810 def CEQI_W : CEQI_W_ENC, CEQI_W_DESC;
2811 def CEQI_D : CEQI_D_ENC, CEQI_D_DESC;
2813 def CFCMSA : CFCMSA_ENC, CFCMSA_DESC;
2815 def CLE_S_B : CLE_S_B_ENC, CLE_S_B_DESC;
2816 def CLE_S_H : CLE_S_H_ENC, CLE_S_H_DESC;
2817 def CLE_S_W : CLE_S_W_ENC, CLE_S_W_DESC;
2818 def CLE_S_D : CLE_S_D_ENC, CLE_S_D_DESC;
2820 def CLE_U_B : CLE_U_B_ENC, CLE_U_B_DESC;
2821 def CLE_U_H : CLE_U_H_ENC, CLE_U_H_DESC;
2822 def CLE_U_W : CLE_U_W_ENC, CLE_U_W_DESC;
2823 def CLE_U_D : CLE_U_D_ENC, CLE_U_D_DESC;
2825 def CLEI_S_B : CLEI_S_B_ENC, CLEI_S_B_DESC;
2826 def CLEI_S_H : CLEI_S_H_ENC, CLEI_S_H_DESC;
2827 def CLEI_S_W : CLEI_S_W_ENC, CLEI_S_W_DESC;
2828 def CLEI_S_D : CLEI_S_D_ENC, CLEI_S_D_DESC;
2830 def CLEI_U_B : CLEI_U_B_ENC, CLEI_U_B_DESC;
2831 def CLEI_U_H : CLEI_U_H_ENC, CLEI_U_H_DESC;
2832 def CLEI_U_W : CLEI_U_W_ENC, CLEI_U_W_DESC;
2833 def CLEI_U_D : CLEI_U_D_ENC, CLEI_U_D_DESC;
2835 def CLT_S_B : CLT_S_B_ENC, CLT_S_B_DESC;
2836 def CLT_S_H : CLT_S_H_ENC, CLT_S_H_DESC;
2837 def CLT_S_W : CLT_S_W_ENC, CLT_S_W_DESC;
2838 def CLT_S_D : CLT_S_D_ENC, CLT_S_D_DESC;
2840 def CLT_U_B : CLT_U_B_ENC, CLT_U_B_DESC;
2841 def CLT_U_H : CLT_U_H_ENC, CLT_U_H_DESC;
2842 def CLT_U_W : CLT_U_W_ENC, CLT_U_W_DESC;
2843 def CLT_U_D : CLT_U_D_ENC, CLT_U_D_DESC;
2845 def CLTI_S_B : CLTI_S_B_ENC, CLTI_S_B_DESC;
2846 def CLTI_S_H : CLTI_S_H_ENC, CLTI_S_H_DESC;
2847 def CLTI_S_W : CLTI_S_W_ENC, CLTI_S_W_DESC;
2848 def CLTI_S_D : CLTI_S_D_ENC, CLTI_S_D_DESC;
2850 def CLTI_U_B : CLTI_U_B_ENC, CLTI_U_B_DESC;
2851 def CLTI_U_H : CLTI_U_H_ENC, CLTI_U_H_DESC;
2852 def CLTI_U_W : CLTI_U_W_ENC, CLTI_U_W_DESC;
2853 def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC;
2855 def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC;
2856 def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC;
2857 def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC;
2859 def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC;
2860 def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC;
2861 def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC;
2863 def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC;
2864 def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC;
2866 def CTCMSA : CTCMSA_ENC, CTCMSA_DESC;
2868 def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC;
2869 def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC;
2870 def DIV_S_W : DIV_S_W_ENC, DIV_S_W_DESC;
2871 def DIV_S_D : DIV_S_D_ENC, DIV_S_D_DESC;
2873 def DIV_U_B : DIV_U_B_ENC, DIV_U_B_DESC;
2874 def DIV_U_H : DIV_U_H_ENC, DIV_U_H_DESC;
2875 def DIV_U_W : DIV_U_W_ENC, DIV_U_W_DESC;
2876 def DIV_U_D : DIV_U_D_ENC, DIV_U_D_DESC;
2878 def DOTP_S_H : DOTP_S_H_ENC, DOTP_S_H_DESC;
2879 def DOTP_S_W : DOTP_S_W_ENC, DOTP_S_W_DESC;
2880 def DOTP_S_D : DOTP_S_D_ENC, DOTP_S_D_DESC;
2882 def DOTP_U_H : DOTP_U_H_ENC, DOTP_U_H_DESC;
2883 def DOTP_U_W : DOTP_U_W_ENC, DOTP_U_W_DESC;
2884 def DOTP_U_D : DOTP_U_D_ENC, DOTP_U_D_DESC;
2886 def DPADD_S_H : DPADD_S_H_ENC, DPADD_S_H_DESC;
2887 def DPADD_S_W : DPADD_S_W_ENC, DPADD_S_W_DESC;
2888 def DPADD_S_D : DPADD_S_D_ENC, DPADD_S_D_DESC;
2890 def DPADD_U_H : DPADD_U_H_ENC, DPADD_U_H_DESC;
2891 def DPADD_U_W : DPADD_U_W_ENC, DPADD_U_W_DESC;
2892 def DPADD_U_D : DPADD_U_D_ENC, DPADD_U_D_DESC;
2894 def DPSUB_S_H : DPSUB_S_H_ENC, DPSUB_S_H_DESC;
2895 def DPSUB_S_W : DPSUB_S_W_ENC, DPSUB_S_W_DESC;
2896 def DPSUB_S_D : DPSUB_S_D_ENC, DPSUB_S_D_DESC;
2898 def DPSUB_U_H : DPSUB_U_H_ENC, DPSUB_U_H_DESC;
2899 def DPSUB_U_W : DPSUB_U_W_ENC, DPSUB_U_W_DESC;
2900 def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC;
2902 def FADD_W : FADD_W_ENC, FADD_W_DESC;
2903 def FADD_D : FADD_D_ENC, FADD_D_DESC;
2905 def FCAF_W : FCAF_W_ENC, FCAF_W_DESC;
2906 def FCAF_D : FCAF_D_ENC, FCAF_D_DESC;
2908 def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC;
2909 def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC;
2911 def FCLE_W : FCLE_W_ENC, FCLE_W_DESC;
2912 def FCLE_D : FCLE_D_ENC, FCLE_D_DESC;
2914 def FCLT_W : FCLT_W_ENC, FCLT_W_DESC;
2915 def FCLT_D : FCLT_D_ENC, FCLT_D_DESC;
2917 def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC;
2918 def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC;
2920 def FCNE_W : FCNE_W_ENC, FCNE_W_DESC;
2921 def FCNE_D : FCNE_D_ENC, FCNE_D_DESC;
2923 def FCOR_W : FCOR_W_ENC, FCOR_W_DESC;
2924 def FCOR_D : FCOR_D_ENC, FCOR_D_DESC;
2926 def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC;
2927 def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC;
2929 def FCULE_W : FCULE_W_ENC, FCULE_W_DESC;
2930 def FCULE_D : FCULE_D_ENC, FCULE_D_DESC;
2932 def FCULT_W : FCULT_W_ENC, FCULT_W_DESC;
2933 def FCULT_D : FCULT_D_ENC, FCULT_D_DESC;
2935 def FCUN_W : FCUN_W_ENC, FCUN_W_DESC;
2936 def FCUN_D : FCUN_D_ENC, FCUN_D_DESC;
2938 def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC;
2939 def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC;
2941 def FDIV_W : FDIV_W_ENC, FDIV_W_DESC;
2942 def FDIV_D : FDIV_D_ENC, FDIV_D_DESC;
2944 def FEXDO_H : FEXDO_H_ENC, FEXDO_H_DESC;
2945 def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC;
2947 def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC;
2948 def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC;
2949 def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC;
2950 def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC;
2952 def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC;
2953 def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC;
2955 def FEXUPR_W : FEXUPR_W_ENC, FEXUPR_W_DESC;
2956 def FEXUPR_D : FEXUPR_D_ENC, FEXUPR_D_DESC;
2958 def FFINT_S_W : FFINT_S_W_ENC, FFINT_S_W_DESC;
2959 def FFINT_S_D : FFINT_S_D_ENC, FFINT_S_D_DESC;
2961 def FFINT_U_W : FFINT_U_W_ENC, FFINT_U_W_DESC;
2962 def FFINT_U_D : FFINT_U_D_ENC, FFINT_U_D_DESC;
2964 def FFQL_W : FFQL_W_ENC, FFQL_W_DESC;
2965 def FFQL_D : FFQL_D_ENC, FFQL_D_DESC;
2967 def FFQR_W : FFQR_W_ENC, FFQR_W_DESC;
2968 def FFQR_D : FFQR_D_ENC, FFQR_D_DESC;
2970 def FILL_B : FILL_B_ENC, FILL_B_DESC;
2971 def FILL_H : FILL_H_ENC, FILL_H_DESC;
2972 def FILL_W : FILL_W_ENC, FILL_W_DESC;
2973 def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC;
2974 def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC;
2976 def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC;
2977 def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC;
2979 def FMADD_W : FMADD_W_ENC, FMADD_W_DESC;
2980 def FMADD_D : FMADD_D_ENC, FMADD_D_DESC;
2982 def FMAX_W : FMAX_W_ENC, FMAX_W_DESC;
2983 def FMAX_D : FMAX_D_ENC, FMAX_D_DESC;
2985 def FMAX_A_W : FMAX_A_W_ENC, FMAX_A_W_DESC;
2986 def FMAX_A_D : FMAX_A_D_ENC, FMAX_A_D_DESC;
2988 def FMIN_W : FMIN_W_ENC, FMIN_W_DESC;
2989 def FMIN_D : FMIN_D_ENC, FMIN_D_DESC;
2991 def FMIN_A_W : FMIN_A_W_ENC, FMIN_A_W_DESC;
2992 def FMIN_A_D : FMIN_A_D_ENC, FMIN_A_D_DESC;
2994 def FMSUB_W : FMSUB_W_ENC, FMSUB_W_DESC;
2995 def FMSUB_D : FMSUB_D_ENC, FMSUB_D_DESC;
2997 def FMUL_W : FMUL_W_ENC, FMUL_W_DESC;
2998 def FMUL_D : FMUL_D_ENC, FMUL_D_DESC;
3000 def FRINT_W : FRINT_W_ENC, FRINT_W_DESC;
3001 def FRINT_D : FRINT_D_ENC, FRINT_D_DESC;
3003 def FRCP_W : FRCP_W_ENC, FRCP_W_DESC;
3004 def FRCP_D : FRCP_D_ENC, FRCP_D_DESC;
3006 def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC;
3007 def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC;
3009 def FSAF_W : FSAF_W_ENC, FSAF_W_DESC;
3010 def FSAF_D : FSAF_D_ENC, FSAF_D_DESC;
3012 def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC;
3013 def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC;
3015 def FSLE_W : FSLE_W_ENC, FSLE_W_DESC;
3016 def FSLE_D : FSLE_D_ENC, FSLE_D_DESC;
3018 def FSLT_W : FSLT_W_ENC, FSLT_W_DESC;
3019 def FSLT_D : FSLT_D_ENC, FSLT_D_DESC;
3021 def FSNE_W : FSNE_W_ENC, FSNE_W_DESC;
3022 def FSNE_D : FSNE_D_ENC, FSNE_D_DESC;
3024 def FSOR_W : FSOR_W_ENC, FSOR_W_DESC;
3025 def FSOR_D : FSOR_D_ENC, FSOR_D_DESC;
3027 def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC;
3028 def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC;
3030 def FSUB_W : FSUB_W_ENC, FSUB_W_DESC;
3031 def FSUB_D : FSUB_D_ENC, FSUB_D_DESC;
3033 def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC;
3034 def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC;
3036 def FSULE_W : FSULE_W_ENC, FSULE_W_DESC;
3037 def FSULE_D : FSULE_D_ENC, FSULE_D_DESC;
3039 def FSULT_W : FSULT_W_ENC, FSULT_W_DESC;
3040 def FSULT_D : FSULT_D_ENC, FSULT_D_DESC;
3042 def FSUN_W : FSUN_W_ENC, FSUN_W_DESC;
3043 def FSUN_D : FSUN_D_ENC, FSUN_D_DESC;
3045 def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC;
3046 def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC;
3048 def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC;
3049 def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC;
3051 def FTINT_U_W : FTINT_U_W_ENC, FTINT_U_W_DESC;
3052 def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC;
3054 def FTQ_H : FTQ_H_ENC, FTQ_H_DESC;
3055 def FTQ_W : FTQ_W_ENC, FTQ_W_DESC;
3057 def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC;
3058 def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC;
3060 def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC;
3061 def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC;
3063 def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC;
3064 def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC;
3065 def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC;
3067 def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC;
3068 def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC;
3069 def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC;
3071 def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC;
3072 def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC;
3073 def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC;
3075 def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC;
3076 def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC;
3077 def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC;
3079 def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC;
3080 def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC;
3081 def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC;
3082 def ILVEV_D : ILVEV_D_ENC, ILVEV_D_DESC;
3084 def ILVL_B : ILVL_B_ENC, ILVL_B_DESC;
3085 def ILVL_H : ILVL_H_ENC, ILVL_H_DESC;
3086 def ILVL_W : ILVL_W_ENC, ILVL_W_DESC;
3087 def ILVL_D : ILVL_D_ENC, ILVL_D_DESC;
3089 def ILVOD_B : ILVOD_B_ENC, ILVOD_B_DESC;
3090 def ILVOD_H : ILVOD_H_ENC, ILVOD_H_DESC;
3091 def ILVOD_W : ILVOD_W_ENC, ILVOD_W_DESC;
3092 def ILVOD_D : ILVOD_D_ENC, ILVOD_D_DESC;
3094 def ILVR_B : ILVR_B_ENC, ILVR_B_DESC;
3095 def ILVR_H : ILVR_H_ENC, ILVR_H_DESC;
3096 def ILVR_W : ILVR_W_ENC, ILVR_W_DESC;
3097 def ILVR_D : ILVR_D_ENC, ILVR_D_DESC;
3099 def INSERT_B : INSERT_B_ENC, INSERT_B_DESC;
3100 def INSERT_H : INSERT_H_ENC, INSERT_H_DESC;
3101 def INSERT_W : INSERT_W_ENC, INSERT_W_DESC;
3103 // INSERT_FW_PSEUDO defined after INSVE_W
3104 // INSERT_FD_PSEUDO defined after INSVE_D
3106 def INSVE_B : INSVE_B_ENC, INSVE_B_DESC;
3107 def INSVE_H : INSVE_H_ENC, INSVE_H_DESC;
3108 def INSVE_W : INSVE_W_ENC, INSVE_W_DESC;
3109 def INSVE_D : INSVE_D_ENC, INSVE_D_DESC;
3111 def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC;
3112 def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC;
3114 def LD_B: LD_B_ENC, LD_B_DESC;
3115 def LD_H: LD_H_ENC, LD_H_DESC;
3116 def LD_W: LD_W_ENC, LD_W_DESC;
3117 def LD_D: LD_D_ENC, LD_D_DESC;
3119 def LDI_B : LDI_B_ENC, LDI_B_DESC;
3120 def LDI_H : LDI_H_ENC, LDI_H_DESC;
3121 def LDI_W : LDI_W_ENC, LDI_W_DESC;
3122 def LDI_D : LDI_D_ENC, LDI_D_DESC;
3124 def LSA : LSA_ENC, LSA_DESC;
3126 def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC;
3127 def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC;
3129 def MADDR_Q_H : MADDR_Q_H_ENC, MADDR_Q_H_DESC;
3130 def MADDR_Q_W : MADDR_Q_W_ENC, MADDR_Q_W_DESC;
3132 def MADDV_B : MADDV_B_ENC, MADDV_B_DESC;
3133 def MADDV_H : MADDV_H_ENC, MADDV_H_DESC;
3134 def MADDV_W : MADDV_W_ENC, MADDV_W_DESC;
3135 def MADDV_D : MADDV_D_ENC, MADDV_D_DESC;
3137 def MAX_A_B : MAX_A_B_ENC, MAX_A_B_DESC;
3138 def MAX_A_H : MAX_A_H_ENC, MAX_A_H_DESC;
3139 def MAX_A_W : MAX_A_W_ENC, MAX_A_W_DESC;
3140 def MAX_A_D : MAX_A_D_ENC, MAX_A_D_DESC;
3142 def MAX_S_B : MAX_S_B_ENC, MAX_S_B_DESC;
3143 def MAX_S_H : MAX_S_H_ENC, MAX_S_H_DESC;
3144 def MAX_S_W : MAX_S_W_ENC, MAX_S_W_DESC;
3145 def MAX_S_D : MAX_S_D_ENC, MAX_S_D_DESC;
3147 def MAX_U_B : MAX_U_B_ENC, MAX_U_B_DESC;
3148 def MAX_U_H : MAX_U_H_ENC, MAX_U_H_DESC;
3149 def MAX_U_W : MAX_U_W_ENC, MAX_U_W_DESC;
3150 def MAX_U_D : MAX_U_D_ENC, MAX_U_D_DESC;
3152 def MAXI_S_B : MAXI_S_B_ENC, MAXI_S_B_DESC;
3153 def MAXI_S_H : MAXI_S_H_ENC, MAXI_S_H_DESC;
3154 def MAXI_S_W : MAXI_S_W_ENC, MAXI_S_W_DESC;
3155 def MAXI_S_D : MAXI_S_D_ENC, MAXI_S_D_DESC;
3157 def MAXI_U_B : MAXI_U_B_ENC, MAXI_U_B_DESC;
3158 def MAXI_U_H : MAXI_U_H_ENC, MAXI_U_H_DESC;
3159 def MAXI_U_W : MAXI_U_W_ENC, MAXI_U_W_DESC;
3160 def MAXI_U_D : MAXI_U_D_ENC, MAXI_U_D_DESC;
3162 def MIN_A_B : MIN_A_B_ENC, MIN_A_B_DESC;
3163 def MIN_A_H : MIN_A_H_ENC, MIN_A_H_DESC;
3164 def MIN_A_W : MIN_A_W_ENC, MIN_A_W_DESC;
3165 def MIN_A_D : MIN_A_D_ENC, MIN_A_D_DESC;
3167 def MIN_S_B : MIN_S_B_ENC, MIN_S_B_DESC;
3168 def MIN_S_H : MIN_S_H_ENC, MIN_S_H_DESC;
3169 def MIN_S_W : MIN_S_W_ENC, MIN_S_W_DESC;
3170 def MIN_S_D : MIN_S_D_ENC, MIN_S_D_DESC;
3172 def MIN_U_B : MIN_U_B_ENC, MIN_U_B_DESC;
3173 def MIN_U_H : MIN_U_H_ENC, MIN_U_H_DESC;
3174 def MIN_U_W : MIN_U_W_ENC, MIN_U_W_DESC;
3175 def MIN_U_D : MIN_U_D_ENC, MIN_U_D_DESC;
3177 def MINI_S_B : MINI_S_B_ENC, MINI_S_B_DESC;
3178 def MINI_S_H : MINI_S_H_ENC, MINI_S_H_DESC;
3179 def MINI_S_W : MINI_S_W_ENC, MINI_S_W_DESC;
3180 def MINI_S_D : MINI_S_D_ENC, MINI_S_D_DESC;
3182 def MINI_U_B : MINI_U_B_ENC, MINI_U_B_DESC;
3183 def MINI_U_H : MINI_U_H_ENC, MINI_U_H_DESC;
3184 def MINI_U_W : MINI_U_W_ENC, MINI_U_W_DESC;
3185 def MINI_U_D : MINI_U_D_ENC, MINI_U_D_DESC;
3187 def MOD_S_B : MOD_S_B_ENC, MOD_S_B_DESC;
3188 def MOD_S_H : MOD_S_H_ENC, MOD_S_H_DESC;
3189 def MOD_S_W : MOD_S_W_ENC, MOD_S_W_DESC;
3190 def MOD_S_D : MOD_S_D_ENC, MOD_S_D_DESC;
3192 def MOD_U_B : MOD_U_B_ENC, MOD_U_B_DESC;
3193 def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC;
3194 def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC;
3195 def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC;
3197 def MOVE_V : MOVE_V_ENC, MOVE_V_DESC;
3199 def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC;
3200 def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC;
3202 def MSUBR_Q_H : MSUBR_Q_H_ENC, MSUBR_Q_H_DESC;
3203 def MSUBR_Q_W : MSUBR_Q_W_ENC, MSUBR_Q_W_DESC;
3205 def MSUBV_B : MSUBV_B_ENC, MSUBV_B_DESC;
3206 def MSUBV_H : MSUBV_H_ENC, MSUBV_H_DESC;
3207 def MSUBV_W : MSUBV_W_ENC, MSUBV_W_DESC;
3208 def MSUBV_D : MSUBV_D_ENC, MSUBV_D_DESC;
3210 def MUL_Q_H : MUL_Q_H_ENC, MUL_Q_H_DESC;
3211 def MUL_Q_W : MUL_Q_W_ENC, MUL_Q_W_DESC;
3213 def MULR_Q_H : MULR_Q_H_ENC, MULR_Q_H_DESC;
3214 def MULR_Q_W : MULR_Q_W_ENC, MULR_Q_W_DESC;
3216 def MULV_B : MULV_B_ENC, MULV_B_DESC;
3217 def MULV_H : MULV_H_ENC, MULV_H_DESC;
3218 def MULV_W : MULV_W_ENC, MULV_W_DESC;
3219 def MULV_D : MULV_D_ENC, MULV_D_DESC;
3221 def NLOC_B : NLOC_B_ENC, NLOC_B_DESC;
3222 def NLOC_H : NLOC_H_ENC, NLOC_H_DESC;
3223 def NLOC_W : NLOC_W_ENC, NLOC_W_DESC;
3224 def NLOC_D : NLOC_D_ENC, NLOC_D_DESC;
3226 def NLZC_B : NLZC_B_ENC, NLZC_B_DESC;
3227 def NLZC_H : NLZC_H_ENC, NLZC_H_DESC;
3228 def NLZC_W : NLZC_W_ENC, NLZC_W_DESC;
3229 def NLZC_D : NLZC_D_ENC, NLZC_D_DESC;
3231 def NOR_V : NOR_V_ENC, NOR_V_DESC;
3232 def NOR_V_H_PSEUDO : NOR_V_H_PSEUDO_DESC,
3233 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3236 def NOR_V_W_PSEUDO : NOR_V_W_PSEUDO_DESC,
3237 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3240 def NOR_V_D_PSEUDO : NOR_V_D_PSEUDO_DESC,
3241 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3245 def NORI_B : NORI_B_ENC, NORI_B_DESC;
3247 def OR_V : OR_V_ENC, OR_V_DESC;
3248 def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC,
3249 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3252 def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC,
3253 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3256 def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC,
3257 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3261 def ORI_B : ORI_B_ENC, ORI_B_DESC;
3263 def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC;
3264 def PCKEV_H : PCKEV_H_ENC, PCKEV_H_DESC;
3265 def PCKEV_W : PCKEV_W_ENC, PCKEV_W_DESC;
3266 def PCKEV_D : PCKEV_D_ENC, PCKEV_D_DESC;
3268 def PCKOD_B : PCKOD_B_ENC, PCKOD_B_DESC;
3269 def PCKOD_H : PCKOD_H_ENC, PCKOD_H_DESC;
3270 def PCKOD_W : PCKOD_W_ENC, PCKOD_W_DESC;
3271 def PCKOD_D : PCKOD_D_ENC, PCKOD_D_DESC;
3273 def PCNT_B : PCNT_B_ENC, PCNT_B_DESC;
3274 def PCNT_H : PCNT_H_ENC, PCNT_H_DESC;
3275 def PCNT_W : PCNT_W_ENC, PCNT_W_DESC;
3276 def PCNT_D : PCNT_D_ENC, PCNT_D_DESC;
3278 def SAT_S_B : SAT_S_B_ENC, SAT_S_B_DESC;
3279 def SAT_S_H : SAT_S_H_ENC, SAT_S_H_DESC;
3280 def SAT_S_W : SAT_S_W_ENC, SAT_S_W_DESC;
3281 def SAT_S_D : SAT_S_D_ENC, SAT_S_D_DESC;
3283 def SAT_U_B : SAT_U_B_ENC, SAT_U_B_DESC;
3284 def SAT_U_H : SAT_U_H_ENC, SAT_U_H_DESC;
3285 def SAT_U_W : SAT_U_W_ENC, SAT_U_W_DESC;
3286 def SAT_U_D : SAT_U_D_ENC, SAT_U_D_DESC;
3288 def SHF_B : SHF_B_ENC, SHF_B_DESC;
3289 def SHF_H : SHF_H_ENC, SHF_H_DESC;
3290 def SHF_W : SHF_W_ENC, SHF_W_DESC;
3292 def SLD_B : SLD_B_ENC, SLD_B_DESC;
3293 def SLD_H : SLD_H_ENC, SLD_H_DESC;
3294 def SLD_W : SLD_W_ENC, SLD_W_DESC;
3295 def SLD_D : SLD_D_ENC, SLD_D_DESC;
3297 def SLDI_B : SLDI_B_ENC, SLDI_B_DESC;
3298 def SLDI_H : SLDI_H_ENC, SLDI_H_DESC;
3299 def SLDI_W : SLDI_W_ENC, SLDI_W_DESC;
3300 def SLDI_D : SLDI_D_ENC, SLDI_D_DESC;
3302 def SLL_B : SLL_B_ENC, SLL_B_DESC;
3303 def SLL_H : SLL_H_ENC, SLL_H_DESC;
3304 def SLL_W : SLL_W_ENC, SLL_W_DESC;
3305 def SLL_D : SLL_D_ENC, SLL_D_DESC;
3307 def SLLI_B : SLLI_B_ENC, SLLI_B_DESC;
3308 def SLLI_H : SLLI_H_ENC, SLLI_H_DESC;
3309 def SLLI_W : SLLI_W_ENC, SLLI_W_DESC;
3310 def SLLI_D : SLLI_D_ENC, SLLI_D_DESC;
3312 def SPLAT_B : SPLAT_B_ENC, SPLAT_B_DESC;
3313 def SPLAT_H : SPLAT_H_ENC, SPLAT_H_DESC;
3314 def SPLAT_W : SPLAT_W_ENC, SPLAT_W_DESC;
3315 def SPLAT_D : SPLAT_D_ENC, SPLAT_D_DESC;
3317 def SPLATI_B : SPLATI_B_ENC, SPLATI_B_DESC;
3318 def SPLATI_H : SPLATI_H_ENC, SPLATI_H_DESC;
3319 def SPLATI_W : SPLATI_W_ENC, SPLATI_W_DESC;
3320 def SPLATI_D : SPLATI_D_ENC, SPLATI_D_DESC;
3322 def SRA_B : SRA_B_ENC, SRA_B_DESC;
3323 def SRA_H : SRA_H_ENC, SRA_H_DESC;
3324 def SRA_W : SRA_W_ENC, SRA_W_DESC;
3325 def SRA_D : SRA_D_ENC, SRA_D_DESC;
3327 def SRAI_B : SRAI_B_ENC, SRAI_B_DESC;
3328 def SRAI_H : SRAI_H_ENC, SRAI_H_DESC;
3329 def SRAI_W : SRAI_W_ENC, SRAI_W_DESC;
3330 def SRAI_D : SRAI_D_ENC, SRAI_D_DESC;
3332 def SRAR_B : SRAR_B_ENC, SRAR_B_DESC;
3333 def SRAR_H : SRAR_H_ENC, SRAR_H_DESC;
3334 def SRAR_W : SRAR_W_ENC, SRAR_W_DESC;
3335 def SRAR_D : SRAR_D_ENC, SRAR_D_DESC;
3337 def SRARI_B : SRARI_B_ENC, SRARI_B_DESC;
3338 def SRARI_H : SRARI_H_ENC, SRARI_H_DESC;
3339 def SRARI_W : SRARI_W_ENC, SRARI_W_DESC;
3340 def SRARI_D : SRARI_D_ENC, SRARI_D_DESC;
3342 def SRL_B : SRL_B_ENC, SRL_B_DESC;
3343 def SRL_H : SRL_H_ENC, SRL_H_DESC;
3344 def SRL_W : SRL_W_ENC, SRL_W_DESC;
3345 def SRL_D : SRL_D_ENC, SRL_D_DESC;
3347 def SRLI_B : SRLI_B_ENC, SRLI_B_DESC;
3348 def SRLI_H : SRLI_H_ENC, SRLI_H_DESC;
3349 def SRLI_W : SRLI_W_ENC, SRLI_W_DESC;
3350 def SRLI_D : SRLI_D_ENC, SRLI_D_DESC;
3352 def SRLR_B : SRLR_B_ENC, SRLR_B_DESC;
3353 def SRLR_H : SRLR_H_ENC, SRLR_H_DESC;
3354 def SRLR_W : SRLR_W_ENC, SRLR_W_DESC;
3355 def SRLR_D : SRLR_D_ENC, SRLR_D_DESC;
3357 def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC;
3358 def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC;
3359 def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC;
3360 def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC;
3362 def ST_B: ST_B_ENC, ST_B_DESC;
3363 def ST_H: ST_H_ENC, ST_H_DESC;
3364 def ST_W: ST_W_ENC, ST_W_DESC;
3365 def ST_D: ST_D_ENC, ST_D_DESC;
3367 def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC;
3368 def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC;
3369 def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC;
3370 def SUBS_S_D : SUBS_S_D_ENC, SUBS_S_D_DESC;
3372 def SUBS_U_B : SUBS_U_B_ENC, SUBS_U_B_DESC;
3373 def SUBS_U_H : SUBS_U_H_ENC, SUBS_U_H_DESC;
3374 def SUBS_U_W : SUBS_U_W_ENC, SUBS_U_W_DESC;
3375 def SUBS_U_D : SUBS_U_D_ENC, SUBS_U_D_DESC;
3377 def SUBSUS_U_B : SUBSUS_U_B_ENC, SUBSUS_U_B_DESC;
3378 def SUBSUS_U_H : SUBSUS_U_H_ENC, SUBSUS_U_H_DESC;
3379 def SUBSUS_U_W : SUBSUS_U_W_ENC, SUBSUS_U_W_DESC;
3380 def SUBSUS_U_D : SUBSUS_U_D_ENC, SUBSUS_U_D_DESC;
3382 def SUBSUU_S_B : SUBSUU_S_B_ENC, SUBSUU_S_B_DESC;
3383 def SUBSUU_S_H : SUBSUU_S_H_ENC, SUBSUU_S_H_DESC;
3384 def SUBSUU_S_W : SUBSUU_S_W_ENC, SUBSUU_S_W_DESC;
3385 def SUBSUU_S_D : SUBSUU_S_D_ENC, SUBSUU_S_D_DESC;
3387 def SUBV_B : SUBV_B_ENC, SUBV_B_DESC;
3388 def SUBV_H : SUBV_H_ENC, SUBV_H_DESC;
3389 def SUBV_W : SUBV_W_ENC, SUBV_W_DESC;
3390 def SUBV_D : SUBV_D_ENC, SUBV_D_DESC;
3392 def SUBVI_B : SUBVI_B_ENC, SUBVI_B_DESC;
3393 def SUBVI_H : SUBVI_H_ENC, SUBVI_H_DESC;
3394 def SUBVI_W : SUBVI_W_ENC, SUBVI_W_DESC;
3395 def SUBVI_D : SUBVI_D_ENC, SUBVI_D_DESC;
3397 def VSHF_B : VSHF_B_ENC, VSHF_B_DESC;
3398 def VSHF_H : VSHF_H_ENC, VSHF_H_DESC;
3399 def VSHF_W : VSHF_W_ENC, VSHF_W_DESC;
3400 def VSHF_D : VSHF_D_ENC, VSHF_D_DESC;
3402 def XOR_V : XOR_V_ENC, XOR_V_DESC;
3403 def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC,
3404 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3407 def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC,
3408 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3411 def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC,
3412 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3416 def XORI_B : XORI_B_ENC, XORI_B_DESC;
3419 class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> :
3420 Pat<pattern, result>, Requires<pred>;
3422 def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx),
3423 (COPY_S_W MSA128W:$ws, immZExt4:$idx)>;
3425 def : MSAPat<(v16i8 (load addr:$addr)), (LD_B addr:$addr)>;
3426 def : MSAPat<(v8i16 (load addr:$addr)), (LD_H addr:$addr)>;
3427 def : MSAPat<(v4i32 (load addr:$addr)), (LD_W addr:$addr)>;
3428 def : MSAPat<(v2i64 (load addr:$addr)), (LD_D addr:$addr)>;
3429 def : MSAPat<(v8f16 (load addr:$addr)), (LD_H addr:$addr)>;
3430 def : MSAPat<(v4f32 (load addr:$addr)), (LD_W addr:$addr)>;
3431 def : MSAPat<(v2f64 (load addr:$addr)), (LD_D addr:$addr)>;
3433 def : MSAPat<(v8f16 (load addrRegImm:$addr)), (LD_H addrRegImm:$addr)>;
3434 def : MSAPat<(v4f32 (load addrRegImm:$addr)), (LD_W addrRegImm:$addr)>;
3435 def : MSAPat<(v2f64 (load addrRegImm:$addr)), (LD_D addrRegImm:$addr)>;
3437 def : MSAPat<(store (v16i8 MSA128B:$ws), addr:$addr),
3438 (ST_B MSA128B:$ws, addr:$addr)>;
3439 def : MSAPat<(store (v8i16 MSA128H:$ws), addr:$addr),
3440 (ST_H MSA128H:$ws, addr:$addr)>;
3441 def : MSAPat<(store (v4i32 MSA128W:$ws), addr:$addr),
3442 (ST_W MSA128W:$ws, addr:$addr)>;
3443 def : MSAPat<(store (v2i64 MSA128D:$ws), addr:$addr),
3444 (ST_D MSA128D:$ws, addr:$addr)>;
3445 def : MSAPat<(store (v8f16 MSA128H:$ws), addr:$addr),
3446 (ST_H MSA128H:$ws, addr:$addr)>;
3447 def : MSAPat<(store (v4f32 MSA128W:$ws), addr:$addr),
3448 (ST_W MSA128W:$ws, addr:$addr)>;
3449 def : MSAPat<(store (v2f64 MSA128D:$ws), addr:$addr),
3450 (ST_D MSA128D:$ws, addr:$addr)>;
3452 def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrRegImm:$addr),
3453 (ST_H MSA128H:$ws, addrRegImm:$addr)>;
3454 def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrRegImm:$addr),
3455 (ST_W MSA128W:$ws, addrRegImm:$addr)>;
3456 def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrRegImm:$addr),
3457 (ST_D MSA128D:$ws, addrRegImm:$addr)>;
3459 class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD,
3460 RegisterOperand ROWS = ROWD,
3461 InstrItinClass itin = NoItinerary> :
3462 MipsPseudo<(outs ROWD:$wd),
3464 [(set ROWD:$wd, (fabs ROWS:$ws))]> {
3465 InstrItinClass Itinerary = itin;
3467 def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>,
3468 PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws,
3470 def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128DOpnd>,
3471 PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws,
3474 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3475 RegisterClass DstRC, list<Predicate> preds = [HasMSA]> :
3476 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3477 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3479 // These are endian-independant because the element size doesnt change
3480 def : MSABitconvertPat<v8i16, v8f16, MSA128H>;
3481 def : MSABitconvertPat<v4i32, v4f32, MSA128W>;
3482 def : MSABitconvertPat<v2i64, v2f64, MSA128D>;
3483 def : MSABitconvertPat<v8f16, v8i16, MSA128H>;
3484 def : MSABitconvertPat<v4f32, v4i32, MSA128W>;
3485 def : MSABitconvertPat<v2f64, v2i64, MSA128D>;
3487 // Little endian bitcasts are always no-ops
3488 def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>;
3489 def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>;
3490 def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>;
3491 def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>;
3492 def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>;
3493 def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>;
3495 def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>;
3496 def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>;
3497 def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>;
3498 def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>;
3499 def : MSABitconvertPat<v8i16, v2f64, MSA128H, [HasMSA, IsLE]>;
3501 def : MSABitconvertPat<v4i32, v16i8, MSA128W, [HasMSA, IsLE]>;
3502 def : MSABitconvertPat<v4i32, v8i16, MSA128W, [HasMSA, IsLE]>;
3503 def : MSABitconvertPat<v4i32, v2i64, MSA128W, [HasMSA, IsLE]>;
3504 def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>;
3505 def : MSABitconvertPat<v4i32, v2f64, MSA128W, [HasMSA, IsLE]>;
3507 def : MSABitconvertPat<v2i64, v16i8, MSA128D, [HasMSA, IsLE]>;
3508 def : MSABitconvertPat<v2i64, v8i16, MSA128D, [HasMSA, IsLE]>;
3509 def : MSABitconvertPat<v2i64, v4i32, MSA128D, [HasMSA, IsLE]>;
3510 def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>;
3511 def : MSABitconvertPat<v2i64, v4f32, MSA128D, [HasMSA, IsLE]>;
3513 def : MSABitconvertPat<v4f32, v16i8, MSA128W, [HasMSA, IsLE]>;
3514 def : MSABitconvertPat<v4f32, v8i16, MSA128W, [HasMSA, IsLE]>;
3515 def : MSABitconvertPat<v4f32, v2i64, MSA128W, [HasMSA, IsLE]>;
3516 def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>;
3517 def : MSABitconvertPat<v4f32, v2f64, MSA128W, [HasMSA, IsLE]>;
3519 def : MSABitconvertPat<v2f64, v16i8, MSA128D, [HasMSA, IsLE]>;
3520 def : MSABitconvertPat<v2f64, v8i16, MSA128D, [HasMSA, IsLE]>;
3521 def : MSABitconvertPat<v2f64, v4i32, MSA128D, [HasMSA, IsLE]>;
3522 def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>;
3523 def : MSABitconvertPat<v2f64, v4f32, MSA128D, [HasMSA, IsLE]>;
3525 // Big endian bitcasts expand to shuffle instructions.
3526 // This is because bitcast is defined to be a store/load sequence and the
3527 // vector store/load instructions are mixed-endian with respect to the vector
3528 // as a whole (little endian with respect to element order, but big endian
3531 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3532 RegisterClass DstRC, MSAInst Insn,
3533 RegisterClass ViaRC> :
3534 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3535 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27),
3539 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3540 RegisterClass DstRC, MSAInst Insn,
3541 RegisterClass ViaRC> :
3542 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3543 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177),
3547 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
3548 RegisterClass DstRC> :
3549 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3551 class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
3552 RegisterClass DstRC> :
3553 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3555 class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT,
3556 RegisterClass DstRC> :
3557 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3561 (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27),
3566 class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT,
3567 RegisterClass DstRC> :
3568 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3570 class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT,
3571 RegisterClass DstRC> :
3572 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3574 class MSABitconvertReverseWInDPat<ValueType DstVT, ValueType SrcVT,
3575 RegisterClass DstRC> :
3576 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_W, MSA128W>;
3578 def : MSABitconvertReverseBInHPat<v8i16, v16i8, MSA128H>;
3579 def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>;
3580 def : MSABitconvertReverseBInWPat<v4i32, v16i8, MSA128W>;
3581 def : MSABitconvertReverseBInWPat<v4f32, v16i8, MSA128W>;
3582 def : MSABitconvertReverseBInDPat<v2i64, v16i8, MSA128D>;
3583 def : MSABitconvertReverseBInDPat<v2f64, v16i8, MSA128D>;
3585 def : MSABitconvertReverseBInHPat<v16i8, v8i16, MSA128B>;
3586 def : MSABitconvertReverseHInWPat<v4i32, v8i16, MSA128W>;
3587 def : MSABitconvertReverseHInWPat<v4f32, v8i16, MSA128W>;
3588 def : MSABitconvertReverseHInDPat<v2i64, v8i16, MSA128D>;
3589 def : MSABitconvertReverseHInDPat<v2f64, v8i16, MSA128D>;
3591 def : MSABitconvertReverseBInHPat<v16i8, v8f16, MSA128B>;
3592 def : MSABitconvertReverseHInWPat<v4i32, v8f16, MSA128W>;
3593 def : MSABitconvertReverseHInWPat<v4f32, v8f16, MSA128W>;
3594 def : MSABitconvertReverseHInDPat<v2i64, v8f16, MSA128D>;
3595 def : MSABitconvertReverseHInDPat<v2f64, v8f16, MSA128D>;
3597 def : MSABitconvertReverseBInWPat<v16i8, v4i32, MSA128B>;
3598 def : MSABitconvertReverseHInWPat<v8i16, v4i32, MSA128H>;
3599 def : MSABitconvertReverseHInWPat<v8f16, v4i32, MSA128H>;
3600 def : MSABitconvertReverseWInDPat<v2i64, v4i32, MSA128D>;
3601 def : MSABitconvertReverseWInDPat<v2f64, v4i32, MSA128D>;
3603 def : MSABitconvertReverseBInWPat<v16i8, v4f32, MSA128B>;
3604 def : MSABitconvertReverseHInWPat<v8i16, v4f32, MSA128H>;
3605 def : MSABitconvertReverseHInWPat<v8f16, v4f32, MSA128H>;
3606 def : MSABitconvertReverseWInDPat<v2i64, v4f32, MSA128D>;
3607 def : MSABitconvertReverseWInDPat<v2f64, v4f32, MSA128D>;
3609 def : MSABitconvertReverseBInDPat<v16i8, v2i64, MSA128B>;
3610 def : MSABitconvertReverseHInDPat<v8i16, v2i64, MSA128H>;
3611 def : MSABitconvertReverseHInDPat<v8f16, v2i64, MSA128H>;
3612 def : MSABitconvertReverseWInDPat<v4i32, v2i64, MSA128W>;
3613 def : MSABitconvertReverseWInDPat<v4f32, v2i64, MSA128W>;
3615 def : MSABitconvertReverseBInDPat<v16i8, v2f64, MSA128B>;
3616 def : MSABitconvertReverseHInDPat<v8i16, v2f64, MSA128H>;
3617 def : MSABitconvertReverseHInDPat<v8f16, v2f64, MSA128H>;
3618 def : MSABitconvertReverseWInDPat<v4i32, v2f64, MSA128W>;
3619 def : MSABitconvertReverseWInDPat<v4f32, v2f64, MSA128W>;
3621 // Pseudos used to implement BNZ.df, and BZ.df
3623 class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode,
3625 InstrItinClass itin = NoItinerary> :
3626 MipsPseudo<(outs GPR32:$dst),
3628 [(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> {
3629 bit usesCustomInserter = 1;
3632 def SNZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8,
3633 MSA128B, NoItinerary>;
3634 def SNZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16,
3635 MSA128H, NoItinerary>;
3636 def SNZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32,
3637 MSA128W, NoItinerary>;
3638 def SNZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64,
3639 MSA128D, NoItinerary>;
3640 def SNZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8,
3641 MSA128B, NoItinerary>;
3643 def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8,
3644 MSA128B, NoItinerary>;
3645 def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16,
3646 MSA128H, NoItinerary>;
3647 def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32,
3648 MSA128W, NoItinerary>;
3649 def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64,
3650 MSA128D, NoItinerary>;
3651 def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8,
3652 MSA128B, NoItinerary>;