1 //===- MipsMSAInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 def HasMSA : Predicate<"Subtarget.hasMSA()">,
11 AssemblerPredicate<"FeatureMSA">;
13 class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
14 let Predicates = [HasMSA];
15 let Inst{31-26} = 0b011110;
18 class PseudoMSA<dag outs, dag ins, list<dag> pattern,
19 InstrItinClass itin = IIPseudo>:
20 MipsPseudo<outs, ins, pattern, itin> {
21 let Predicates = [HasMSA];
24 class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
25 let Inst{25-23} = major;
26 let Inst{22-19} = 0b1110;
27 let Inst{5-0} = minor;
30 class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {
31 let Inst{25-23} = major;
32 let Inst{22-20} = 0b110;
33 let Inst{5-0} = minor;
36 class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {
37 let Inst{25-23} = major;
38 let Inst{22-21} = 0b10;
39 let Inst{5-0} = minor;
42 class MSA_BIT_D_FMT<bits<3> major, bits<6> minor>: MSAInst {
43 let Inst{25-23} = major;
45 let Inst{5-0} = minor;
48 class MSA_2R_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
49 let Inst{25-18} = major;
51 let Inst{5-0} = minor;
54 class MSA_2RF_FMT<bits<9> major, bits<1> df, bits<6> minor>: MSAInst {
58 let Inst{25-17} = major;
62 let Inst{5-0} = minor;
65 class MSA_3R_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
66 let Inst{25-23} = major;
68 let Inst{5-0} = minor;
71 class MSA_3RF_FMT<bits<4> major, bits<1> df, bits<6> minor>: MSAInst {
72 let Inst{25-22} = major;
74 let Inst{5-0} = minor;
77 class MSA_ELM_FMT<bits<10> major, bits<6> minor>: MSAInst {
78 let Inst{25-16} = major;
79 let Inst{5-0} = minor;
82 class MSA_ELM_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
83 let Inst{25-22} = major;
84 let Inst{21-20} = 0b00;
85 let Inst{5-0} = minor;
88 class MSA_ELM_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
89 let Inst{25-22} = major;
90 let Inst{21-19} = 0b100;
91 let Inst{5-0} = minor;
94 class MSA_ELM_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
95 let Inst{25-22} = major;
96 let Inst{21-18} = 0b1100;
97 let Inst{5-0} = minor;
100 class MSA_ELM_D_FMT<bits<4> major, bits<6> minor>: MSAInst {
101 let Inst{25-22} = major;
102 let Inst{21-17} = 0b11100;
103 let Inst{5-0} = minor;
106 class MSA_I5_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
107 let Inst{25-23} = major;
108 let Inst{22-21} = df;
109 let Inst{5-0} = minor;
112 class MSA_I8_FMT<bits<2> major, bits<6> minor>: MSAInst {
113 let Inst{25-24} = major;
114 let Inst{5-0} = minor;
117 class MSA_I10_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
118 let Inst{25-23} = major;
119 let Inst{22-21} = df;
120 let Inst{5-0} = minor;
123 class MSA_VEC_FMT<bits<5> major, bits<6> minor>: MSAInst {
124 let Inst{25-21} = major;
125 let Inst{5-0} = minor;
128 class MSA_VECS10_FMT<bits<5> major, bits<6> minor>: MSAInst {
129 let Inst{25-21} = major;
130 let Inst{5-0} = minor;