1 //===- MipsMSAInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 def HasMSA : Predicate<"Subtarget.hasMSA()">,
11 AssemblerPredicate<"FeatureMSA">;
13 class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
14 let Predicates = [HasMSA];
15 let Inst{31-26} = 0b011110;
18 class PseudoMSA<dag outs, dag ins, list<dag> pattern,
19 InstrItinClass itin = IIPseudo>:
20 MipsPseudo<outs, ins, pattern, itin> {
21 let Predicates = [HasMSA];
24 class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
29 let Inst{25-23} = major;
30 let Inst{22-19} = 0b1110;
34 let Inst{5-0} = minor;
37 class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {
42 let Inst{25-23} = major;
43 let Inst{22-20} = 0b110;
47 let Inst{5-0} = minor;
50 class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {
55 let Inst{25-23} = major;
56 let Inst{22-21} = 0b10;
60 let Inst{5-0} = minor;
63 class MSA_BIT_D_FMT<bits<3> major, bits<6> minor>: MSAInst {
68 let Inst{25-23} = major;
73 let Inst{5-0} = minor;
76 class MSA_2R_FILL_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
80 let Inst{25-18} = major;
84 let Inst{5-0} = minor;
87 class MSA_2R_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
91 let Inst{25-18} = major;
95 let Inst{5-0} = minor;
98 class MSA_2RF_FMT<bits<9> major, bits<1> df, bits<6> minor>: MSAInst {
102 let Inst{25-17} = major;
104 let Inst{15-11} = ws;
106 let Inst{5-0} = minor;
109 class MSA_3R_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
114 let Inst{25-23} = major;
115 let Inst{22-21} = df;
116 let Inst{20-16} = wt;
117 let Inst{15-11} = ws;
119 let Inst{5-0} = minor;
122 class MSA_3RF_FMT<bits<4> major, bits<1> df, bits<6> minor>: MSAInst {
127 let Inst{25-22} = major;
129 let Inst{20-16} = wt;
130 let Inst{15-11} = ws;
132 let Inst{5-0} = minor;
135 class MSA_ELM_FMT<bits<10> major, bits<6> minor>: MSAInst {
136 let Inst{25-16} = major;
137 let Inst{5-0} = minor;
140 class MSA_ELM_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
145 let Inst{25-22} = major;
146 let Inst{21-20} = 0b00;
147 let Inst{19-16} = n{3-0};
148 let Inst{15-11} = ws;
150 let Inst{5-0} = minor;
153 class MSA_ELM_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
158 let Inst{25-22} = major;
159 let Inst{21-19} = 0b100;
160 let Inst{18-16} = n{2-0};
161 let Inst{15-11} = ws;
163 let Inst{5-0} = minor;
166 class MSA_ELM_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
171 let Inst{25-22} = major;
172 let Inst{21-18} = 0b1100;
173 let Inst{17-16} = n{1-0};
174 let Inst{15-11} = ws;
176 let Inst{5-0} = minor;
179 class MSA_ELM_D_FMT<bits<4> major, bits<6> minor>: MSAInst {
184 let Inst{25-22} = major;
185 let Inst{21-17} = 0b11100;
187 let Inst{15-11} = ws;
189 let Inst{5-0} = minor;
192 class MSA_ELM_COPY_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
197 let Inst{25-22} = major;
198 let Inst{21-20} = 0b00;
199 let Inst{19-16} = n{3-0};
200 let Inst{15-11} = ws;
202 let Inst{5-0} = minor;
205 class MSA_ELM_COPY_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
210 let Inst{25-22} = major;
211 let Inst{21-19} = 0b100;
212 let Inst{18-16} = n{2-0};
213 let Inst{15-11} = ws;
215 let Inst{5-0} = minor;
218 class MSA_ELM_COPY_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
223 let Inst{25-22} = major;
224 let Inst{21-18} = 0b1100;
225 let Inst{17-16} = n{1-0};
226 let Inst{15-11} = ws;
228 let Inst{5-0} = minor;
231 class MSA_ELM_INSERT_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
236 let Inst{25-22} = major;
237 let Inst{21-20} = 0b00;
238 let Inst{19-16} = n{3-0};
239 let Inst{15-11} = rs;
241 let Inst{5-0} = minor;
244 class MSA_ELM_INSERT_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
249 let Inst{25-22} = major;
250 let Inst{21-19} = 0b100;
251 let Inst{18-16} = n{2-0};
252 let Inst{15-11} = rs;
254 let Inst{5-0} = minor;
257 class MSA_ELM_INSERT_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
262 let Inst{25-22} = major;
263 let Inst{21-18} = 0b1100;
264 let Inst{17-16} = n{1-0};
265 let Inst{15-11} = rs;
267 let Inst{5-0} = minor;
270 class MSA_I5_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
275 let Inst{25-23} = major;
276 let Inst{22-21} = df;
277 let Inst{20-16} = imm;
278 let Inst{15-11} = ws;
280 let Inst{5-0} = minor;
283 class MSA_I8_FMT<bits<2> major, bits<6> minor>: MSAInst {
288 let Inst{25-24} = major;
289 let Inst{23-16} = u8;
290 let Inst{15-11} = ws;
292 let Inst{5-0} = minor;
295 class MSA_I10_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
296 let Inst{25-23} = major;
297 let Inst{22-21} = df;
298 let Inst{5-0} = minor;
301 class MSA_VEC_FMT<bits<5> major, bits<6> minor>: MSAInst {
306 let Inst{25-21} = major;
307 let Inst{20-16} = wt;
308 let Inst{15-11} = ws;
310 let Inst{5-0} = minor;
313 class MSA_VECS10_FMT<bits<5> major, bits<6> minor>: MSAInst {
314 let Inst{25-21} = major;
315 let Inst{5-0} = minor;