1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "MipsInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Mips profiles and nodes
22 //===----------------------------------------------------------------------===//
24 def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
25 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
26 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
30 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
31 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
32 def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
33 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
36 def SDT_MipsDivRem : SDTypeProfile<0, 2,
40 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
42 def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
44 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
46 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
47 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
48 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
49 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
53 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
57 // Hi and Lo nodes are used to handle global addresses. Used on
58 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
59 // static model. (nothing to do with Mips Registers Hi and Lo)
60 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
61 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
62 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
64 // TlsGd node is used to handle General Dynamic TLS
65 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
67 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
68 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
69 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
72 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
75 def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
78 // These are target-independent nodes, but have target-specific formats.
79 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
80 [SDNPHasChain, SDNPOutGlue]>;
81 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
85 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
86 [SDNPOptInGlue, SDNPOutGlue]>;
87 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
88 [SDNPOptInGlue, SDNPOutGlue]>;
89 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
90 [SDNPOptInGlue, SDNPOutGlue]>;
91 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
92 [SDNPOptInGlue, SDNPOutGlue]>;
95 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
97 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
100 // Target constant nodes that are not part of any isel patterns and remain
101 // unchanged can cause instructions with illegal operands to be emitted.
102 // Wrapper node patterns give the instruction selector a chance to replace
103 // target constant nodes that would otherwise remain unchanged with ADDiu
104 // nodes. Without these wrapper node patterns, the following conditional move
105 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
107 // movn %got(d)($gp), %got(c)($gp), $4
108 // This instruction is illegal since movn can take only register operands.
110 def MipsWrapperPIC : SDNode<"MipsISD::WrapperPIC", SDTIntUnaryOp>;
112 // Pointer to dynamically allocated stack area.
113 def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc,
114 [SDNPHasChain, SDNPInGlue]>;
116 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain]>;
118 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
119 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
121 //===----------------------------------------------------------------------===//
122 // Mips Instruction Predicate Definitions.
123 //===----------------------------------------------------------------------===//
124 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
125 def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
126 def HasSwap : Predicate<"Subtarget.hasSwap()">;
127 def HasCondMov : Predicate<"Subtarget.hasCondMov()">;
128 def HasMips32 : Predicate<"Subtarget.hasMips32()">;
129 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">;
130 def HasMips64 : Predicate<"Subtarget.hasMips64()">;
131 def NotMips64 : Predicate<"!Subtarget.hasMips64()">;
132 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">;
133 def IsN64 : Predicate<"Subtarget.isABI_N64()">;
134 def NotN64 : Predicate<"!Subtarget.isABI_N64()">;
136 //===----------------------------------------------------------------------===//
137 // Mips Operand, Complex Patterns and Transformations Definitions.
138 //===----------------------------------------------------------------------===//
140 // Instruction operand types
141 def brtarget : Operand<OtherVT>;
142 def calltarget : Operand<i32>;
143 def simm16 : Operand<i32>;
144 def simm16_64 : Operand<i64>;
145 def shamt : Operand<i32>;
148 def uimm16 : Operand<i32> {
149 let PrintMethod = "printUnsignedImm";
153 def mem : Operand<i32> {
154 let PrintMethod = "printMemOperand";
155 let MIOperandInfo = (ops CPURegs, simm16);
158 def mem64 : Operand<i64> {
159 let PrintMethod = "printMemOperand";
160 let MIOperandInfo = (ops CPU64Regs, simm16_64);
163 def mem_ea : Operand<i32> {
164 let PrintMethod = "printMemOperandEA";
165 let MIOperandInfo = (ops CPURegs, simm16);
168 // Transformation Function - get the lower 16 bits.
169 def LO16 : SDNodeXForm<imm, [{
170 return getI32Imm((unsigned)N->getZExtValue() & 0xFFFF);
173 // Transformation Function - get the higher 16 bits.
174 def HI16 : SDNodeXForm<imm, [{
175 return getI32Imm((unsigned)N->getZExtValue() >> 16);
178 // Node immediate fits as 16-bit sign extended on target immediate.
180 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
182 // Node immediate fits as 16-bit zero extended on target immediate.
183 // The LO16 param means that only the lower 16 bits of the node
184 // immediate are caught.
186 def immZExt16 : PatLeaf<(imm), [{
187 if (N->getValueType(0) == MVT::i32)
188 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
190 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
193 // shamt field must fit in 5 bits.
194 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
196 // Mips Address Mode! SDNode frameindex could possibily be a match
197 // since load and store instructions from stack used it.
198 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], []>;
200 //===----------------------------------------------------------------------===//
201 // Pattern fragment for load/store
202 //===----------------------------------------------------------------------===//
203 class UnalignedLoad<PatFrag Node> : PatFrag<(ops node:$ptr), (Node node:$ptr), [{
204 LoadSDNode *LD = cast<LoadSDNode>(N);
205 return LD->getMemoryVT().getSizeInBits()/8 > LD->getAlignment();
208 class AlignedLoad<PatFrag Node> : PatFrag<(ops node:$ptr), (Node node:$ptr), [{
209 LoadSDNode *LD = cast<LoadSDNode>(N);
210 return LD->getMemoryVT().getSizeInBits()/8 <= LD->getAlignment();
213 class UnalignedStore<PatFrag Node> : PatFrag<(ops node:$val, node:$ptr),
214 (Node node:$val, node:$ptr), [{
215 StoreSDNode *SD = cast<StoreSDNode>(N);
216 return SD->getMemoryVT().getSizeInBits()/8 > SD->getAlignment();
219 class AlignedStore<PatFrag Node> : PatFrag<(ops node:$val, node:$ptr),
220 (Node node:$val, node:$ptr), [{
221 StoreSDNode *SD = cast<StoreSDNode>(N);
222 return SD->getMemoryVT().getSizeInBits()/8 <= SD->getAlignment();
225 // Load/Store PatFrags.
226 def sextloadi16_a : AlignedLoad<sextloadi16>;
227 def zextloadi16_a : AlignedLoad<zextloadi16>;
228 def extloadi16_a : AlignedLoad<extloadi16>;
229 def load_a : AlignedLoad<load>;
230 def sextloadi32_a : AlignedLoad<sextloadi32>;
231 def zextloadi32_a : AlignedLoad<zextloadi32>;
232 def extloadi32_a : AlignedLoad<extloadi32>;
233 def truncstorei16_a : AlignedStore<truncstorei16>;
234 def store_a : AlignedStore<store>;
235 def truncstorei32_a : AlignedStore<truncstorei32>;
236 def sextloadi16_u : UnalignedLoad<sextloadi16>;
237 def zextloadi16_u : UnalignedLoad<zextloadi16>;
238 def extloadi16_u : UnalignedLoad<extloadi16>;
239 def load_u : UnalignedLoad<load>;
240 def sextloadi32_u : UnalignedLoad<sextloadi32>;
241 def zextloadi32_u : UnalignedLoad<zextloadi32>;
242 def extloadi32_u : UnalignedLoad<extloadi32>;
243 def truncstorei16_u : UnalignedStore<truncstorei16>;
244 def store_u : UnalignedStore<store>;
245 def truncstorei32_u : UnalignedStore<truncstorei32>;
247 //===----------------------------------------------------------------------===//
248 // Instructions specific format
249 //===----------------------------------------------------------------------===//
251 // Arithmetic and logical instructions with 3 register operands.
252 class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
253 InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
254 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
255 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
256 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], itin> {
258 let isCommutable = isComm;
261 class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm,
262 InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
263 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
264 !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], itin> {
266 let isCommutable = isComm;
269 // Arithmetic and logical instructions with 2 register operands.
270 class ArithLogicI<bits<6> op, string instr_asm, SDNode OpNode,
271 Operand Od, PatLeaf imm_type, RegisterClass RC> :
272 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$i),
273 !strconcat(instr_asm, "\t$rt, $rs, $i"),
274 [(set RC:$rt, (OpNode RC:$rs, imm_type:$i))], IIAlu>;
276 class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
277 Operand Od, PatLeaf imm_type, RegisterClass RC> :
278 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$i),
279 !strconcat(instr_asm, "\t$rt, $rs, $i"), [], IIAlu>;
281 // Arithmetic Multiply ADD/SUB
282 let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
283 class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> :
284 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
285 !strconcat(instr_asm, "\t$rs, $rt"),
286 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> {
289 let isCommutable = isComm;
293 class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>:
294 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
295 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
296 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> {
298 let isCommutable = 1;
302 class shift_rotate_imm<bits<6> func, bits<5> isRotate, string instr_asm,
303 SDNode OpNode, PatFrag PF, Operand ImmOpnd,
305 FR<0x00, func, (outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
306 !strconcat(instr_asm, "\t$rd, $rt, $shamt"),
307 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu> {
311 // 32-bit shift instructions.
312 class shift_rotate_imm32<bits<6> func, bits<5> isRotate, string instr_asm,
314 shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt, CPURegs>;
316 class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm,
317 SDNode OpNode, RegisterClass RC>:
318 FR<0x00, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
319 !strconcat(instr_asm, "\t$rd, $rt, $rs"),
320 [(set RC:$rd, (OpNode RC:$rt, RC:$rs))], IIAlu> {
321 let shamt = isRotate;
324 // Load Upper Imediate
325 class LoadUpper<bits<6> op, string instr_asm>:
326 FI<op, (outs CPURegs:$rt), (ins uimm16:$imm),
327 !strconcat(instr_asm, "\t$rt, $imm"), [], IIAlu> {
332 let canFoldAsLoad = 1 in
333 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
334 Operand MemOpnd, bit Pseudo>:
335 FI<op, (outs RC:$rt), (ins MemOpnd:$addr),
336 !strconcat(instr_asm, "\t$rt, $addr"),
337 [(set RC:$rt, (OpNode addr:$addr))], IILoad> {
338 let isPseudo = Pseudo;
341 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
342 Operand MemOpnd, bit Pseudo>:
343 FI<op, (outs), (ins RC:$rt, MemOpnd:$addr),
344 !strconcat(instr_asm, "\t$rt, $addr"),
345 [(OpNode RC:$rt, addr:$addr)], IIStore> {
346 let isPseudo = Pseudo;
350 multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode,
352 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
354 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
359 multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode,
361 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
363 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
368 multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode,
370 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
372 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
377 multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode,
379 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
381 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
385 // Conditional Branch
386 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>:
387 CBranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$offset),
388 !strconcat(instr_asm, "\t$rs, $rt, $offset"),
389 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch> {
391 let isTerminator = 1;
392 let hasDelaySlot = 1;
395 class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op,
397 CBranchBase<op, (outs), (ins RC:$rs, brtarget:$offset),
398 !strconcat(instr_asm, "\t$rs, $offset"),
399 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch> {
402 let isTerminator = 1;
403 let hasDelaySlot = 1;
407 class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op,
409 FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt),
410 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
411 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))],
416 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od,
417 PatLeaf imm_type, RegisterClass RC>:
418 FI<op, (outs CPURegs:$rd), (ins RC:$rs, Od:$i),
419 !strconcat(instr_asm, "\t$rd, $rs, $i"),
420 [(set CPURegs:$rd, (cond_op RC:$rs, imm_type:$i))],
423 // Unconditional branch
424 let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
425 class JumpFJ<bits<6> op, string instr_asm>:
426 FJ<op, (outs), (ins brtarget:$target),
427 !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch>;
429 let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in
430 class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
431 FR<op, func, (outs), (ins CPURegs:$rs),
432 !strconcat(instr_asm, "\t$rs"), [(brind CPURegs:$rs)], IIBranch> {
438 // Jump and Link (Call)
439 let isCall=1, hasDelaySlot=1,
440 // All calls clobber the non-callee saved registers...
441 Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
442 K0, K1, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9], Uses = [GP] in {
443 class JumpLink<bits<6> op, string instr_asm>:
444 FJ<op, (outs), (ins calltarget:$target, variable_ops),
445 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
448 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
449 FR<op, func, (outs), (ins CPURegs:$rs, variable_ops),
450 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink CPURegs:$rs)], IIBranch> {
456 class BranchLink<string instr_asm>:
457 FI<0x1, (outs), (ins CPURegs:$rs, brtarget:$target, variable_ops),
458 !strconcat(instr_asm, "\t$rs, $target"), [], IIBranch> {
464 class Mult<bits<6> func, string instr_asm, InstrItinClass itin,
465 RegisterClass RC, list<Register> DefRegs>:
466 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
467 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> {
470 let isCommutable = 1;
474 class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>:
475 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>;
477 class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin,
478 RegisterClass RC, list<Register> DefRegs>:
479 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
480 !strconcat(instr_asm, "\t$$zero, $rs, $rt"),
481 [(op RC:$rs, RC:$rt)], itin> {
487 class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
488 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>;
491 class MoveFromLOHI<bits<6> func, string instr_asm>:
492 FR<0x00, func, (outs CPURegs:$rd), (ins),
493 !strconcat(instr_asm, "\t$rd"), [], IIHiLo> {
499 class MoveToLOHI<bits<6> func, string instr_asm>:
500 FR<0x00, func, (outs), (ins CPURegs:$rs),
501 !strconcat(instr_asm, "\t$rs"), [], IIHiLo> {
507 class EffectiveAddress<string instr_asm> :
508 FI<0x09, (outs CPURegs:$rt), (ins mem_ea:$addr),
509 instr_asm, [(set CPURegs:$rt, addr:$addr)], IIAlu>;
511 // Count Leading Ones/Zeros in Word
512 class CountLeading<bits<6> func, string instr_asm, list<dag> pattern>:
513 FR<0x1c, func, (outs CPURegs:$rd), (ins CPURegs:$rs),
514 !strconcat(instr_asm, "\t$rd, $rs"), pattern, IIAlu>,
515 Requires<[HasBitCount]> {
520 // Sign Extend in Register.
521 class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt>:
522 FR<0x3f, 0x20, (outs CPURegs:$rd), (ins CPURegs:$rt),
523 !strconcat(instr_asm, "\t$rd, $rt"),
524 [(set CPURegs:$rd, (sext_inreg CPURegs:$rt, vt))], NoItinerary> {
527 let Predicates = [HasSEInReg];
531 class ByteSwap<bits<6> func, bits<5> sa, string instr_asm>:
532 FR<0x1f, func, (outs CPURegs:$rd), (ins CPURegs:$rt),
533 !strconcat(instr_asm, "\t$rd, $rt"),
534 [(set CPURegs:$rd, (bswap CPURegs:$rt))], NoItinerary> {
537 let Predicates = [HasSwap];
541 class ReadHardware: FR<0x1f, 0x3b, (outs CPURegs:$rt), (ins HWRegs:$rd),
542 "rdhwr\t$rt, $rd", [], IIAlu> {
548 class ExtIns<bits<6> _funct, string instr_asm, dag outs, dag ins,
549 list<dag> pattern, InstrItinClass itin>:
550 FR<0x1f, _funct, outs, ins, !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
551 pattern, itin>, Requires<[HasMips32r2]> {
558 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
559 class Atomic2Ops<PatFrag Op, string Opstr> :
560 MipsPseudo<(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
561 !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"),
563 (Op CPURegs:$ptr, CPURegs:$incr))]>;
565 // Atomic Compare & Swap.
566 class AtomicCmpSwap<PatFrag Op, string Width> :
567 MipsPseudo<(outs CPURegs:$dst),
568 (ins CPURegs:$ptr, CPURegs:$cmp, CPURegs:$swap),
569 !strconcat("atomic_cmp_swap_", Width,
570 "\t$dst, $ptr, $cmp, $swap"),
572 (Op CPURegs:$ptr, CPURegs:$cmp, CPURegs:$swap))]>;
574 //===----------------------------------------------------------------------===//
575 // Pseudo instructions
576 //===----------------------------------------------------------------------===//
578 // As stack alignment is always done with addiu, we need a 16-bit immediate
579 let Defs = [SP], Uses = [SP] in {
580 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
581 "!ADJCALLSTACKDOWN $amt",
582 [(callseq_start timm:$amt)]>;
583 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
584 "!ADJCALLSTACKUP $amt1",
585 [(callseq_end timm:$amt1, timm:$amt2)]>;
588 // Some assembly macros need to avoid pseudoinstructions and assembler
589 // automatic reodering, we should reorder ourselves.
590 def MACRO : MipsPseudo<(outs), (ins), ".set\tmacro", []>;
591 def REORDER : MipsPseudo<(outs), (ins), ".set\treorder", []>;
592 def NOMACRO : MipsPseudo<(outs), (ins), ".set\tnomacro", []>;
593 def NOREORDER : MipsPseudo<(outs), (ins), ".set\tnoreorder", []>;
595 // These macros are inserted to prevent GAS from complaining
596 // when using the AT register.
597 def NOAT : MipsPseudo<(outs), (ins), ".set\tnoat", []>;
598 def ATMACRO : MipsPseudo<(outs), (ins), ".set\tat", []>;
600 // When handling PIC code the assembler needs .cpload and .cprestore
601 // directives. If the real instructions corresponding these directives
602 // are used, we have the same behavior, but get also a bunch of warnings
603 // from the assembler.
604 def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
605 def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc), ".cprestore\t$loc", []>;
607 let usesCustomInserter = 1 in {
608 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, "load_add_8">;
609 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, "load_add_16">;
610 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, "load_add_32">;
611 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, "load_sub_8">;
612 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, "load_sub_16">;
613 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, "load_sub_32">;
614 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, "load_and_8">;
615 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, "load_and_16">;
616 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, "load_and_32">;
617 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, "load_or_8">;
618 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, "load_or_16">;
619 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, "load_or_32">;
620 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, "load_xor_8">;
621 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, "load_xor_16">;
622 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, "load_xor_32">;
623 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, "load_nand_8">;
624 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, "load_nand_16">;
625 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, "load_nand_32">;
627 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, "swap_8">;
628 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, "swap_16">;
629 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, "swap_32">;
631 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, "8">;
632 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, "16">;
633 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, "32">;
636 //===----------------------------------------------------------------------===//
637 // Instruction definition
638 //===----------------------------------------------------------------------===//
640 //===----------------------------------------------------------------------===//
641 // MipsI Instructions
642 //===----------------------------------------------------------------------===//
644 /// Arithmetic Instructions (ALU Immediate)
645 def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>;
646 def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16, CPURegs>;
647 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>;
648 def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;
649 def ANDi : ArithLogicI<0x0c, "andi", and, uimm16, immZExt16, CPURegs>;
650 def ORi : ArithLogicI<0x0d, "ori", or, uimm16, immZExt16, CPURegs>;
651 def XORi : ArithLogicI<0x0e, "xori", xor, uimm16, immZExt16, CPURegs>;
652 def LUi : LoadUpper<0x0f, "lui">;
654 /// Arithmetic Instructions (3-Operand, R-Type)
655 def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>;
656 def SUBu : ArithLogicR<0x00, 0x23, "subu", sub, IIAlu, CPURegs>;
657 def ADD : ArithOverflowR<0x00, 0x20, "add", IIAlu, CPURegs, 1>;
658 def SUB : ArithOverflowR<0x00, 0x22, "sub", IIAlu, CPURegs>;
659 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>;
660 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>;
661 def AND : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>;
662 def OR : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPURegs, 1>;
663 def XOR : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPURegs, 1>;
664 def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>;
666 /// Shift Instructions
667 def SLL : shift_rotate_imm32<0x00, 0x00, "sll", shl>;
668 def SRL : shift_rotate_imm32<0x02, 0x00, "srl", srl>;
669 def SRA : shift_rotate_imm32<0x03, 0x00, "sra", sra>;
670 def SLLV : shift_rotate_reg<0x04, 0x00, "sllv", shl, CPURegs>;
671 def SRLV : shift_rotate_reg<0x06, 0x00, "srlv", srl, CPURegs>;
672 def SRAV : shift_rotate_reg<0x07, 0x00, "srav", sra, CPURegs>;
674 // Rotate Instructions
675 let Predicates = [HasMips32r2] in {
676 def ROTR : shift_rotate_imm32<0x02, 0x01, "rotr", rotr>;
677 def ROTRV : shift_rotate_reg<0x06, 0x01, "rotrv", rotr, CPURegs>;
680 /// Load and Store Instructions
682 defm LB : LoadM32<0x20, "lb", sextloadi8>;
683 defm LBu : LoadM32<0x24, "lbu", zextloadi8>;
684 defm LH : LoadM32<0x21, "lh", sextloadi16_a>;
685 defm LHu : LoadM32<0x25, "lhu", zextloadi16_a>;
686 defm LW : LoadM32<0x23, "lw", load_a>;
687 defm SB : StoreM32<0x28, "sb", truncstorei8>;
688 defm SH : StoreM32<0x29, "sh", truncstorei16_a>;
689 defm SW : StoreM32<0x2b, "sw", store_a>;
692 defm ULH : LoadM32<0x21, "ulh", sextloadi16_u, 1>;
693 defm ULHu : LoadM32<0x25, "ulhu", zextloadi16_u, 1>;
694 defm ULW : LoadM32<0x23, "ulw", load_u, 1>;
695 defm USH : StoreM32<0x29, "ush", truncstorei16_u, 1>;
696 defm USW : StoreM32<0x2b, "usw", store_u, 1>;
698 let hasSideEffects = 1 in
699 def SYNC : MipsInst<(outs), (ins i32imm:$stype), "sync $stype",
700 [(MipsSync imm:$stype)], NoItinerary>
707 /// Load-linked, Store-conditional
709 def LL : FI<0x30, (outs CPURegs:$dst), (ins mem:$addr),
710 "ll\t$dst, $addr", [], IILoad>;
711 let mayStore = 1, Constraints = "$src = $dst" in
712 def SC : FI<0x38, (outs CPURegs:$dst), (ins CPURegs:$src, mem:$addr),
713 "sc\t$src, $addr", [], IIStore>;
715 /// Jump and Branch Instructions
716 def J : JumpFJ<0x02, "j">;
717 let isIndirectBranch = 1 in
718 def JR : JumpFR<0x00, 0x08, "jr">;
719 def JAL : JumpLink<0x03, "jal">;
720 def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
721 def BEQ : CBranch<0x04, "beq", seteq, CPURegs>;
722 def BNE : CBranch<0x05, "bne", setne, CPURegs>;
723 def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>;
724 def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>;
725 def BLEZ : CBranchZero<0x07, 0, "blez", setle, CPURegs>;
726 def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>;
728 def BGEZAL : BranchLink<"bgezal">;
729 def BLTZAL : BranchLink<"bltzal">;
731 let isReturn=1, isTerminator=1, hasDelaySlot=1,
732 isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
733 def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
734 "jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
736 /// Multiply and Divide Instructions.
737 def MULT : Mult32<0x18, "mult", IIImul>;
738 def MULTu : Mult32<0x19, "multu", IIImul>;
739 def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>;
740 def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>;
743 def MTHI : MoveToLOHI<0x11, "mthi">;
745 def MTLO : MoveToLOHI<0x13, "mtlo">;
748 def MFHI : MoveFromLOHI<0x10, "mfhi">;
750 def MFLO : MoveFromLOHI<0x12, "mflo">;
752 /// Sign Ext In Register Instructions.
753 def SEB : SignExtInReg<0x10, "seb", i8>;
754 def SEH : SignExtInReg<0x18, "seh", i16>;
757 def CLZ : CountLeading<0x20, "clz",
758 [(set CPURegs:$rd, (ctlz CPURegs:$rs))]>;
759 def CLO : CountLeading<0x21, "clo",
760 [(set CPURegs:$rd, (ctlz (not CPURegs:$rs)))]>;
763 def WSBW : ByteSwap<0x20, 0x2, "wsbw">;
765 // Conditional moves:
766 // These instructions are expanded in
767 // MipsISelLowering::EmitInstrWithCustomInserter if target does not have
768 // conditional move instructions.
769 // flag:int, data:int
770 class CondMovIntInt<bits<6> funct, string instr_asm> :
771 FR<0, funct, (outs CPURegs:$rd),
772 (ins CPURegs:$rs, CPURegs:$rt, CPURegs:$F),
773 !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], NoItinerary> {
775 let usesCustomInserter = 1;
776 let Constraints = "$F = $rd";
779 def MOVZ_I : CondMovIntInt<0x0a, "movz">;
780 def MOVN_I : CondMovIntInt<0x0b, "movn">;
784 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
786 // FrameIndexes are legalized when they are operands from load/store
787 // instructions. The same not happens for stack address copies, so an
788 // add op with mem ComplexPattern is used and the stack address copy
789 // can be matched. It's similar to Sparc LEA_ADDRi
790 def LEA_ADDiu : EffectiveAddress<"addiu\t$rt, $addr">;
792 // DynAlloc node points to dynamically allocated stack space.
793 // $sp is added to the list of implicitly used registers to prevent dead code
794 // elimination from removing instructions that modify $sp.
796 def DynAlloc : EffectiveAddress<"addiu\t$rt, $addr">;
799 def MADD : MArithR<0, "madd", MipsMAdd, 1>;
800 def MADDU : MArithR<1, "maddu", MipsMAddu, 1>;
801 def MSUB : MArithR<4, "msub", MipsMSub>;
802 def MSUBU : MArithR<5, "msubu", MipsMSubu>;
804 // MUL is a assembly macro in the current used ISAs. In recent ISA's
805 // it is a real instruction.
806 def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>,
807 Requires<[HasMips32]>;
809 def RDHWR : ReadHardware;
811 def EXT : ExtIns<0, "ext", (outs CPURegs:$rt),
812 (ins CPURegs:$rs, uimm16:$pos, uimm16:$sz),
814 (MipsExt CPURegs:$rs, immZExt5:$pos, immZExt5:$sz))],
817 let Constraints = "$src = $rt" in
818 def INS : ExtIns<4, "ins", (outs CPURegs:$rt),
819 (ins CPURegs:$rs, uimm16:$pos, uimm16:$sz, CPURegs:$src),
821 (MipsIns CPURegs:$rs, immZExt5:$pos, immZExt5:$sz,
825 //===----------------------------------------------------------------------===//
826 // Arbitrary patterns that map to one or more instructions
827 //===----------------------------------------------------------------------===//
830 def : Pat<(i32 immSExt16:$in),
831 (ADDiu ZERO, imm:$in)>;
832 def : Pat<(i32 immZExt16:$in),
833 (ORi ZERO, imm:$in)>;
835 // Arbitrary immediates
836 def : Pat<(i32 imm:$imm),
837 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
840 def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs),
841 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
842 def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs),
843 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
844 def : Pat<(addc CPURegs:$src, immSExt16:$imm),
845 (ADDiu CPURegs:$src, imm:$imm)>;
848 def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
849 (JAL tglobaladdr:$dst)>;
850 def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
851 (JAL texternalsym:$dst)>;
852 //def : Pat<(MipsJmpLink CPURegs:$dst),
853 // (JALR CPURegs:$dst)>;
856 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
857 def : Pat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
858 def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
859 def : Pat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
860 def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
861 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
862 def : Pat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
863 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
865 def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
866 def : Pat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
867 def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
868 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
870 def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
871 def : Pat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
872 def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
873 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
876 def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
877 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
878 def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
879 (ADDiu CPURegs:$gp, tconstpool:$in)>;
882 def : Pat<(add CPURegs:$gp, (MipsTlsGd tglobaltlsaddr:$in)),
883 (ADDiu CPURegs:$gp, tglobaltlsaddr:$in)>;
886 def : Pat<(MipsTprelHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
887 def : Pat<(MipsTprelLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
888 def : Pat<(add CPURegs:$hi, (MipsTprelLo tglobaltlsaddr:$lo)),
889 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
892 class WrapperPICPat<SDNode node>:
893 Pat<(MipsWrapperPIC node:$in),
894 (ADDiu GP, node:$in)>;
896 def : WrapperPICPat<tglobaladdr>;
897 def : WrapperPICPat<tconstpool>;
898 def : WrapperPICPat<texternalsym>;
899 def : WrapperPICPat<tblockaddress>;
900 def : WrapperPICPat<tjumptable>;
902 // Mips does not have "not", so we expand our way
903 def : Pat<(not CPURegs:$in),
904 (NOR CPURegs:$in, ZERO)>;
906 // extended load and stores
907 def : Pat<(extloadi1 addr:$src), (LBu addr:$src)>;
908 def : Pat<(extloadi8 addr:$src), (LBu addr:$src)>;
909 def : Pat<(extloadi16_a addr:$src), (LHu addr:$src)>;
910 def : Pat<(extloadi16_u addr:$src), (ULHu addr:$src)>;
913 def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
916 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
917 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
918 Instruction SLTiuOp, Register ZEROReg> {
919 def : Pat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
920 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
921 def : Pat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
922 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
924 def : Pat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
925 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
926 def : Pat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
927 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
928 def : Pat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
929 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
930 def : Pat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
931 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
933 def : Pat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
934 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
935 def : Pat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
936 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
938 def : Pat<(brcond RC:$cond, bb:$dst),
939 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
942 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
945 multiclass MovzPats<RegisterClass RC, Instruction MOVZInst> {
946 def : Pat<(select (i32 (setge CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
947 (MOVZInst RC:$T, (SLT CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
948 def : Pat<(select (i32 (setuge CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
949 (MOVZInst RC:$T, (SLTu CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
950 def : Pat<(select (i32 (setge CPURegs:$lhs, immSExt16:$rhs)), RC:$T, RC:$F),
951 (MOVZInst RC:$T, (SLTi CPURegs:$lhs, immSExt16:$rhs), RC:$F)>;
952 def : Pat<(select (i32 (setuge CPURegs:$lh, immSExt16:$rh)), RC:$T, RC:$F),
953 (MOVZInst RC:$T, (SLTiu CPURegs:$lh, immSExt16:$rh), RC:$F)>;
954 def : Pat<(select (i32 (setle CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
955 (MOVZInst RC:$T, (SLT CPURegs:$rhs, CPURegs:$lhs), RC:$F)>;
956 def : Pat<(select (i32 (setule CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
957 (MOVZInst RC:$T, (SLTu CPURegs:$rhs, CPURegs:$lhs), RC:$F)>;
958 def : Pat<(select (i32 (seteq CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
959 (MOVZInst RC:$T, (XOR CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
960 def : Pat<(select (i32 (seteq CPURegs:$lhs, 0)), RC:$T, RC:$F),
961 (MOVZInst RC:$T, CPURegs:$lhs, RC:$F)>;
964 multiclass MovnPats<RegisterClass RC, Instruction MOVNInst> {
965 def : Pat<(select (i32 (setne CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
966 (MOVNInst RC:$T, (XOR CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
967 def : Pat<(select CPURegs:$cond, RC:$T, RC:$F),
968 (MOVNInst RC:$T, CPURegs:$cond, RC:$F)>;
969 def : Pat<(select (i32 (setne CPURegs:$lhs, 0)), RC:$T, RC:$F),
970 (MOVNInst RC:$T, CPURegs:$lhs, RC:$F)>;
973 defm : MovzPats<CPURegs, MOVZ_I>;
974 defm : MovnPats<CPURegs, MOVN_I>;
977 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
978 Instruction SLTuOp, Register ZEROReg> {
979 def : Pat<(seteq RC:$lhs, RC:$rhs),
980 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
981 def : Pat<(setne RC:$lhs, RC:$rhs),
982 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
985 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
986 def : Pat<(setle RC:$lhs, RC:$rhs),
987 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
988 def : Pat<(setule RC:$lhs, RC:$rhs),
989 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
992 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
993 def : Pat<(setgt RC:$lhs, RC:$rhs),
994 (SLTOp RC:$rhs, RC:$lhs)>;
995 def : Pat<(setugt RC:$lhs, RC:$rhs),
996 (SLTuOp RC:$rhs, RC:$lhs)>;
999 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1000 def : Pat<(setge RC:$lhs, RC:$rhs),
1001 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1002 def : Pat<(setuge RC:$lhs, RC:$rhs),
1003 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1006 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1007 Instruction SLTiuOp> {
1008 def : Pat<(setge RC:$lhs, immSExt16:$rhs),
1009 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1010 def : Pat<(setuge RC:$lhs, immSExt16:$rhs),
1011 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1014 defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
1015 defm : SetlePats<CPURegs, SLT, SLTu>;
1016 defm : SetgtPats<CPURegs, SLT, SLTu>;
1017 defm : SetgePats<CPURegs, SLT, SLTu>;
1018 defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
1020 // select MipsDynAlloc
1021 def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;
1023 //===----------------------------------------------------------------------===//
1024 // Floating Point Support
1025 //===----------------------------------------------------------------------===//
1027 include "MipsInstrFPU.td"
1028 include "Mips64InstrInfo.td"