1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
30 def SDT_MipsDivRem : SDTypeProfile<0, 2,
34 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
36 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
38 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
39 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
40 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
44 def SDTMipsLoadLR : SDTypeProfile<1, 2,
45 [SDTCisInt<0>, SDTCisPtrTy<1>,
49 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
50 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
54 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
55 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
57 // Hi and Lo nodes are used to handle global addresses. Used on
58 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
59 // static model. (nothing to do with Mips Registers Hi and Lo)
60 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
61 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
62 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
64 // TlsGd node is used to handle General Dynamic TLS
65 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
67 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
68 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
69 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
72 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
75 def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>;
77 // These are target-independent nodes, but have target-specific formats.
78 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
79 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
80 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
81 [SDNPHasChain, SDNPSideEffect,
82 SDNPOptInGlue, SDNPOutGlue]>;
85 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
86 [SDNPOptInGlue, SDNPOutGlue]>;
87 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
88 [SDNPOptInGlue, SDNPOutGlue]>;
89 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
90 [SDNPOptInGlue, SDNPOutGlue]>;
91 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
92 [SDNPOptInGlue, SDNPOutGlue]>;
95 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
97 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
100 // Target constant nodes that are not part of any isel patterns and remain
101 // unchanged can cause instructions with illegal operands to be emitted.
102 // Wrapper node patterns give the instruction selector a chance to replace
103 // target constant nodes that would otherwise remain unchanged with ADDiu
104 // nodes. Without these wrapper node patterns, the following conditional move
105 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
107 // movn %got(d)($gp), %got(c)($gp), $4
108 // This instruction is illegal since movn can take only register operands.
110 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
112 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
114 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
115 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
117 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
118 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
119 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
120 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
121 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
122 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
123 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
124 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
125 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
126 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
127 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
128 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
129 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
130 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
131 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
132 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
134 //===----------------------------------------------------------------------===//
135 // Mips Instruction Predicate Definitions.
136 //===----------------------------------------------------------------------===//
137 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
138 AssemblerPredicate<"FeatureSEInReg">;
139 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
140 AssemblerPredicate<"FeatureBitCount">;
141 def HasSwap : Predicate<"Subtarget.hasSwap()">,
142 AssemblerPredicate<"FeatureSwap">;
143 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
144 AssemblerPredicate<"FeatureCondMov">;
145 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
146 AssemblerPredicate<"FeatureFPIdx">;
147 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
148 AssemblerPredicate<"FeatureMips32">;
149 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
150 AssemblerPredicate<"FeatureMips32r2">;
151 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
152 AssemblerPredicate<"FeatureMips64">;
153 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
154 AssemblerPredicate<"!FeatureMips64">;
155 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
156 AssemblerPredicate<"FeatureMips64r2">;
157 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
158 AssemblerPredicate<"FeatureN64">;
159 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
160 AssemblerPredicate<"!FeatureN64">;
161 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
162 AssemblerPredicate<"FeatureMips16">;
163 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
164 AssemblerPredicate<"FeatureMips32">;
165 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
166 AssemblerPredicate<"FeatureMips32">;
167 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
168 AssemblerPredicate<"FeatureMips32">;
169 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
170 AssemblerPredicate<"!FeatureMips16">;
172 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
173 let Predicates = [HasStdEnc];
177 bit isCommutable = 1;
194 bit isTerminator = 1;
197 bit hasExtraSrcRegAllocReq = 1;
198 bit isCodeGenOnly = 1;
201 class IsAsCheapAsAMove {
202 bit isAsCheapAsAMove = 1;
205 class NeverHasSideEffects {
206 bit neverHasSideEffects = 1;
209 //===----------------------------------------------------------------------===//
210 // Instruction format superclass
211 //===----------------------------------------------------------------------===//
213 include "MipsInstrFormats.td"
215 //===----------------------------------------------------------------------===//
216 // Mips Operand, Complex Patterns and Transformations Definitions.
217 //===----------------------------------------------------------------------===//
219 // Instruction operand types
220 def jmptarget : Operand<OtherVT> {
221 let EncoderMethod = "getJumpTargetOpValue";
223 def brtarget : Operand<OtherVT> {
224 let EncoderMethod = "getBranchTargetOpValue";
225 let OperandType = "OPERAND_PCREL";
226 let DecoderMethod = "DecodeBranchTarget";
228 def calltarget : Operand<iPTR> {
229 let EncoderMethod = "getJumpTargetOpValue";
231 def calltarget64: Operand<i64>;
232 def simm16 : Operand<i32> {
233 let DecoderMethod= "DecodeSimm16";
235 def simm16_64 : Operand<i64>;
236 def shamt : Operand<i32>;
239 def uimm16 : Operand<i32> {
240 let PrintMethod = "printUnsignedImm";
243 def MipsMemAsmOperand : AsmOperandClass {
245 let ParserMethod = "parseMemOperand";
249 def mem : Operand<i32> {
250 let PrintMethod = "printMemOperand";
251 let MIOperandInfo = (ops CPURegs, simm16);
252 let EncoderMethod = "getMemEncoding";
253 let ParserMatchClass = MipsMemAsmOperand;
256 def mem64 : Operand<i64> {
257 let PrintMethod = "printMemOperand";
258 let MIOperandInfo = (ops CPU64Regs, simm16_64);
259 let EncoderMethod = "getMemEncoding";
260 let ParserMatchClass = MipsMemAsmOperand;
263 def mem_ea : Operand<i32> {
264 let PrintMethod = "printMemOperandEA";
265 let MIOperandInfo = (ops CPURegs, simm16);
266 let EncoderMethod = "getMemEncoding";
269 def mem_ea_64 : Operand<i64> {
270 let PrintMethod = "printMemOperandEA";
271 let MIOperandInfo = (ops CPU64Regs, simm16_64);
272 let EncoderMethod = "getMemEncoding";
275 // size operand of ext instruction
276 def size_ext : Operand<i32> {
277 let EncoderMethod = "getSizeExtEncoding";
278 let DecoderMethod = "DecodeExtSize";
281 // size operand of ins instruction
282 def size_ins : Operand<i32> {
283 let EncoderMethod = "getSizeInsEncoding";
284 let DecoderMethod = "DecodeInsSize";
287 // Transformation Function - get the lower 16 bits.
288 def LO16 : SDNodeXForm<imm, [{
289 return getImm(N, N->getZExtValue() & 0xFFFF);
292 // Transformation Function - get the higher 16 bits.
293 def HI16 : SDNodeXForm<imm, [{
294 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
297 // Node immediate fits as 16-bit sign extended on target immediate.
299 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
301 // Node immediate fits as 16-bit zero extended on target immediate.
302 // The LO16 param means that only the lower 16 bits of the node
303 // immediate are caught.
305 def immZExt16 : PatLeaf<(imm), [{
306 if (N->getValueType(0) == MVT::i32)
307 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
309 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
312 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
313 def immLow16Zero : PatLeaf<(imm), [{
314 int64_t Val = N->getSExtValue();
315 return isInt<32>(Val) && !(Val & 0xffff);
318 // shamt field must fit in 5 bits.
319 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
321 // Mips Address Mode! SDNode frameindex could possibily be a match
322 // since load and store instructions from stack used it.
324 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>;
326 //===----------------------------------------------------------------------===//
327 // Instructions specific format
328 //===----------------------------------------------------------------------===//
330 /// Move Control Registers From/To CPU Registers
331 def MFC0_3OP : MFC3OP<0x10, 0, (outs CPURegs:$rt),
332 (ins CPURegs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">;
333 def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegs:$rt, CPURegs:$rd, 0)>;
335 def MTC0_3OP : MFC3OP<0x10, 4, (outs CPURegs:$rd, uimm16:$sel),
336 (ins CPURegs:$rt),"mtc0\t$rt, $rd, $sel">;
337 def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegs:$rd, 0, CPURegs:$rt)>;
339 def MFC2_3OP : MFC3OP<0x12, 0, (outs CPURegs:$rt),
340 (ins CPURegs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">;
341 def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegs:$rt, CPURegs:$rd, 0)>;
343 def MTC2_3OP : MFC3OP<0x12, 4, (outs CPURegs:$rd, uimm16:$sel),
344 (ins CPURegs:$rt),"mtc2\t$rt, $rd, $sel">;
345 def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>;
347 // Arithmetic and logical instructions with 3 register operands.
348 class ArithLogicR<bits<6> op, bits<6> func, string instr_asm,
349 InstrItinClass itin, RegisterClass RC, bit isComm = 0,
350 SDPatternOperator OpNode = null_frag>:
351 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
352 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
353 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], itin> {
355 let isCommutable = isComm;
356 let isReMaterializable = 1;
359 // Arithmetic and logical instructions with 2 register operands.
360 class ArithLogicI<bits<6> op, string instr_asm, Operand Od, PatLeaf imm_type,
361 RegisterClass RC, SDPatternOperator OpNode = null_frag> :
362 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
363 !strconcat(instr_asm, "\t$rt, $rs, $imm16"),
364 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu> {
365 let isReMaterializable = 1;
368 // Arithmetic Multiply ADD/SUB
369 let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
370 class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> :
371 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
372 !strconcat(instr_asm, "\t$rs, $rt"),
373 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> {
376 let isCommutable = isComm;
380 class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>:
381 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
382 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
383 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> {
385 let isCommutable = 1;
389 class shift_rotate_imm<bits<6> func, bits<5> isRotate, string instr_asm,
390 SDNode OpNode, PatFrag PF, Operand ImmOpnd,
392 FR<0x00, func, (outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
393 !strconcat(instr_asm, "\t$rd, $rt, $shamt"),
394 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu> {
398 // 32-bit shift instructions.
399 class shift_rotate_imm32<bits<6> func, bits<5> isRotate, string instr_asm,
401 shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt, CPURegs>;
403 class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm,
404 SDNode OpNode, RegisterClass RC>:
405 FR<0x00, func, (outs RC:$rd), (ins CPURegs:$rs, RC:$rt),
406 !strconcat(instr_asm, "\t$rd, $rt, $rs"),
407 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu> {
408 let shamt = isRotate;
411 // Load Upper Imediate
412 class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>:
413 FI<op, (outs RC:$rt), (ins Imm:$imm16),
414 !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu>, IsAsCheapAsAMove {
416 let neverHasSideEffects = 1;
417 let isReMaterializable = 1;
420 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
421 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
423 let Inst{25-21} = addr{20-16};
424 let Inst{15-0} = addr{15-0};
425 let DecoderMethod = "DecodeMem";
429 let canFoldAsLoad = 1 in
430 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
431 Operand MemOpnd, bit Pseudo>:
432 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr),
433 !strconcat(instr_asm, "\t$rt, $addr"),
434 [(set RC:$rt, (OpNode addr:$addr))], IILoad> {
435 let isPseudo = Pseudo;
438 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
439 Operand MemOpnd, bit Pseudo>:
440 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
441 !strconcat(instr_asm, "\t$rt, $addr"),
442 [(OpNode RC:$rt, addr:$addr)], IIStore> {
443 let isPseudo = Pseudo;
447 multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode,
449 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
450 Requires<[NotN64, HasStdEnc]>;
451 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
452 Requires<[IsN64, HasStdEnc]> {
453 let DecoderNamespace = "Mips64";
454 let isCodeGenOnly = 1;
459 multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode,
461 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
462 Requires<[NotN64, HasStdEnc]>;
463 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
464 Requires<[IsN64, HasStdEnc]> {
465 let DecoderNamespace = "Mips64";
466 let isCodeGenOnly = 1;
471 multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode,
473 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
474 Requires<[NotN64, HasStdEnc]>;
475 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
476 Requires<[IsN64, HasStdEnc]> {
477 let DecoderNamespace = "Mips64";
478 let isCodeGenOnly = 1;
483 multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode,
485 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
486 Requires<[NotN64, HasStdEnc]>;
487 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
488 Requires<[IsN64, HasStdEnc]> {
489 let DecoderNamespace = "Mips64";
490 let isCodeGenOnly = 1;
494 // Load/Store Left/Right
495 let canFoldAsLoad = 1 in
496 class LoadLeftRight<bits<6> op, string instr_asm, SDNode OpNode,
497 RegisterClass RC, Operand MemOpnd> :
498 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr, RC:$src),
499 !strconcat(instr_asm, "\t$rt, $addr"),
500 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], IILoad> {
501 string Constraints = "$src = $rt";
504 class StoreLeftRight<bits<6> op, string instr_asm, SDNode OpNode,
505 RegisterClass RC, Operand MemOpnd>:
506 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
507 !strconcat(instr_asm, "\t$rt, $addr"), [(OpNode RC:$rt, addr:$addr)],
510 // 32-bit load left/right.
511 multiclass LoadLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> {
512 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem>,
513 Requires<[NotN64, HasStdEnc]>;
514 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem64>,
515 Requires<[IsN64, HasStdEnc]> {
516 let DecoderNamespace = "Mips64";
517 let isCodeGenOnly = 1;
521 // 64-bit load left/right.
522 multiclass LoadLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> {
523 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>,
524 Requires<[NotN64, HasStdEnc]>;
525 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>,
526 Requires<[IsN64, HasStdEnc]> {
527 let DecoderNamespace = "Mips64";
528 let isCodeGenOnly = 1;
532 // 32-bit store left/right.
533 multiclass StoreLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> {
534 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem>,
535 Requires<[NotN64, HasStdEnc]>;
536 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem64>,
537 Requires<[IsN64, HasStdEnc]> {
538 let DecoderNamespace = "Mips64";
539 let isCodeGenOnly = 1;
543 // 64-bit store left/right.
544 multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> {
545 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>,
546 Requires<[NotN64, HasStdEnc]>;
547 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>,
548 Requires<[IsN64, HasStdEnc]> {
549 let DecoderNamespace = "Mips64";
550 let isCodeGenOnly = 1;
554 // Conditional Branch
555 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>:
556 BranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$imm16),
557 !strconcat(instr_asm, "\t$rs, $rt, $imm16"),
558 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> {
560 let isTerminator = 1;
561 let hasDelaySlot = 1;
565 class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op,
567 BranchBase<op, (outs), (ins RC:$rs, brtarget:$imm16),
568 !strconcat(instr_asm, "\t$rs, $imm16"),
569 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> {
572 let isTerminator = 1;
573 let hasDelaySlot = 1;
578 class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op,
580 FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt),
581 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
582 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))],
587 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od,
588 PatLeaf imm_type, RegisterClass RC>:
589 FI<op, (outs CPURegs:$rt), (ins RC:$rs, Od:$imm16),
590 !strconcat(instr_asm, "\t$rt, $rs, $imm16"),
591 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))],
595 class JumpFJ<bits<6> op, DAGOperand opnd, string instr_asm,
596 SDPatternOperator operator, SDPatternOperator targetoperator>:
597 FJ<op, (outs), (ins opnd:$target), !strconcat(instr_asm, "\t$target"),
598 [(operator targetoperator:$target)], IIBranch> {
601 let hasDelaySlot = 1;
602 let DecoderMethod = "DecodeJumpTarget";
606 // Unconditional branch
607 class UncondBranch<bits<6> op, string instr_asm>:
608 BranchBase<op, (outs), (ins brtarget:$imm16),
609 !strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> {
613 let isTerminator = 1;
615 let hasDelaySlot = 1;
616 let Predicates = [RelocPIC, HasStdEnc];
620 // Base class for indirect branch and return instruction classes.
621 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
622 class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>:
623 FR<0, 0x8, (outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch> {
630 class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> {
632 let isIndirectBranch = 1;
635 // Return instruction
636 class RetBase<RegisterClass RC>: JumpFR<RC> {
638 let isCodeGenOnly = 1;
640 let hasExtraSrcRegAllocReq = 1;
643 // Jump and Link (Call)
644 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
645 class JumpLink<bits<6> op, string instr_asm>:
646 FJ<op, (outs), (ins calltarget:$target),
647 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
649 let DecoderMethod = "DecodeJumpTarget";
652 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm,
654 FR<op, func, (outs), (ins RC:$rs),
655 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> {
661 class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>:
662 FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16),
663 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> {
669 class Mult<bits<6> func, string instr_asm, InstrItinClass itin,
670 RegisterClass RC, list<Register> DefRegs>:
671 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
672 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> {
675 let isCommutable = 1;
677 let neverHasSideEffects = 1;
680 class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>:
681 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>;
683 class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin,
684 RegisterClass RC, list<Register> DefRegs>:
685 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
686 !strconcat(instr_asm, "\t$$zero, $rs, $rt"),
687 [(op RC:$rs, RC:$rt)], itin> {
693 class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
694 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>;
697 class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC,
698 list<Register> UseRegs>:
699 FR<0x00, func, (outs RC:$rd), (ins),
700 !strconcat(instr_asm, "\t$rd"), [], IIHiLo> {
705 let neverHasSideEffects = 1;
708 class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC,
709 list<Register> DefRegs>:
710 FR<0x00, func, (outs), (ins RC:$rs),
711 !strconcat(instr_asm, "\t$rs"), [], IIHiLo> {
716 let neverHasSideEffects = 1;
719 class EffectiveAddress<bits<6> opc, string instr_asm, RegisterClass RC, Operand Mem> :
720 FMem<opc, (outs RC:$rt), (ins Mem:$addr),
721 instr_asm, [(set RC:$rt, addr:$addr)], IIAlu> {
722 let isCodeGenOnly = 1;
725 // Count Leading Ones/Zeros in Word
726 class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>:
727 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
728 !strconcat(instr_asm, "\t$rd, $rs"),
729 [(set RC:$rd, (ctlz RC:$rs))], IIAlu>,
730 Requires<[HasBitCount, HasStdEnc]> {
735 class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>:
736 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
737 !strconcat(instr_asm, "\t$rd, $rs"),
738 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>,
739 Requires<[HasBitCount, HasStdEnc]> {
744 // Sign Extend in Register.
745 class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt,
747 FR<0x1f, 0x20, (outs RC:$rd), (ins RC:$rt),
748 !strconcat(instr_asm, "\t$rd, $rt"),
749 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary> {
752 let Predicates = [HasSEInReg, HasStdEnc];
756 class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>:
757 FR<0x1f, func, (outs RC:$rd), (ins RC:$rt),
758 !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> {
761 let Predicates = [HasSwap, HasStdEnc];
762 let neverHasSideEffects = 1;
766 class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass>
767 : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd),
768 "rdhwr\t$rt, $rd", [], IIAlu> {
774 class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
775 FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz),
776 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
777 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> {
782 let Predicates = [HasMips32r2, HasStdEnc];
785 class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
786 FR<0x1f, _funct, (outs RC:$rt),
787 (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src),
788 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
789 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))],
795 let Predicates = [HasMips32r2, HasStdEnc];
796 let Constraints = "$src = $rt";
799 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
800 class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC,
802 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
803 !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"),
804 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
806 multiclass Atomic2Ops32<PatFrag Op, string Opstr> {
807 def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>,
808 Requires<[NotN64, HasStdEnc]>;
809 def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>,
810 Requires<[IsN64, HasStdEnc]> {
811 let DecoderNamespace = "Mips64";
815 // Atomic Compare & Swap.
816 class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC,
818 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
819 !strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"),
820 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
822 multiclass AtomicCmpSwap32<PatFrag Op, string Width> {
823 def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>,
824 Requires<[NotN64, HasStdEnc]>;
825 def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>,
826 Requires<[IsN64, HasStdEnc]> {
827 let DecoderNamespace = "Mips64";
831 class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
832 FMem<Opc, (outs RC:$rt), (ins Mem:$addr),
833 !strconcat(opstring, "\t$rt, $addr"), [], IILoad> {
837 class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
838 FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr),
839 !strconcat(opstring, "\t$rt, $addr"), [], IIStore> {
841 let Constraints = "$rt = $dst";
844 //===----------------------------------------------------------------------===//
845 // Pseudo instructions
846 //===----------------------------------------------------------------------===//
849 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
850 def RetRA : PseudoSE<(outs), (ins), "", [(MipsRet)]>;
852 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
853 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
854 "!ADJCALLSTACKDOWN $amt",
855 [(callseq_start timm:$amt)]>;
856 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
857 "!ADJCALLSTACKUP $amt1",
858 [(callseq_end timm:$amt1, timm:$amt2)]>;
861 // When handling PIC code the assembler needs .cpload and .cprestore
862 // directives. If the real instructions corresponding these directives
863 // are used, we have the same behavior, but get also a bunch of warnings
864 // from the assembler.
865 let neverHasSideEffects = 1 in
866 def CPRESTORE : PseudoSE<(outs), (ins i32imm:$loc, CPURegs:$gp),
867 ".cprestore\t$loc", []>;
869 let usesCustomInserter = 1 in {
870 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">;
871 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16, "load_add_16">;
872 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32, "load_add_32">;
873 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8, "load_sub_8">;
874 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16, "load_sub_16">;
875 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32, "load_sub_32">;
876 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8, "load_and_8">;
877 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16, "load_and_16">;
878 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32, "load_and_32">;
879 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8, "load_or_8">;
880 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16, "load_or_16">;
881 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32, "load_or_32">;
882 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8, "load_xor_8">;
883 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16, "load_xor_16">;
884 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32, "load_xor_32">;
885 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8, "load_nand_8">;
886 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16, "load_nand_16">;
887 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32, "load_nand_32">;
889 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8, "swap_8">;
890 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16, "swap_16">;
891 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32, "swap_32">;
893 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8, "8">;
894 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16, "16">;
895 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32, "32">;
898 //===----------------------------------------------------------------------===//
899 // Instruction definition
900 //===----------------------------------------------------------------------===//
902 class LoadImm32< string instr_asm, Operand Od, RegisterClass RC> :
903 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32),
904 !strconcat(instr_asm, "\t$rt, $imm32")> ;
905 def LoadImm32Reg : LoadImm32<"li", shamt,CPURegs>;
907 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterClass RC> :
908 MipsAsmPseudoInst<(outs RC:$rt), (ins MemOpnd:$addr),
909 !strconcat(instr_asm, "\t$rt, $addr")> ;
910 def LoadAddr32Reg : LoadAddress<"la", mem, CPURegs>;
912 class LoadAddressImm<string instr_asm, Operand Od, RegisterClass RC> :
913 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32),
914 !strconcat(instr_asm, "\t$rt, $imm32")> ;
915 def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegs>;
917 //===----------------------------------------------------------------------===//
918 // MipsI Instructions
919 //===----------------------------------------------------------------------===//
921 /// Arithmetic Instructions (ALU Immediate)
922 def ADDiu : ArithLogicI<0x09, "addiu", simm16, immSExt16, CPURegs, add>,
924 def ADDi : ArithLogicI<0x08, "addi", simm16, immSExt16, CPURegs>;
925 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>;
926 def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;
927 def ANDi : ArithLogicI<0x0c, "andi", uimm16, immZExt16, CPURegs, and>;
928 def ORi : ArithLogicI<0x0d, "ori", uimm16, immZExt16, CPURegs, or>;
929 def XORi : ArithLogicI<0x0e, "xori", uimm16, immZExt16, CPURegs, xor>;
930 def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>;
932 /// Arithmetic Instructions (3-Operand, R-Type)
933 def ADDu : ArithLogicR<0x00, 0x21, "addu", IIAlu, CPURegs, 1, add>;
934 def SUBu : ArithLogicR<0x00, 0x23, "subu", IIAlu, CPURegs, 0, sub>;
935 def ADD : ArithLogicR<0x00, 0x20, "add", IIAlu, CPURegs, 1>;
936 def SUB : ArithLogicR<0x00, 0x22, "sub", IIAlu, CPURegs, 0>;
937 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>;
938 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>;
939 def AND : ArithLogicR<0x00, 0x24, "and", IIAlu, CPURegs, 1, and>;
940 def OR : ArithLogicR<0x00, 0x25, "or", IIAlu, CPURegs, 1, or>;
941 def XOR : ArithLogicR<0x00, 0x26, "xor", IIAlu, CPURegs, 1, xor>;
942 def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>;
944 /// Shift Instructions
945 def SLL : shift_rotate_imm32<0x00, 0x00, "sll", shl>;
946 def SRL : shift_rotate_imm32<0x02, 0x00, "srl", srl>;
947 def SRA : shift_rotate_imm32<0x03, 0x00, "sra", sra>;
948 def SLLV : shift_rotate_reg<0x04, 0x00, "sllv", shl, CPURegs>;
949 def SRLV : shift_rotate_reg<0x06, 0x00, "srlv", srl, CPURegs>;
950 def SRAV : shift_rotate_reg<0x07, 0x00, "srav", sra, CPURegs>;
952 // Rotate Instructions
953 let Predicates = [HasMips32r2, HasStdEnc] in {
954 def ROTR : shift_rotate_imm32<0x02, 0x01, "rotr", rotr>;
955 def ROTRV : shift_rotate_reg<0x06, 0x01, "rotrv", rotr, CPURegs>;
958 /// Load and Store Instructions
960 defm LB : LoadM32<0x20, "lb", sextloadi8>;
961 defm LBu : LoadM32<0x24, "lbu", zextloadi8>;
962 defm LH : LoadM32<0x21, "lh", sextloadi16>;
963 defm LHu : LoadM32<0x25, "lhu", zextloadi16>;
964 defm LW : LoadM32<0x23, "lw", load>;
965 defm SB : StoreM32<0x28, "sb", truncstorei8>;
966 defm SH : StoreM32<0x29, "sh", truncstorei16>;
967 defm SW : StoreM32<0x2b, "sw", store>;
969 /// load/store left/right
970 defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>;
971 defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>;
972 defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>;
973 defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>;
975 let hasSideEffects = 1 in
976 def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype",
977 [(MipsSync imm:$stype)], NoItinerary, FrmOther>
982 let Inst{10-6} = stype;
986 /// Load-linked, Store-conditional
987 def LL : LLBase<0x30, "ll", CPURegs, mem>,
988 Requires<[NotN64, HasStdEnc]>;
989 def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>,
990 Requires<[IsN64, HasStdEnc]> {
991 let DecoderNamespace = "Mips64";
994 def SC : SCBase<0x38, "sc", CPURegs, mem>,
995 Requires<[NotN64, HasStdEnc]>;
996 def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>,
997 Requires<[IsN64, HasStdEnc]> {
998 let DecoderNamespace = "Mips64";
1001 /// Jump and Branch Instructions
1002 def J : JumpFJ<0x02, jmptarget, "j", br, bb>,
1003 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
1004 def JR : IndirectBranch<CPURegs>;
1005 def B : UncondBranch<0x04, "b">;
1006 def BEQ : CBranch<0x04, "beq", seteq, CPURegs>;
1007 def BNE : CBranch<0x05, "bne", setne, CPURegs>;
1008 def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>;
1009 def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>;
1010 def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>;
1011 def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>;
1013 let rt = 0, rs = 0, isBranch = 1, isTerminator = 1, isBarrier = 1,
1014 hasDelaySlot = 1, Defs = [RA] in
1015 def BAL_BR: FI<0x1, (outs), (ins brtarget:$imm16), "bal\t$imm16", [], IIBranch>;
1017 def JAL : JumpLink<0x03, "jal">;
1018 def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>;
1019 def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>;
1020 def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>;
1021 def TAILCALL : JumpFJ<0x02, calltarget, "j", MipsTailCall, imm>, IsTailCall;
1022 def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, IsTailCall;
1024 def RET : RetBase<CPURegs>;
1026 /// Multiply and Divide Instructions.
1027 def MULT : Mult32<0x18, "mult", IIImul>;
1028 def MULTu : Mult32<0x19, "multu", IIImul>;
1029 def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>;
1030 def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>;
1032 def MTHI : MoveToLOHI<0x11, "mthi", CPURegs, [HI]>;
1033 def MTLO : MoveToLOHI<0x13, "mtlo", CPURegs, [LO]>;
1034 def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>;
1035 def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>;
1037 /// Sign Ext In Register Instructions.
1038 def SEB : SignExtInReg<0x10, "seb", i8, CPURegs>;
1039 def SEH : SignExtInReg<0x18, "seh", i16, CPURegs>;
1042 def CLZ : CountLeading0<0x20, "clz", CPURegs>;
1043 def CLO : CountLeading1<0x21, "clo", CPURegs>;
1045 /// Word Swap Bytes Within Halfwords
1046 def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>;
1050 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
1052 // FrameIndexes are legalized when they are operands from load/store
1053 // instructions. The same not happens for stack address copies, so an
1054 // add op with mem ComplexPattern is used and the stack address copy
1055 // can be matched. It's similar to Sparc LEA_ADDRi
1056 def LEA_ADDiu : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>;
1059 def MADD : MArithR<0, "madd", MipsMAdd, 1>;
1060 def MADDU : MArithR<1, "maddu", MipsMAddu, 1>;
1061 def MSUB : MArithR<4, "msub", MipsMSub>;
1062 def MSUBU : MArithR<5, "msubu", MipsMSubu>;
1064 // MUL is a assembly macro in the current used ISAs. In recent ISA's
1065 // it is a real instruction.
1066 def MUL : ArithLogicR<0x1c, 0x02, "mul", IIImul, CPURegs, 1, mul>,
1067 Requires<[HasStdEnc]>;
1069 def RDHWR : ReadHardware<CPURegs, HWRegs>;
1071 def EXT : ExtBase<0, "ext", CPURegs>;
1072 def INS : InsBase<4, "ins", CPURegs>;
1074 //===----------------------------------------------------------------------===//
1075 // Instruction aliases
1076 //===----------------------------------------------------------------------===//
1077 def : InstAlias<"move $dst,$src", (ADD CPURegs:$dst,CPURegs:$src,ZERO)>;
1078 def : InstAlias<"bal $offset", (BGEZAL RA,brtarget:$offset)>;
1079 def : InstAlias<"addu $rs,$rt,$imm",
1080 (ADDiu CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
1081 def : InstAlias<"add $rs,$rt,$imm",
1082 (ADDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
1083 def : InstAlias<"and $rs,$rt,$imm",
1084 (ANDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
1085 def : InstAlias<"j $rs", (JR CPURegs:$rs)>;
1086 def : InstAlias<"not $rt,$rs", (NOR CPURegs:$rt,CPURegs:$rs,ZERO)>;
1087 def : InstAlias<"neg $rt,$rs", (SUB CPURegs:$rt,ZERO,CPURegs:$rs)>;
1088 def : InstAlias<"negu $rt,$rs", (SUBu CPURegs:$rt,ZERO,CPURegs:$rs)>;
1089 def : InstAlias<"slt $rs,$rt,$imm",
1090 (SLTi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
1091 def : InstAlias<"xor $rs,$rt,$imm",
1092 (XORi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
1094 //===----------------------------------------------------------------------===//
1095 // Arbitrary patterns that map to one or more instructions
1096 //===----------------------------------------------------------------------===//
1099 def : MipsPat<(i32 immSExt16:$in),
1100 (ADDiu ZERO, imm:$in)>;
1101 def : MipsPat<(i32 immZExt16:$in),
1102 (ORi ZERO, imm:$in)>;
1103 def : MipsPat<(i32 immLow16Zero:$in),
1104 (LUi (HI16 imm:$in))>;
1106 // Arbitrary immediates
1107 def : MipsPat<(i32 imm:$imm),
1108 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1110 // Carry MipsPatterns
1111 def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs),
1112 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
1113 def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs),
1114 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
1115 def : MipsPat<(addc CPURegs:$src, immSExt16:$imm),
1116 (ADDiu CPURegs:$src, imm:$imm)>;
1119 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1120 (JAL tglobaladdr:$dst)>;
1121 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1122 (JAL texternalsym:$dst)>;
1123 //def : MipsPat<(MipsJmpLink CPURegs:$dst),
1124 // (JALR CPURegs:$dst)>;
1127 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1128 (TAILCALL tglobaladdr:$dst)>;
1129 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1130 (TAILCALL texternalsym:$dst)>;
1132 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1133 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1134 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1135 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1136 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1137 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1139 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1140 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1141 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1142 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1143 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1144 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1146 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
1147 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
1148 def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
1149 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
1150 def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
1151 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
1152 def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
1153 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
1154 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)),
1155 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
1158 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
1159 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
1160 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
1161 (ADDiu CPURegs:$gp, tconstpool:$in)>;
1164 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1165 MipsPat<(MipsWrapper RC:$gp, node:$in),
1166 (ADDiuOp RC:$gp, node:$in)>;
1168 def : WrapperPat<tglobaladdr, ADDiu, CPURegs>;
1169 def : WrapperPat<tconstpool, ADDiu, CPURegs>;
1170 def : WrapperPat<texternalsym, ADDiu, CPURegs>;
1171 def : WrapperPat<tblockaddress, ADDiu, CPURegs>;
1172 def : WrapperPat<tjumptable, ADDiu, CPURegs>;
1173 def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>;
1175 // Mips does not have "not", so we expand our way
1176 def : MipsPat<(not CPURegs:$in),
1177 (NOR CPURegs:$in, ZERO)>;
1180 let Predicates = [NotN64, HasStdEnc] in {
1181 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1182 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1183 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1185 let Predicates = [IsN64, HasStdEnc] in {
1186 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
1187 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
1188 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>;
1192 let Predicates = [NotN64, HasStdEnc] in {
1193 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1195 let Predicates = [IsN64, HasStdEnc] in {
1196 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
1200 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1201 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1202 Instruction SLTiuOp, Register ZEROReg> {
1203 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1204 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1205 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1206 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1208 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1209 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1210 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1211 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1212 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1213 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1214 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1215 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1217 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1218 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1219 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1220 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1222 def : MipsPat<(brcond RC:$cond, bb:$dst),
1223 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1226 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1229 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1230 Instruction SLTuOp, Register ZEROReg> {
1231 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1232 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1233 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1234 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1237 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1238 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1239 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1240 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1241 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1244 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1245 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1246 (SLTOp RC:$rhs, RC:$lhs)>;
1247 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1248 (SLTuOp RC:$rhs, RC:$lhs)>;
1251 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1252 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1253 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1254 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1255 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1258 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1259 Instruction SLTiuOp> {
1260 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1261 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1262 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1263 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1266 defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
1267 defm : SetlePats<CPURegs, SLT, SLTu>;
1268 defm : SetgtPats<CPURegs, SLT, SLTu>;
1269 defm : SetgePats<CPURegs, SLT, SLTu>;
1270 defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
1273 def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
1275 //===----------------------------------------------------------------------===//
1276 // Floating Point Support
1277 //===----------------------------------------------------------------------===//
1279 include "MipsInstrFPU.td"
1280 include "Mips64InstrInfo.td"
1281 include "MipsCondMov.td"
1286 include "Mips16InstrFormats.td"
1287 include "Mips16InstrInfo.td"
1290 include "MipsDSPInstrFormats.td"
1291 include "MipsDSPInstrInfo.td"