1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasMips2 : Predicate<"Subtarget.hasMips2()">,
150 AssemblerPredicate<"FeatureMips2">;
151 def HasMips3_32 : Predicate<"Subtarget.hasMips3_32()">,
152 AssemblerPredicate<"FeatureMips3_32">;
153 def HasMips3_32r2 : Predicate<"Subtarget.hasMips3_32r2()">,
154 AssemblerPredicate<"FeatureMips3_32r2">;
155 def HasMips3 : Predicate<"Subtarget.hasMips3()">,
156 AssemblerPredicate<"FeatureMips3">;
157 def HasMips4_32 : Predicate<"Subtarget.hasMips4_32()">,
158 AssemblerPredicate<"FeatureMips4_32">;
159 def HasMips4_32r2 : Predicate<"Subtarget.hasMips4_32r2()">,
160 AssemblerPredicate<"FeatureMips4_32r2">;
161 def HasMips5_32r2 : Predicate<"Subtarget.hasMips5_32r2()">,
162 AssemblerPredicate<"FeatureMips5_32r2">;
163 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
164 AssemblerPredicate<"FeatureMips32">;
165 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
166 AssemblerPredicate<"FeatureMips32r2">;
167 def HasMips32r6 : Predicate<"Subtarget.hasMips32r6()">,
168 AssemblerPredicate<"FeatureMips32r6">;
169 def NotMips32r6 : Predicate<"!Subtarget.hasMips32r6()">,
170 AssemblerPredicate<"!FeatureMips32r6">;
171 def IsGP64bit : Predicate<"Subtarget.isGP64bit()">,
172 AssemblerPredicate<"FeatureGP64Bit">;
173 def IsGP32bit : Predicate<"!Subtarget.isGP64bit()">,
174 AssemblerPredicate<"!FeatureGP64Bit">;
175 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
176 AssemblerPredicate<"FeatureMips64">;
177 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
178 AssemblerPredicate<"FeatureMips64r2">;
179 def HasMips64r6 : Predicate<"Subtarget.hasMips64r6()">,
180 AssemblerPredicate<"FeatureMips64r6">;
181 def NotMips64r6 : Predicate<"!Subtarget.hasMips64r6()">,
182 AssemblerPredicate<"!FeatureMips64r6">;
183 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
184 AssemblerPredicate<"FeatureN64">;
185 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
186 AssemblerPredicate<"FeatureMips16">;
187 def HasCnMips : Predicate<"Subtarget.hasCnMips()">,
188 AssemblerPredicate<"FeatureCnMips">;
189 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
190 AssemblerPredicate<"FeatureMips32">;
191 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
192 AssemblerPredicate<"FeatureMips32">;
193 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
194 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
195 AssemblerPredicate<"!FeatureMips16">;
196 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
197 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
198 AssemblerPredicate<"FeatureMicroMips">;
199 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
200 AssemblerPredicate<"!FeatureMicroMips">;
201 def IsLE : Predicate<"Subtarget.isLittle()">;
202 def IsBE : Predicate<"!Subtarget.isLittle()">;
203 def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
205 //===----------------------------------------------------------------------===//
206 // Mips GPR size adjectives.
207 // They are mutually exclusive.
208 //===----------------------------------------------------------------------===//
210 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
211 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
213 //===----------------------------------------------------------------------===//
214 // Mips ISA/ASE membership and instruction group membership adjectives.
215 // They are mutually exclusive.
216 //===----------------------------------------------------------------------===//
218 // FIXME: I'd prefer to use additive predicates to build the instruction sets
219 // but we are short on assembler feature bits at the moment. Using a
220 // subtractive predicate will hopefully keep us under the 32 predicate
221 // limit long enough to develop an alternative way to handle P1||P2
223 class ISA_MIPS1_NOT_32R6_64R6 {
224 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
226 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
227 class ISA_MIPS2_NOT_32R6_64R6 {
228 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
230 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
231 class ISA_MIPS3_NOT_32R6_64R6 {
232 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];
234 class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
235 class ISA_MIPS32_NOT_32R6_64R6 {
236 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
238 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
239 class ISA_MIPS32R2_NOT_32R6_64R6 {
240 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
242 class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
243 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
244 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
245 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
247 // The portions of MIPS-III that were also added to MIPS32
248 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
250 // The portions of MIPS-III that were also added to MIPS32
251 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
253 // The portions of MIPS-IV that were also added to MIPS32 but were removed in
254 // MIPS32r6 and MIPS64r6.
255 class INSN_MIPS4_32_NOT_32R6_64R6 {
256 list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6];
259 // The portions of MIPS-IV that were also added to MIPS32R2
260 class INSN_MIPS4_32R2 { list<Predicate> InsnPredicates = [HasMips4_32r2]; }
262 // The portions of MIPS-V that were also added to MIPS32R2
263 class INSN_MIPS5_32R2 { list<Predicate> InsnPredicates = [HasMips5_32r2]; }
265 //===----------------------------------------------------------------------===//
267 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
268 let EncodingPredicates = [HasStdEnc];
271 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
272 InstAlias<Asm, Result, Emit>, PredicateControl;
275 bit isCommutable = 1;
292 bit isTerminator = 1;
295 bit hasExtraSrcRegAllocReq = 1;
296 bit isCodeGenOnly = 1;
299 class IsAsCheapAsAMove {
300 bit isAsCheapAsAMove = 1;
303 class NeverHasSideEffects {
304 bit neverHasSideEffects = 1;
307 //===----------------------------------------------------------------------===//
308 // Instruction format superclass
309 //===----------------------------------------------------------------------===//
311 include "MipsInstrFormats.td"
313 //===----------------------------------------------------------------------===//
314 // Mips Operand, Complex Patterns and Transformations Definitions.
315 //===----------------------------------------------------------------------===//
317 def MipsJumpTargetAsmOperand : AsmOperandClass {
318 let Name = "JumpTarget";
319 let ParserMethod = "ParseJumpTarget";
320 let PredicateMethod = "isImm";
321 let RenderMethod = "addImmOperands";
324 // Instruction operand types
325 def jmptarget : Operand<OtherVT> {
326 let EncoderMethod = "getJumpTargetOpValue";
327 let ParserMatchClass = MipsJumpTargetAsmOperand;
329 def brtarget : Operand<OtherVT> {
330 let EncoderMethod = "getBranchTargetOpValue";
331 let OperandType = "OPERAND_PCREL";
332 let DecoderMethod = "DecodeBranchTarget";
333 let ParserMatchClass = MipsJumpTargetAsmOperand;
335 def calltarget : Operand<iPTR> {
336 let EncoderMethod = "getJumpTargetOpValue";
337 let ParserMatchClass = MipsJumpTargetAsmOperand;
340 def simm10 : Operand<i32>;
342 def simm16 : Operand<i32> {
343 let DecoderMethod= "DecodeSimm16";
346 def simm19_lsl2 : Operand<i32> {
347 let EncoderMethod = "getSimm19Lsl2Encoding";
348 let DecoderMethod = "DecodeSimm19Lsl2";
349 let ParserMatchClass = MipsJumpTargetAsmOperand;
352 def simm18_lsl3 : Operand<i32> {
353 let EncoderMethod = "getSimm18Lsl3Encoding";
354 let DecoderMethod = "DecodeSimm18Lsl3";
357 def simm20 : Operand<i32> {
360 def uimm20 : Operand<i32> {
363 def uimm10 : Operand<i32> {
366 def simm16_64 : Operand<i64> {
367 let DecoderMethod = "DecodeSimm16";
371 def uimmz : Operand<i32> {
372 let PrintMethod = "printUnsignedImm";
376 def uimm2 : Operand<i32> {
377 let PrintMethod = "printUnsignedImm";
380 def uimm3 : Operand<i32> {
381 let PrintMethod = "printUnsignedImm";
384 def uimm5 : Operand<i32> {
385 let PrintMethod = "printUnsignedImm";
388 def uimm6 : Operand<i32> {
389 let PrintMethod = "printUnsignedImm";
392 def uimm16 : Operand<i32> {
393 let PrintMethod = "printUnsignedImm";
396 def pcrel16 : Operand<i32> {
399 def MipsMemAsmOperand : AsmOperandClass {
401 let ParserMethod = "parseMemOperand";
404 def MipsInvertedImmoperand : AsmOperandClass {
406 let RenderMethod = "addImmOperands";
407 let ParserMethod = "parseInvNum";
410 def InvertedImOperand : Operand<i32> {
411 let ParserMatchClass = MipsInvertedImmoperand;
414 def InvertedImOperand64 : Operand<i64> {
415 let ParserMatchClass = MipsInvertedImmoperand;
418 class mem_generic : Operand<iPTR> {
419 let PrintMethod = "printMemOperand";
420 let MIOperandInfo = (ops ptr_rc, simm16);
421 let EncoderMethod = "getMemEncoding";
422 let ParserMatchClass = MipsMemAsmOperand;
423 let OperandType = "OPERAND_MEMORY";
427 def mem : mem_generic;
429 // MSA specific address operand
430 def mem_msa : mem_generic {
431 let MIOperandInfo = (ops ptr_rc, simm10);
432 let EncoderMethod = "getMSAMemEncoding";
435 def mem_ea : Operand<iPTR> {
436 let PrintMethod = "printMemOperandEA";
437 let MIOperandInfo = (ops ptr_rc, simm16);
438 let EncoderMethod = "getMemEncoding";
439 let OperandType = "OPERAND_MEMORY";
442 def PtrRC : Operand<iPTR> {
443 let MIOperandInfo = (ops ptr_rc);
444 let DecoderMethod = "DecodePtrRegisterClass";
445 let ParserMatchClass = GPR32AsmOperand;
448 // size operand of ext instruction
449 def size_ext : Operand<i32> {
450 let EncoderMethod = "getSizeExtEncoding";
451 let DecoderMethod = "DecodeExtSize";
454 // size operand of ins instruction
455 def size_ins : Operand<i32> {
456 let EncoderMethod = "getSizeInsEncoding";
457 let DecoderMethod = "DecodeInsSize";
460 // Transformation Function - get the lower 16 bits.
461 def LO16 : SDNodeXForm<imm, [{
462 return getImm(N, N->getZExtValue() & 0xFFFF);
465 // Transformation Function - get the higher 16 bits.
466 def HI16 : SDNodeXForm<imm, [{
467 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
471 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
473 // Node immediate is zero (e.g. insve.d)
474 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
476 // Node immediate fits as 16-bit sign extended on target immediate.
478 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
480 // Node immediate fits as 16-bit sign extended on target immediate.
482 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
484 // Node immediate fits as 15-bit sign extended on target immediate.
486 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
488 // Node immediate fits as 16-bit zero extended on target immediate.
489 // The LO16 param means that only the lower 16 bits of the node
490 // immediate are caught.
492 def immZExt16 : PatLeaf<(imm), [{
493 if (N->getValueType(0) == MVT::i32)
494 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
496 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
499 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
500 def immLow16Zero : PatLeaf<(imm), [{
501 int64_t Val = N->getSExtValue();
502 return isInt<32>(Val) && !(Val & 0xffff);
505 // shamt field must fit in 5 bits.
506 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
508 // True if (N + 1) fits in 16-bit field.
509 def immSExt16Plus1 : PatLeaf<(imm), [{
510 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
513 // Mips Address Mode! SDNode frameindex could possibily be a match
514 // since load and store instructions from stack used it.
516 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
519 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
522 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
525 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
527 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
529 //===----------------------------------------------------------------------===//
530 // Instructions specific format
531 //===----------------------------------------------------------------------===//
533 // Arithmetic and logical instructions with 3 register operands.
534 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
535 InstrItinClass Itin = NoItinerary,
536 SDPatternOperator OpNode = null_frag>:
537 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
538 !strconcat(opstr, "\t$rd, $rs, $rt"),
539 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
540 let isCommutable = isComm;
541 let isReMaterializable = 1;
542 let TwoOperandAliasConstraint = "$rd = $rs";
545 // Arithmetic and logical instructions with 2 register operands.
546 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
547 InstrItinClass Itin = NoItinerary,
548 SDPatternOperator imm_type = null_frag,
549 SDPatternOperator OpNode = null_frag> :
550 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
551 !strconcat(opstr, "\t$rt, $rs, $imm16"),
552 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
554 let isReMaterializable = 1;
555 let TwoOperandAliasConstraint = "$rs = $rt";
558 // Arithmetic Multiply ADD/SUB
559 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
560 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
561 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
562 let Defs = [HI0, LO0];
563 let Uses = [HI0, LO0];
564 let isCommutable = isComm;
568 class LogicNOR<string opstr, RegisterOperand RO>:
569 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
570 !strconcat(opstr, "\t$rd, $rs, $rt"),
571 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
572 let isCommutable = 1;
576 class shift_rotate_imm<string opstr, Operand ImmOpnd,
577 RegisterOperand RO, InstrItinClass itin,
578 SDPatternOperator OpNode = null_frag,
579 SDPatternOperator PF = null_frag> :
580 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
581 !strconcat(opstr, "\t$rd, $rt, $shamt"),
582 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
583 let TwoOperandAliasConstraint = "$rt = $rd";
586 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
587 SDPatternOperator OpNode = null_frag>:
588 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
589 !strconcat(opstr, "\t$rd, $rt, $rs"),
590 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
593 // Load Upper Imediate
594 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
595 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
596 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
597 let neverHasSideEffects = 1;
598 let isReMaterializable = 1;
602 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
603 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
604 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
605 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
606 let DecoderMethod = "DecodeMem";
607 let canFoldAsLoad = 1;
611 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
612 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
613 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
614 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
615 let DecoderMethod = "DecodeMem";
619 // Load/Store Left/Right
620 let canFoldAsLoad = 1 in
621 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
622 InstrItinClass Itin> :
623 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
624 !strconcat(opstr, "\t$rt, $addr"),
625 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
626 let DecoderMethod = "DecodeMem";
627 string Constraints = "$src = $rt";
630 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
631 InstrItinClass Itin> :
632 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
633 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
634 let DecoderMethod = "DecodeMem";
637 // Conditional Branch
638 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
639 RegisterOperand RO> :
640 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
641 !strconcat(opstr, "\t$rs, $rt, $offset"),
642 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
645 let isTerminator = 1;
646 let hasDelaySlot = 1;
650 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
651 RegisterOperand RO> :
652 InstSE<(outs), (ins RO:$rs, opnd:$offset),
653 !strconcat(opstr, "\t$rs, $offset"),
654 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
657 let isTerminator = 1;
658 let hasDelaySlot = 1;
663 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
664 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
665 !strconcat(opstr, "\t$rd, $rs, $rt"),
666 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
667 II_SLT_SLTU, FrmR, opstr>;
669 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
671 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
672 !strconcat(opstr, "\t$rt, $rs, $imm16"),
673 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
674 II_SLTI_SLTIU, FrmI, opstr>;
677 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
678 SDPatternOperator targetoperator, string bopstr> :
679 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
680 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
683 let hasDelaySlot = 1;
684 let DecoderMethod = "DecodeJumpTarget";
688 // Unconditional branch
689 class UncondBranch<Instruction BEQInst> :
690 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
691 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
693 let isTerminator = 1;
695 let hasDelaySlot = 1;
696 let AdditionalPredicates = [RelocPIC];
700 // Base class for indirect branch and return instruction classes.
701 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
702 class JumpFR<string opstr, RegisterOperand RO,
703 SDPatternOperator operator = null_frag>:
704 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
708 class IndirectBranch<string opstr, RegisterOperand RO> :
709 JumpFR<opstr, RO, brind> {
711 let isIndirectBranch = 1;
714 // Return instruction
715 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
717 let isCodeGenOnly = 1;
719 let hasExtraSrcRegAllocReq = 1;
722 // Jump and Link (Call)
723 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
724 class JumpLink<string opstr, DAGOperand opnd> :
725 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
726 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
727 let DecoderMethod = "DecodeJumpTarget";
730 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
731 Register RetReg, RegisterOperand ResRO = RO>:
732 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
733 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
735 class JumpLinkReg<string opstr, RegisterOperand RO>:
736 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
739 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
740 InstSE<(outs), (ins RO:$rs, opnd:$offset),
741 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
745 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
746 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
747 class TailCall<Instruction JumpInst> :
748 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
749 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
751 class TailCallReg<RegisterOperand RO, Instruction JRInst,
752 RegisterOperand ResRO = RO> :
753 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
754 PseudoInstExpansion<(JRInst ResRO:$rs)>;
757 class BAL_BR_Pseudo<Instruction RealInst> :
758 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
759 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
761 let isTerminator = 1;
763 let hasDelaySlot = 1;
768 class SYS_FT<string opstr> :
769 InstSE<(outs), (ins uimm20:$code_),
770 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
772 class BRK_FT<string opstr> :
773 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
774 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
778 class ER_FT<string opstr> :
779 InstSE<(outs), (ins),
780 opstr, [], NoItinerary, FrmOther, opstr>;
783 class DEI_FT<string opstr, RegisterOperand RO> :
784 InstSE<(outs RO:$rt), (ins),
785 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
788 class WAIT_FT<string opstr> :
789 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
792 let hasSideEffects = 1 in
793 class SYNC_FT<string opstr> :
794 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
795 NoItinerary, FrmOther, opstr>;
797 let hasSideEffects = 1 in
798 class TEQ_FT<string opstr, RegisterOperand RO> :
799 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
800 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
803 class TEQI_FT<string opstr, RegisterOperand RO> :
804 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
805 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
807 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
808 list<Register> DefRegs> :
809 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
811 let isCommutable = 1;
813 let neverHasSideEffects = 1;
816 // Pseudo multiply/divide instruction with explicit accumulator register
818 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
819 SDPatternOperator OpNode, InstrItinClass Itin,
820 bit IsComm = 1, bit HasSideEffects = 0,
821 bit UsesCustomInserter = 0> :
822 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
823 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
824 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
825 let isCommutable = IsComm;
826 let hasSideEffects = HasSideEffects;
827 let usesCustomInserter = UsesCustomInserter;
830 // Pseudo multiply add/sub instruction with explicit accumulator register
832 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
834 : PseudoSE<(outs ACC64:$ac),
835 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
837 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
839 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
840 string Constraints = "$acin = $ac";
843 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
844 list<Register> DefRegs> :
845 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
846 [], itin, FrmR, opstr> {
851 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
852 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
853 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
855 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
856 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
859 let neverHasSideEffects = 1;
862 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
863 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
864 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
867 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
868 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
871 let neverHasSideEffects = 1;
874 class EffectiveAddress<string opstr, RegisterOperand RO> :
875 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
876 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
877 !strconcat(opstr, "_lea")> {
878 let isCodeGenOnly = 1;
879 let DecoderMethod = "DecodeMem";
882 // Count Leading Ones/Zeros in Word
883 class CountLeading0<string opstr, RegisterOperand RO>:
884 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
885 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
887 class CountLeading1<string opstr, RegisterOperand RO>:
888 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
889 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
891 // Sign Extend in Register.
892 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
893 InstrItinClass itin> :
894 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
895 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
898 class SubwordSwap<string opstr, RegisterOperand RO>:
899 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
900 NoItinerary, FrmR, opstr> {
901 let neverHasSideEffects = 1;
905 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
906 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
910 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
911 SDPatternOperator Op = null_frag>:
912 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
913 !strconcat(opstr, " $rt, $rs, $pos, $size"),
914 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
915 FrmR, opstr>, ISA_MIPS32R2;
917 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
918 SDPatternOperator Op = null_frag>:
919 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
920 !strconcat(opstr, " $rt, $rs, $pos, $size"),
921 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
922 NoItinerary, FrmR, opstr>, ISA_MIPS32R2 {
923 let Constraints = "$src = $rt";
926 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
927 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
928 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
929 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
931 // Atomic Compare & Swap.
932 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
933 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
934 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
936 class LLBase<string opstr, RegisterOperand RO> :
937 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
938 [], NoItinerary, FrmI> {
939 let DecoderMethod = "DecodeMem";
943 class SCBase<string opstr, RegisterOperand RO> :
944 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
945 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
946 let DecoderMethod = "DecodeMem";
948 let Constraints = "$rt = $dst";
951 class MFC3OP<string asmstr, RegisterOperand RO> :
952 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
953 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
955 class TrapBase<Instruction RealInst>
956 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
957 PseudoInstExpansion<(RealInst 0, 0)> {
959 let isTerminator = 1;
960 let isCodeGenOnly = 1;
963 //===----------------------------------------------------------------------===//
964 // Pseudo instructions
965 //===----------------------------------------------------------------------===//
968 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
969 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
971 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
972 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
973 [(callseq_start timm:$amt)]>;
974 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
975 [(callseq_end timm:$amt1, timm:$amt2)]>;
978 let usesCustomInserter = 1 in {
979 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
980 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
981 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
982 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
983 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
984 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
985 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
986 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
987 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
988 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
989 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
990 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
991 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
992 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
993 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
994 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
995 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
996 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
998 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
999 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
1000 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
1002 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
1003 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
1004 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
1007 /// Pseudo instructions for loading and storing accumulator registers.
1008 let isPseudo = 1, isCodeGenOnly = 1 in {
1009 def LOAD_ACC64 : Load<"", ACC64>;
1010 def STORE_ACC64 : Store<"", ACC64>;
1013 // We need these two pseudo instructions to avoid offset calculation for long
1014 // branches. See the comment in file MipsLongBranch.cpp for detailed
1017 // Expands to: lui $dst, %hi($tgt - $baltgt)
1018 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
1019 (ins brtarget:$tgt, brtarget:$baltgt), []>;
1021 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
1022 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
1023 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
1025 //===----------------------------------------------------------------------===//
1026 // Instruction definition
1027 //===----------------------------------------------------------------------===//
1028 //===----------------------------------------------------------------------===//
1029 // MipsI Instructions
1030 //===----------------------------------------------------------------------===//
1032 /// Arithmetic Instructions (ALU Immediate)
1033 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
1035 ADDI_FM<0x9>, IsAsCheapAsAMove;
1036 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
1037 ISA_MIPS1_NOT_32R6_64R6;
1038 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1040 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1042 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
1045 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
1048 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
1051 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
1053 /// Arithmetic Instructions (3-Operand, R-Type)
1054 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
1056 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1058 let Defs = [HI0, LO0] in
1059 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1060 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
1061 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1062 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1063 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1064 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1065 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1067 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1069 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1071 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1073 /// Shift Instructions
1074 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1075 immZExt5>, SRA_FM<0, 0>;
1076 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1077 immZExt5>, SRA_FM<2, 0>;
1078 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1079 immZExt5>, SRA_FM<3, 0>;
1080 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1082 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1084 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1087 // Rotate Instructions
1088 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1090 SRA_FM<2, 1>, ISA_MIPS32R2;
1091 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1092 SRLV_FM<6, 1>, ISA_MIPS32R2;
1094 /// Load and Store Instructions
1096 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1097 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1099 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1101 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1102 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1104 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1105 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1106 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1108 /// load/store left/right
1109 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1110 AdditionalPredicates = [NotInMicroMips] in {
1111 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
1112 ISA_MIPS1_NOT_32R6_64R6;
1113 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
1114 ISA_MIPS1_NOT_32R6_64R6;
1115 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
1116 ISA_MIPS1_NOT_32R6_64R6;
1117 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
1118 ISA_MIPS1_NOT_32R6_64R6;
1121 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
1122 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
1123 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
1124 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
1125 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
1126 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
1127 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
1129 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
1130 ISA_MIPS2_NOT_32R6_64R6;
1131 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
1132 ISA_MIPS2_NOT_32R6_64R6;
1133 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
1134 ISA_MIPS2_NOT_32R6_64R6;
1135 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
1136 ISA_MIPS2_NOT_32R6_64R6;
1137 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
1138 ISA_MIPS2_NOT_32R6_64R6;
1139 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
1140 ISA_MIPS2_NOT_32R6_64R6;
1142 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1143 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1144 def TRAP : TrapBase<BREAK>;
1146 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
1147 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
1149 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
1150 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
1152 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1153 AdditionalPredicates = [NotInMicroMips] in {
1154 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1156 /// Load-linked, Store-conditional
1157 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2;
1158 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2;
1161 /// Jump and Branch Instructions
1162 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1163 AdditionalRequires<[RelocStatic]>, IsBranch;
1164 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1165 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1166 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1167 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1169 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1171 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1173 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1175 def B : UncondBranch<BEQ>;
1177 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1178 let AdditionalPredicates = [NotInMicroMips] in {
1179 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1180 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1183 // FIXME: JALX really requires either MIPS16 or microMIPS in addition to MIPS32.
1184 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>, ISA_MIPS32_NOT_32R6_64R6;
1185 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
1186 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
1187 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1188 def TAILCALL : TailCall<J>;
1189 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1191 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1193 // Exception handling related node and instructions.
1194 // The conversion sequence is:
1195 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1196 // MIPSeh_return -> (stack change + indirect branch)
1198 // MIPSeh_return takes the place of regular return instruction
1199 // but takes two arguments (V1, V0) which are used for storing
1200 // the offset and return address respectively.
1201 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1203 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1204 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1206 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1207 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1208 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1209 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1211 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1214 /// Multiply and Divide Instructions.
1215 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1216 MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
1217 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1218 MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
1219 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1220 MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
1221 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1222 MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
1224 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
1225 ISA_MIPS1_NOT_32R6_64R6;
1226 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
1227 ISA_MIPS1_NOT_32R6_64R6;
1228 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1229 AdditionalPredicates = [NotInMicroMips] in {
1230 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
1231 ISA_MIPS1_NOT_32R6_64R6;
1232 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
1233 ISA_MIPS1_NOT_32R6_64R6;
1236 /// Sign Ext In Register Instructions.
1237 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
1238 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
1239 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
1240 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
1243 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>, ISA_MIPS32;
1244 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>, ISA_MIPS32;
1246 /// Word Swap Bytes Within Halfwords
1247 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2;
1250 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1252 // FrameIndexes are legalized when they are operands from load/store
1253 // instructions. The same not happens for stack address copies, so an
1254 // add op with mem ComplexPattern is used and the stack address copy
1255 // can be matched. It's similar to Sparc LEA_ADDRi
1256 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1259 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
1260 ISA_MIPS32_NOT_32R6_64R6;
1261 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
1262 ISA_MIPS32_NOT_32R6_64R6;
1263 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
1264 ISA_MIPS32_NOT_32R6_64R6;
1265 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
1266 ISA_MIPS32_NOT_32R6_64R6;
1268 let AdditionalPredicates = [NotDSP] in {
1269 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
1270 ISA_MIPS1_NOT_32R6_64R6;
1271 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
1272 ISA_MIPS1_NOT_32R6_64R6;
1273 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6;
1274 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6;
1275 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6;
1276 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
1277 ISA_MIPS32_NOT_32R6_64R6;
1278 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
1279 ISA_MIPS32_NOT_32R6_64R6;
1280 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
1281 ISA_MIPS32_NOT_32R6_64R6;
1282 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
1283 ISA_MIPS32_NOT_32R6_64R6;
1286 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1287 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1288 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1289 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1291 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1293 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1294 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1296 /// Move Control Registers From/To CPU Registers
1297 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
1298 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
1299 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1300 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1302 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1304 def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
1305 def EHB : Barrier<"ehb">, BARRIER_FM<3>;
1306 def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1308 // JR_HB and JALR_HB are defined here using the new style naming
1309 // scheme because some of this code is shared with Mips32r6InstrInfo.td
1310 // and because of that it doesn't follow the naming convention of the
1311 // rest of the file. To avoid a mixture of old vs new style, the new
1312 // style was chosen.
1313 class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1314 dag OutOperandList = (outs);
1315 dag InOperandList = (ins GPROpnd:$rs);
1316 string AsmString = !strconcat(instr_asm, "\t$rs");
1317 list<dag> Pattern = [];
1320 class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1321 dag OutOperandList = (outs GPROpnd:$rd);
1322 dag InOperandList = (ins GPROpnd:$rs);
1323 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
1324 list<dag> Pattern = [];
1327 class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1328 JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
1330 let isIndirectBranch=1;
1336 class JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1337 JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> {
1338 let isIndirectBranch=1;
1342 class JR_HB_ENC : JR_HB_FM<8>;
1343 class JALR_HB_ENC : JALR_HB_FM<9>;
1345 def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
1346 def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
1348 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1350 def TLBP : TLB<"tlbp">, COP0_TLB_FM<0x08>;
1351 def TLBR : TLB<"tlbr">, COP0_TLB_FM<0x01>;
1352 def TLBWI : TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1353 def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1355 //===----------------------------------------------------------------------===//
1356 // Instruction aliases
1357 //===----------------------------------------------------------------------===//
1358 def : MipsInstAlias<"move $dst, $src",
1359 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1361 let AdditionalPredicates = [NotInMicroMips];
1363 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1364 def : MipsInstAlias<"addu $rs, $rt, $imm",
1365 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1366 def : MipsInstAlias<"add $rs, $rt, $imm",
1367 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1368 def : MipsInstAlias<"and $rs, $rt, $imm",
1369 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1370 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1371 let Predicates = [NotInMicroMips] in {
1372 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1374 def : MipsInstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1375 def : MipsInstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1376 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
1377 def : MipsInstAlias<"not $rt, $rs",
1378 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1379 def : MipsInstAlias<"neg $rt, $rs",
1380 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1381 def : MipsInstAlias<"negu $rt",
1382 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1383 def : MipsInstAlias<"negu $rt, $rs",
1384 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1385 def : MipsInstAlias<"slt $rs, $rt, $imm",
1386 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1387 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1388 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1389 def : MipsInstAlias<"xor $rs, $rt, $imm",
1390 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1391 def : MipsInstAlias<"or $rs, $rt, $imm",
1392 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1393 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1394 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1395 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1396 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1397 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1398 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1399 def : MipsInstAlias<"bnez $rs,$offset",
1400 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1401 def : MipsInstAlias<"beqz $rs,$offset",
1402 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1403 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1405 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1406 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1407 def : MipsInstAlias<"ei", (EI ZERO), 1>;
1408 def : MipsInstAlias<"di", (DI ZERO), 1>;
1410 def : MipsInstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1411 def : MipsInstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1412 def : MipsInstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1414 def : MipsInstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1415 def : MipsInstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1417 def : MipsInstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1418 def : MipsInstAlias<"sll $rd, $rt, $rs",
1419 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1420 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1421 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1422 InvertedImOperand:$imm), 0>;
1423 def : MipsInstAlias<"sub $rs, $imm",
1424 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1426 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1427 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1428 InvertedImOperand:$imm), 0>;
1429 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1430 InvertedImOperand:$imm), 0>;
1431 def : MipsInstAlias<"sra $rd, $rt, $rs",
1432 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1433 def : MipsInstAlias<"srl $rd, $rt, $rs",
1434 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1435 //===----------------------------------------------------------------------===//
1436 // Assembler Pseudo Instructions
1437 //===----------------------------------------------------------------------===//
1439 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1440 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1441 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1442 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1444 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1445 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1446 !strconcat(instr_asm, "\t$rt, $addr")> ;
1447 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1449 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1450 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1451 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1452 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1454 //===----------------------------------------------------------------------===//
1455 // Arbitrary patterns that map to one or more instructions
1456 //===----------------------------------------------------------------------===//
1458 // Load/store pattern templates.
1459 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1460 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1462 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1463 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1466 def : MipsPat<(i32 immSExt16:$in),
1467 (ADDiu ZERO, imm:$in)>;
1468 def : MipsPat<(i32 immZExt16:$in),
1469 (ORi ZERO, imm:$in)>;
1470 def : MipsPat<(i32 immLow16Zero:$in),
1471 (LUi (HI16 imm:$in))>;
1473 // Arbitrary immediates
1474 def : MipsPat<(i32 imm:$imm),
1475 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1477 // Carry MipsPatterns
1478 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1479 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1480 let AdditionalPredicates = [NotDSP] in {
1481 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1482 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1483 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1484 (ADDiu GPR32:$src, imm:$imm)>;
1488 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1489 (JAL tglobaladdr:$dst)>;
1490 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1491 (JAL texternalsym:$dst)>;
1492 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1493 // (JALR GPR32:$dst)>;
1496 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1497 (TAILCALL tglobaladdr:$dst)>;
1498 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1499 (TAILCALL texternalsym:$dst)>;
1501 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1502 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1503 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1504 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1505 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1506 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1508 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1509 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1510 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1511 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1512 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1513 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1515 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1516 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1517 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1518 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1519 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1520 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1521 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1522 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1523 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1524 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1527 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1528 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1529 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1530 (ADDiu GPR32:$gp, tconstpool:$in)>;
1533 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1534 MipsPat<(MipsWrapper RC:$gp, node:$in),
1535 (ADDiuOp RC:$gp, node:$in)>;
1537 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1538 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1539 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1540 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1541 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1542 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1544 // Mips does not have "not", so we expand our way
1545 def : MipsPat<(not GPR32:$in),
1546 (NOR GPR32Opnd:$in, ZERO)>;
1549 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1550 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1551 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1554 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1557 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1558 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1559 Instruction SLTiuOp, Register ZEROReg> {
1560 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1561 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1562 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1563 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1565 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1566 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1567 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1568 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1569 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1570 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1571 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1572 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1573 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1574 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1575 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1576 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1578 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1579 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1580 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1581 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1583 def : MipsPat<(brcond RC:$cond, bb:$dst),
1584 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1587 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1589 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1590 (BLEZ i32:$lhs, bb:$dst)>;
1591 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1592 (BGEZ i32:$lhs, bb:$dst)>;
1595 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1596 Instruction SLTuOp, Register ZEROReg> {
1597 def : MipsPat<(seteq RC:$lhs, 0),
1598 (SLTiuOp RC:$lhs, 1)>;
1599 def : MipsPat<(setne RC:$lhs, 0),
1600 (SLTuOp ZEROReg, RC:$lhs)>;
1601 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1602 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1603 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1604 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1607 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1608 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1609 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1610 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1611 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1614 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1615 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1616 (SLTOp RC:$rhs, RC:$lhs)>;
1617 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1618 (SLTuOp RC:$rhs, RC:$lhs)>;
1621 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1622 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1623 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1624 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1625 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1628 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1629 Instruction SLTiuOp> {
1630 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1631 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1632 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1633 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1636 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1637 defm : SetlePats<GPR32, SLT, SLTu>;
1638 defm : SetgtPats<GPR32, SLT, SLTu>;
1639 defm : SetgePats<GPR32, SLT, SLTu>;
1640 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1643 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1645 // Load halfword/word patterns.
1646 let AddedComplexity = 40 in {
1647 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1648 def : LoadRegImmPat<LH, i32, sextloadi16>;
1649 def : LoadRegImmPat<LW, i32, load>;
1652 //===----------------------------------------------------------------------===//
1653 // Floating Point Support
1654 //===----------------------------------------------------------------------===//
1656 include "MipsInstrFPU.td"
1657 include "Mips64InstrInfo.td"
1658 include "MipsCondMov.td"
1660 include "Mips32r6InstrInfo.td"
1661 include "Mips64r6InstrInfo.td"
1666 include "Mips16InstrFormats.td"
1667 include "Mips16InstrInfo.td"
1670 include "MipsDSPInstrFormats.td"
1671 include "MipsDSPInstrInfo.td"
1674 include "MipsMSAInstrFormats.td"
1675 include "MipsMSAInstrInfo.td"
1678 include "MicroMipsInstrFormats.td"
1679 include "MicroMipsInstrInfo.td"
1680 include "MicroMipsInstrFPU.td"