1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
30 def SDT_MipsDivRem : SDTypeProfile<0, 2,
34 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
36 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
38 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
39 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
40 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
44 def SDTMipsLoadLR : SDTypeProfile<1, 2,
45 [SDTCisInt<0>, SDTCisPtrTy<1>,
49 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
50 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
54 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
55 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
57 // Hi and Lo nodes are used to handle global addresses. Used on
58 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
59 // static model. (nothing to do with Mips Registers Hi and Lo)
60 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
61 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
62 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
64 // TlsGd node is used to handle General Dynamic TLS
65 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
67 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
68 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
69 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
72 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
75 def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>;
77 // These are target-independent nodes, but have target-specific formats.
78 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
79 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
80 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
81 [SDNPHasChain, SDNPSideEffect,
82 SDNPOptInGlue, SDNPOutGlue]>;
85 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
86 [SDNPOptInGlue, SDNPOutGlue]>;
87 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
88 [SDNPOptInGlue, SDNPOutGlue]>;
89 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
90 [SDNPOptInGlue, SDNPOutGlue]>;
91 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
92 [SDNPOptInGlue, SDNPOutGlue]>;
95 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
97 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
100 // Target constant nodes that are not part of any isel patterns and remain
101 // unchanged can cause instructions with illegal operands to be emitted.
102 // Wrapper node patterns give the instruction selector a chance to replace
103 // target constant nodes that would otherwise remain unchanged with ADDiu
104 // nodes. Without these wrapper node patterns, the following conditional move
105 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
107 // movn %got(d)($gp), %got(c)($gp), $4
108 // This instruction is illegal since movn can take only register operands.
110 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
112 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
114 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
115 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
117 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
118 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
119 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
120 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
121 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
122 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
123 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
124 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
125 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
126 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
127 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
128 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
129 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
130 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
131 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
132 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
134 //===----------------------------------------------------------------------===//
135 // Mips Instruction Predicate Definitions.
136 //===----------------------------------------------------------------------===//
137 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
138 AssemblerPredicate<"FeatureSEInReg">;
139 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
140 AssemblerPredicate<"FeatureBitCount">;
141 def HasSwap : Predicate<"Subtarget.hasSwap()">,
142 AssemblerPredicate<"FeatureSwap">;
143 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
144 AssemblerPredicate<"FeatureCondMov">;
145 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
146 AssemblerPredicate<"FeatureFPIdx">;
147 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
148 AssemblerPredicate<"FeatureMips32">;
149 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
150 AssemblerPredicate<"FeatureMips32r2">;
151 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
152 AssemblerPredicate<"FeatureMips64">;
153 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
154 AssemblerPredicate<"!FeatureMips64">;
155 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
156 AssemblerPredicate<"FeatureMips64r2">;
157 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
158 AssemblerPredicate<"FeatureN64">;
159 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
160 AssemblerPredicate<"!FeatureN64">;
161 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
162 AssemblerPredicate<"FeatureMips16">;
163 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
164 AssemblerPredicate<"FeatureMips32">;
165 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
166 AssemblerPredicate<"FeatureMips32">;
167 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
168 AssemblerPredicate<"FeatureMips32">;
169 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
170 AssemblerPredicate<"!FeatureMips16">;
172 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
173 let Predicates = [HasStdEnc];
177 bit isCommutable = 1;
194 bit isTerminator = 1;
197 bit hasExtraSrcRegAllocReq = 1;
198 bit isCodeGenOnly = 1;
201 class IsAsCheapAsAMove {
202 bit isAsCheapAsAMove = 1;
205 class NeverHasSideEffects {
206 bit neverHasSideEffects = 1;
209 //===----------------------------------------------------------------------===//
210 // Instruction format superclass
211 //===----------------------------------------------------------------------===//
213 include "MipsInstrFormats.td"
215 //===----------------------------------------------------------------------===//
216 // Mips Operand, Complex Patterns and Transformations Definitions.
217 //===----------------------------------------------------------------------===//
219 // Instruction operand types
220 def jmptarget : Operand<OtherVT> {
221 let EncoderMethod = "getJumpTargetOpValue";
223 def brtarget : Operand<OtherVT> {
224 let EncoderMethod = "getBranchTargetOpValue";
225 let OperandType = "OPERAND_PCREL";
226 let DecoderMethod = "DecodeBranchTarget";
228 def calltarget : Operand<iPTR> {
229 let EncoderMethod = "getJumpTargetOpValue";
231 def calltarget64: Operand<i64>;
232 def simm16 : Operand<i32> {
233 let DecoderMethod= "DecodeSimm16";
235 def simm16_64 : Operand<i64>;
236 def shamt : Operand<i32>;
239 def uimm16 : Operand<i32> {
240 let PrintMethod = "printUnsignedImm";
243 def MipsMemAsmOperand : AsmOperandClass {
245 let ParserMethod = "parseMemOperand";
249 def mem : Operand<i32> {
250 let PrintMethod = "printMemOperand";
251 let MIOperandInfo = (ops CPURegs, simm16);
252 let EncoderMethod = "getMemEncoding";
253 let ParserMatchClass = MipsMemAsmOperand;
256 def mem64 : Operand<i64> {
257 let PrintMethod = "printMemOperand";
258 let MIOperandInfo = (ops CPU64Regs, simm16_64);
259 let EncoderMethod = "getMemEncoding";
260 let ParserMatchClass = MipsMemAsmOperand;
263 def mem_ea : Operand<i32> {
264 let PrintMethod = "printMemOperandEA";
265 let MIOperandInfo = (ops CPURegs, simm16);
266 let EncoderMethod = "getMemEncoding";
269 def mem_ea_64 : Operand<i64> {
270 let PrintMethod = "printMemOperandEA";
271 let MIOperandInfo = (ops CPU64Regs, simm16_64);
272 let EncoderMethod = "getMemEncoding";
275 // size operand of ext instruction
276 def size_ext : Operand<i32> {
277 let EncoderMethod = "getSizeExtEncoding";
278 let DecoderMethod = "DecodeExtSize";
281 // size operand of ins instruction
282 def size_ins : Operand<i32> {
283 let EncoderMethod = "getSizeInsEncoding";
284 let DecoderMethod = "DecodeInsSize";
287 // Transformation Function - get the lower 16 bits.
288 def LO16 : SDNodeXForm<imm, [{
289 return getImm(N, N->getZExtValue() & 0xFFFF);
292 // Transformation Function - get the higher 16 bits.
293 def HI16 : SDNodeXForm<imm, [{
294 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
297 // Node immediate fits as 16-bit sign extended on target immediate.
299 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
301 // Node immediate fits as 15-bit sign extended on target immediate.
303 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
305 // Node immediate fits as 16-bit zero extended on target immediate.
306 // The LO16 param means that only the lower 16 bits of the node
307 // immediate are caught.
309 def immZExt16 : PatLeaf<(imm), [{
310 if (N->getValueType(0) == MVT::i32)
311 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
313 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
316 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
317 def immLow16Zero : PatLeaf<(imm), [{
318 int64_t Val = N->getSExtValue();
319 return isInt<32>(Val) && !(Val & 0xffff);
322 // shamt field must fit in 5 bits.
323 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
325 // Mips Address Mode! SDNode frameindex could possibily be a match
326 // since load and store instructions from stack used it.
328 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>;
330 //===----------------------------------------------------------------------===//
331 // Instructions specific format
332 //===----------------------------------------------------------------------===//
334 // Arithmetic and logical instructions with 3 register operands.
335 class ArithLogicR<string opstr, RegisterClass RC, bit isComm = 0,
336 InstrItinClass Itin = NoItinerary,
337 SDPatternOperator OpNode = null_frag>:
338 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt),
339 !strconcat(opstr, "\t$rd, $rs, $rt"),
340 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], Itin, FrmR> {
341 let isCommutable = isComm;
342 let isReMaterializable = 1;
345 // Arithmetic and logical instructions with 2 register operands.
346 class ArithLogicI<string opstr, Operand Od, RegisterClass RC,
347 SDPatternOperator imm_type = null_frag,
348 SDPatternOperator OpNode = null_frag> :
349 InstSE<(outs RC:$rt), (ins RC:$rs, Od:$imm16),
350 !strconcat(opstr, "\t$rt, $rs, $imm16"),
351 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu, FrmI> {
352 let isReMaterializable = 1;
355 // Arithmetic Multiply ADD/SUB
356 let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
357 class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> :
358 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
359 !strconcat(instr_asm, "\t$rs, $rt"),
360 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> {
363 let isCommutable = isComm;
367 class LogicNOR<string opstr, RegisterClass RC>:
368 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt),
369 !strconcat(opstr, "\t$rd, $rs, $rt"),
370 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR> {
371 let isCommutable = 1;
375 class shift_rotate_imm<string opstr, PatFrag PF, Operand ImmOpnd,
376 RegisterClass RC, SDPatternOperator OpNode> :
377 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
378 !strconcat(opstr, "\t$rd, $rt, $shamt"),
379 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>;
381 // 32-bit shift instructions.
382 class shift_rotate_imm32<string opstr, SDPatternOperator OpNode = null_frag> :
383 shift_rotate_imm<opstr, immZExt5, shamt, CPURegs, OpNode>;
385 class shift_rotate_reg<string opstr, SDNode OpNode, RegisterClass RC>:
386 InstSE<(outs RC:$rd), (ins CPURegs:$rs, RC:$rt),
387 !strconcat(opstr, "\t$rd, $rt, $rs"),
388 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu, FrmR>;
390 // Load Upper Imediate
391 class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>:
392 FI<op, (outs RC:$rt), (ins Imm:$imm16),
393 !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu>, IsAsCheapAsAMove {
395 let neverHasSideEffects = 1;
396 let isReMaterializable = 1;
399 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
400 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
402 let Inst{25-21} = addr{20-16};
403 let Inst{15-0} = addr{15-0};
404 let DecoderMethod = "DecodeMem";
408 let canFoldAsLoad = 1 in
409 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
410 Operand MemOpnd, bit Pseudo>:
411 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr),
412 !strconcat(instr_asm, "\t$rt, $addr"),
413 [(set RC:$rt, (OpNode addr:$addr))], IILoad> {
414 let isPseudo = Pseudo;
417 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
418 Operand MemOpnd, bit Pseudo>:
419 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
420 !strconcat(instr_asm, "\t$rt, $addr"),
421 [(OpNode RC:$rt, addr:$addr)], IIStore> {
422 let isPseudo = Pseudo;
426 multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode,
428 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
429 Requires<[NotN64, HasStdEnc]>;
430 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
431 Requires<[IsN64, HasStdEnc]> {
432 let DecoderNamespace = "Mips64";
433 let isCodeGenOnly = 1;
438 multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode,
440 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
441 Requires<[NotN64, HasStdEnc]>;
442 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
443 Requires<[IsN64, HasStdEnc]> {
444 let DecoderNamespace = "Mips64";
445 let isCodeGenOnly = 1;
450 multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode,
452 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
453 Requires<[NotN64, HasStdEnc]>;
454 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
455 Requires<[IsN64, HasStdEnc]> {
456 let DecoderNamespace = "Mips64";
457 let isCodeGenOnly = 1;
462 multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode,
464 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
465 Requires<[NotN64, HasStdEnc]>;
466 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
467 Requires<[IsN64, HasStdEnc]> {
468 let DecoderNamespace = "Mips64";
469 let isCodeGenOnly = 1;
473 // Load/Store Left/Right
474 let canFoldAsLoad = 1 in
475 class LoadLeftRight<bits<6> op, string instr_asm, SDNode OpNode,
476 RegisterClass RC, Operand MemOpnd> :
477 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr, RC:$src),
478 !strconcat(instr_asm, "\t$rt, $addr"),
479 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], IILoad> {
480 string Constraints = "$src = $rt";
483 class StoreLeftRight<bits<6> op, string instr_asm, SDNode OpNode,
484 RegisterClass RC, Operand MemOpnd>:
485 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
486 !strconcat(instr_asm, "\t$rt, $addr"), [(OpNode RC:$rt, addr:$addr)],
489 // 32-bit load left/right.
490 multiclass LoadLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> {
491 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem>,
492 Requires<[NotN64, HasStdEnc]>;
493 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem64>,
494 Requires<[IsN64, HasStdEnc]> {
495 let DecoderNamespace = "Mips64";
496 let isCodeGenOnly = 1;
500 // 64-bit load left/right.
501 multiclass LoadLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> {
502 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>,
503 Requires<[NotN64, HasStdEnc]>;
504 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>,
505 Requires<[IsN64, HasStdEnc]> {
506 let DecoderNamespace = "Mips64";
507 let isCodeGenOnly = 1;
511 // 32-bit store left/right.
512 multiclass StoreLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> {
513 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem>,
514 Requires<[NotN64, HasStdEnc]>;
515 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem64>,
516 Requires<[IsN64, HasStdEnc]> {
517 let DecoderNamespace = "Mips64";
518 let isCodeGenOnly = 1;
522 // 64-bit store left/right.
523 multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> {
524 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>,
525 Requires<[NotN64, HasStdEnc]>;
526 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>,
527 Requires<[IsN64, HasStdEnc]> {
528 let DecoderNamespace = "Mips64";
529 let isCodeGenOnly = 1;
533 // Conditional Branch
534 class CBranch<string opstr, PatFrag cond_op, RegisterClass RC> :
535 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset),
536 !strconcat(opstr, "\t$rs, $rt, $offset"),
537 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch,
540 let isTerminator = 1;
541 let hasDelaySlot = 1;
545 class CBranchZero<string opstr, PatFrag cond_op, RegisterClass RC> :
546 InstSE<(outs), (ins RC:$rs, brtarget:$offset),
547 !strconcat(opstr, "\t$rs, $offset"),
548 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> {
550 let isTerminator = 1;
551 let hasDelaySlot = 1;
556 class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> :
557 InstSE<(outs CPURegs:$rd), (ins RC:$rs, RC:$rt),
558 !strconcat(opstr, "\t$rd, $rs, $rt"),
559 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))], IIAlu, FrmR>;
561 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
563 InstSE<(outs CPURegs:$rt), (ins RC:$rs, Od:$imm16),
564 !strconcat(opstr, "\t$rt, $rs, $imm16"),
565 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))], IIAlu, FrmI>;
568 class JumpFJ<bits<6> op, DAGOperand opnd, string instr_asm,
569 SDPatternOperator operator, SDPatternOperator targetoperator>:
570 FJ<op, (outs), (ins opnd:$target), !strconcat(instr_asm, "\t$target"),
571 [(operator targetoperator:$target)], IIBranch> {
574 let hasDelaySlot = 1;
575 let DecoderMethod = "DecodeJumpTarget";
579 // Unconditional branch
580 class UncondBranch<string opstr> :
581 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
582 [(br bb:$offset)], IIBranch, FrmI> {
584 let isTerminator = 1;
586 let hasDelaySlot = 1;
587 let Predicates = [RelocPIC, HasStdEnc];
591 // Base class for indirect branch and return instruction classes.
592 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
593 class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>:
594 FR<0, 0x8, (outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch> {
601 class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> {
603 let isIndirectBranch = 1;
606 // Return instruction
607 class RetBase<RegisterClass RC>: JumpFR<RC> {
609 let isCodeGenOnly = 1;
611 let hasExtraSrcRegAllocReq = 1;
614 // Jump and Link (Call)
615 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
616 class JumpLink<bits<6> op, string instr_asm>:
617 FJ<op, (outs), (ins calltarget:$target),
618 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
620 let DecoderMethod = "DecodeJumpTarget";
623 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm,
625 FR<op, func, (outs), (ins RC:$rs),
626 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> {
632 class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>:
633 FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16),
634 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> {
640 class Mult<bits<6> func, string instr_asm, InstrItinClass itin,
641 RegisterClass RC, list<Register> DefRegs>:
642 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
643 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> {
646 let isCommutable = 1;
648 let neverHasSideEffects = 1;
651 class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>:
652 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>;
654 class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin,
655 RegisterClass RC, list<Register> DefRegs>:
656 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
657 !strconcat(instr_asm, "\t$$zero, $rs, $rt"),
658 [(op RC:$rs, RC:$rt)], itin> {
664 class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
665 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>;
668 class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>:
669 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> {
671 let neverHasSideEffects = 1;
674 class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>:
675 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> {
677 let neverHasSideEffects = 1;
680 class EffectiveAddress<bits<6> opc, string instr_asm, RegisterClass RC, Operand Mem> :
681 FMem<opc, (outs RC:$rt), (ins Mem:$addr),
682 instr_asm, [(set RC:$rt, addr:$addr)], IIAlu> {
683 let isCodeGenOnly = 1;
686 // Count Leading Ones/Zeros in Word
687 class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>:
688 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
689 !strconcat(instr_asm, "\t$rd, $rs"),
690 [(set RC:$rd, (ctlz RC:$rs))], IIAlu>,
691 Requires<[HasBitCount, HasStdEnc]> {
696 class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>:
697 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
698 !strconcat(instr_asm, "\t$rd, $rs"),
699 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>,
700 Requires<[HasBitCount, HasStdEnc]> {
705 // Sign Extend in Register.
706 class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt,
708 FR<0x1f, 0x20, (outs RC:$rd), (ins RC:$rt),
709 !strconcat(instr_asm, "\t$rd, $rt"),
710 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary> {
713 let Predicates = [HasSEInReg, HasStdEnc];
717 class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>:
718 FR<0x1f, func, (outs RC:$rd), (ins RC:$rt),
719 !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> {
722 let Predicates = [HasSwap, HasStdEnc];
723 let neverHasSideEffects = 1;
727 class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass>
728 : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd),
729 "rdhwr\t$rt, $rd", [], IIAlu> {
735 class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
736 FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz),
737 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
738 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> {
743 let Predicates = [HasMips32r2, HasStdEnc];
746 class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
747 FR<0x1f, _funct, (outs RC:$rt),
748 (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src),
749 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
750 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))],
756 let Predicates = [HasMips32r2, HasStdEnc];
757 let Constraints = "$src = $rt";
760 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
761 class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
762 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
763 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
765 multiclass Atomic2Ops32<PatFrag Op> {
766 def #NAME# : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>;
767 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>,
768 Requires<[IsN64, HasStdEnc]> {
769 let DecoderNamespace = "Mips64";
773 // Atomic Compare & Swap.
774 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
775 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
776 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
778 multiclass AtomicCmpSwap32<PatFrag Op> {
779 def #NAME# : AtomicCmpSwap<Op, CPURegs, CPURegs>,
780 Requires<[NotN64, HasStdEnc]>;
781 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>,
782 Requires<[IsN64, HasStdEnc]> {
783 let DecoderNamespace = "Mips64";
787 class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
788 FMem<Opc, (outs RC:$rt), (ins Mem:$addr),
789 !strconcat(opstring, "\t$rt, $addr"), [], IILoad> {
793 class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
794 FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr),
795 !strconcat(opstring, "\t$rt, $addr"), [], IIStore> {
797 let Constraints = "$rt = $dst";
800 //===----------------------------------------------------------------------===//
801 // Pseudo instructions
802 //===----------------------------------------------------------------------===//
805 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
806 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
808 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
809 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
810 [(callseq_start timm:$amt)]>;
811 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
812 [(callseq_end timm:$amt1, timm:$amt2)]>;
815 let usesCustomInserter = 1 in {
816 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>;
817 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>;
818 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>;
819 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>;
820 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>;
821 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>;
822 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>;
823 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>;
824 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>;
825 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>;
826 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>;
827 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>;
828 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>;
829 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>;
830 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>;
831 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>;
832 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>;
833 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>;
835 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>;
836 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>;
837 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>;
839 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>;
840 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>;
841 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>;
844 //===----------------------------------------------------------------------===//
845 // Instruction definition
846 //===----------------------------------------------------------------------===//
847 //===----------------------------------------------------------------------===//
848 // MipsI Instructions
849 //===----------------------------------------------------------------------===//
851 /// Arithmetic Instructions (ALU Immediate)
852 def ADDiu : ArithLogicI<"addiu", simm16, CPURegs, immSExt16, add>,
853 ADDI_FM<0x9>, IsAsCheapAsAMove;
854 def ADDi : ArithLogicI<"addi", simm16, CPURegs>, ADDI_FM<0x8>;
855 def SLTi : SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, SLTI_FM<0xa>;
856 def SLTiu : SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, SLTI_FM<0xb>;
857 def ANDi : ArithLogicI<"andi", uimm16, CPURegs, immZExt16, and>, ADDI_FM<0xc>;
858 def ORi : ArithLogicI<"ori", uimm16, CPURegs, immZExt16, or>, ADDI_FM<0xd>;
859 def XORi : ArithLogicI<"xori", uimm16, CPURegs, immZExt16, xor>, ADDI_FM<0xe>;
860 def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>;
862 /// Arithmetic Instructions (3-Operand, R-Type)
863 def ADDu : ArithLogicR<"addu", CPURegs, 1, IIAlu, add>, ADD_FM<0, 0x21>;
864 def SUBu : ArithLogicR<"subu", CPURegs, 0, IIAlu, sub>, ADD_FM<0, 0x23>;
865 def MUL : ArithLogicR<"mul", CPURegs, 1, IIImul, mul>, ADD_FM<0x1c, 2>;
866 def ADD : ArithLogicR<"add", CPURegs>, ADD_FM<0, 0x20>;
867 def SUB : ArithLogicR<"sub", CPURegs>, ADD_FM<0, 0x22>;
868 def SLT : SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>;
869 def SLTu : SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>;
870 def AND : ArithLogicR<"and", CPURegs, 1, IIAlu, and>, ADD_FM<0, 0x24>;
871 def OR : ArithLogicR<"or", CPURegs, 1, IIAlu, or>, ADD_FM<0, 0x25>;
872 def XOR : ArithLogicR<"xor", CPURegs, 1, IIAlu, xor>, ADD_FM<0, 0x26>;
873 def NOR : LogicNOR<"nor", CPURegs>, ADD_FM<0, 0x27>;
875 /// Shift Instructions
876 def SLL : shift_rotate_imm32<"sll", shl>, SRA_FM<0, 0>;
877 def SRL : shift_rotate_imm32<"srl", srl>, SRA_FM<2, 0>;
878 def SRA : shift_rotate_imm32<"sra", sra>, SRA_FM<3, 0>;
879 def SLLV : shift_rotate_reg<"sllv", shl, CPURegs>, SRLV_FM<4, 0>;
880 def SRLV : shift_rotate_reg<"srlv", srl, CPURegs>, SRLV_FM<6, 0>;
881 def SRAV : shift_rotate_reg<"srav", sra, CPURegs>, SRLV_FM<7, 0>;
883 // Rotate Instructions
884 let Predicates = [HasMips32r2, HasStdEnc] in {
885 def ROTR : shift_rotate_imm32<"rotr", rotr>, SRA_FM<2, 1>;
886 def ROTRV : shift_rotate_reg<"rotrv", rotr, CPURegs>, SRLV_FM<6, 1>;
889 /// Load and Store Instructions
891 defm LB : LoadM32<0x20, "lb", sextloadi8>;
892 defm LBu : LoadM32<0x24, "lbu", zextloadi8>;
893 defm LH : LoadM32<0x21, "lh", sextloadi16>;
894 defm LHu : LoadM32<0x25, "lhu", zextloadi16>;
895 defm LW : LoadM32<0x23, "lw", load>;
896 defm SB : StoreM32<0x28, "sb", truncstorei8>;
897 defm SH : StoreM32<0x29, "sh", truncstorei16>;
898 defm SW : StoreM32<0x2b, "sw", store>;
900 /// load/store left/right
901 defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>;
902 defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>;
903 defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>;
904 defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>;
906 let hasSideEffects = 1 in
907 def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype",
908 [(MipsSync imm:$stype)], NoItinerary, FrmOther>
913 let Inst{10-6} = stype;
917 /// Load-linked, Store-conditional
918 def LL : LLBase<0x30, "ll", CPURegs, mem>,
919 Requires<[NotN64, HasStdEnc]>;
920 def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>,
921 Requires<[IsN64, HasStdEnc]> {
922 let DecoderNamespace = "Mips64";
925 def SC : SCBase<0x38, "sc", CPURegs, mem>,
926 Requires<[NotN64, HasStdEnc]>;
927 def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>,
928 Requires<[IsN64, HasStdEnc]> {
929 let DecoderNamespace = "Mips64";
932 /// Jump and Branch Instructions
933 def J : JumpFJ<0x02, jmptarget, "j", br, bb>,
934 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
935 def JR : IndirectBranch<CPURegs>;
936 def B : UncondBranch<"b">, B_FM;
937 def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>;
938 def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>;
939 def BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>;
940 def BGTZ : CBranchZero<"bgtz", setgt, CPURegs>, BGEZ_FM<7, 0>;
941 def BLEZ : CBranchZero<"blez", setle, CPURegs>, BGEZ_FM<6, 0>;
942 def BLTZ : CBranchZero<"bltz", setlt, CPURegs>, BGEZ_FM<1, 0>;
944 let rt = 0, rs = 0, isBranch = 1, isTerminator = 1, isBarrier = 1,
945 hasDelaySlot = 1, Defs = [RA] in
946 def BAL_BR: FI<0x1, (outs), (ins brtarget:$imm16), "bal\t$imm16", [], IIBranch>;
948 def JAL : JumpLink<0x03, "jal">;
949 def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>;
950 def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>;
951 def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>;
952 def TAILCALL : JumpFJ<0x02, calltarget, "j", MipsTailCall, imm>, IsTailCall;
953 def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, IsTailCall;
955 def RET : RetBase<CPURegs>;
957 /// Multiply and Divide Instructions.
958 def MULT : Mult32<0x18, "mult", IIImul>;
959 def MULTu : Mult32<0x19, "multu", IIImul>;
960 def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>;
961 def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>;
963 def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>;
964 def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>;
965 def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>;
966 def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>;
968 /// Sign Ext In Register Instructions.
969 def SEB : SignExtInReg<0x10, "seb", i8, CPURegs>;
970 def SEH : SignExtInReg<0x18, "seh", i16, CPURegs>;
973 def CLZ : CountLeading0<0x20, "clz", CPURegs>;
974 def CLO : CountLeading1<0x21, "clo", CPURegs>;
976 /// Word Swap Bytes Within Halfwords
977 def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>;
981 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
983 // FrameIndexes are legalized when they are operands from load/store
984 // instructions. The same not happens for stack address copies, so an
985 // add op with mem ComplexPattern is used and the stack address copy
986 // can be matched. It's similar to Sparc LEA_ADDRi
987 def LEA_ADDiu : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>;
990 def MADD : MArithR<0, "madd", MipsMAdd, 1>;
991 def MADDU : MArithR<1, "maddu", MipsMAddu, 1>;
992 def MSUB : MArithR<4, "msub", MipsMSub>;
993 def MSUBU : MArithR<5, "msubu", MipsMSubu>;
995 def RDHWR : ReadHardware<CPURegs, HWRegs>;
997 def EXT : ExtBase<0, "ext", CPURegs>;
998 def INS : InsBase<4, "ins", CPURegs>;
1000 /// Move Control Registers From/To CPU Registers
1001 def MFC0_3OP : MFC3OP<0x10, 0, (outs CPURegs:$rt),
1002 (ins CPURegs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">;
1003 def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegs:$rt, CPURegs:$rd, 0)>;
1005 def MTC0_3OP : MFC3OP<0x10, 4, (outs CPURegs:$rd, uimm16:$sel),
1006 (ins CPURegs:$rt),"mtc0\t$rt, $rd, $sel">;
1007 def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegs:$rd, 0, CPURegs:$rt)>;
1009 def MFC2_3OP : MFC3OP<0x12, 0, (outs CPURegs:$rt),
1010 (ins CPURegs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">;
1011 def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegs:$rt, CPURegs:$rd, 0)>;
1013 def MTC2_3OP : MFC3OP<0x12, 4, (outs CPURegs:$rd, uimm16:$sel),
1014 (ins CPURegs:$rt),"mtc2\t$rt, $rd, $sel">;
1015 def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>;
1017 //===----------------------------------------------------------------------===//
1018 // Instruction aliases
1019 //===----------------------------------------------------------------------===//
1020 def : InstAlias<"move $dst,$src", (ADD CPURegs:$dst,CPURegs:$src,ZERO)>;
1021 def : InstAlias<"bal $offset", (BGEZAL RA,brtarget:$offset)>;
1022 def : InstAlias<"addu $rs,$rt,$imm",
1023 (ADDiu CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
1024 def : InstAlias<"add $rs,$rt,$imm",
1025 (ADDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
1026 def : InstAlias<"and $rs,$rt,$imm",
1027 (ANDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
1028 def : InstAlias<"j $rs", (JR CPURegs:$rs)>;
1029 def : InstAlias<"not $rt,$rs", (NOR CPURegs:$rt,CPURegs:$rs,ZERO)>;
1030 def : InstAlias<"neg $rt,$rs", (SUB CPURegs:$rt,ZERO,CPURegs:$rs)>;
1031 def : InstAlias<"negu $rt,$rs", (SUBu CPURegs:$rt,ZERO,CPURegs:$rs)>;
1032 def : InstAlias<"slt $rs,$rt,$imm",
1033 (SLTi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
1034 def : InstAlias<"xor $rs,$rt,$imm",
1035 (XORi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
1037 //===----------------------------------------------------------------------===//
1038 // Assembler Pseudo Instructions
1039 //===----------------------------------------------------------------------===//
1041 class LoadImm32< string instr_asm, Operand Od, RegisterClass RC> :
1042 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32),
1043 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1044 def LoadImm32Reg : LoadImm32<"li", shamt,CPURegs>;
1046 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterClass RC> :
1047 MipsAsmPseudoInst<(outs RC:$rt), (ins MemOpnd:$addr),
1048 !strconcat(instr_asm, "\t$rt, $addr")> ;
1049 def LoadAddr32Reg : LoadAddress<"la", mem, CPURegs>;
1051 class LoadAddressImm<string instr_asm, Operand Od, RegisterClass RC> :
1052 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32),
1053 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1054 def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegs>;
1058 //===----------------------------------------------------------------------===//
1059 // Arbitrary patterns that map to one or more instructions
1060 //===----------------------------------------------------------------------===//
1063 def : MipsPat<(i32 immSExt16:$in),
1064 (ADDiu ZERO, imm:$in)>;
1065 def : MipsPat<(i32 immZExt16:$in),
1066 (ORi ZERO, imm:$in)>;
1067 def : MipsPat<(i32 immLow16Zero:$in),
1068 (LUi (HI16 imm:$in))>;
1070 // Arbitrary immediates
1071 def : MipsPat<(i32 imm:$imm),
1072 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1074 // Carry MipsPatterns
1075 def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs),
1076 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
1077 def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs),
1078 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
1079 def : MipsPat<(addc CPURegs:$src, immSExt16:$imm),
1080 (ADDiu CPURegs:$src, imm:$imm)>;
1083 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1084 (JAL tglobaladdr:$dst)>;
1085 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1086 (JAL texternalsym:$dst)>;
1087 //def : MipsPat<(MipsJmpLink CPURegs:$dst),
1088 // (JALR CPURegs:$dst)>;
1091 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1092 (TAILCALL tglobaladdr:$dst)>;
1093 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1094 (TAILCALL texternalsym:$dst)>;
1096 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1097 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1098 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1099 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1100 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1101 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1103 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1104 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1105 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1106 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1107 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1108 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1110 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
1111 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
1112 def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
1113 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
1114 def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
1115 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
1116 def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
1117 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
1118 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)),
1119 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
1122 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
1123 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
1124 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
1125 (ADDiu CPURegs:$gp, tconstpool:$in)>;
1128 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1129 MipsPat<(MipsWrapper RC:$gp, node:$in),
1130 (ADDiuOp RC:$gp, node:$in)>;
1132 def : WrapperPat<tglobaladdr, ADDiu, CPURegs>;
1133 def : WrapperPat<tconstpool, ADDiu, CPURegs>;
1134 def : WrapperPat<texternalsym, ADDiu, CPURegs>;
1135 def : WrapperPat<tblockaddress, ADDiu, CPURegs>;
1136 def : WrapperPat<tjumptable, ADDiu, CPURegs>;
1137 def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>;
1139 // Mips does not have "not", so we expand our way
1140 def : MipsPat<(not CPURegs:$in),
1141 (NOR CPURegs:$in, ZERO)>;
1144 let Predicates = [NotN64, HasStdEnc] in {
1145 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1146 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1147 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1149 let Predicates = [IsN64, HasStdEnc] in {
1150 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
1151 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
1152 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>;
1156 let Predicates = [NotN64, HasStdEnc] in {
1157 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1159 let Predicates = [IsN64, HasStdEnc] in {
1160 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
1164 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1165 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1166 Instruction SLTiuOp, Register ZEROReg> {
1167 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1168 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1169 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1170 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1172 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1173 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1174 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1175 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1176 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1177 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1178 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1179 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1181 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1182 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1183 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1184 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1186 def : MipsPat<(brcond RC:$cond, bb:$dst),
1187 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1190 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1193 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1194 Instruction SLTuOp, Register ZEROReg> {
1195 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1196 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1197 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1198 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1201 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1202 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1203 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1204 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1205 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1208 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1209 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1210 (SLTOp RC:$rhs, RC:$lhs)>;
1211 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1212 (SLTuOp RC:$rhs, RC:$lhs)>;
1215 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1216 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1217 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1218 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1219 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1222 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1223 Instruction SLTiuOp> {
1224 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1225 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1226 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1227 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1230 defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
1231 defm : SetlePats<CPURegs, SLT, SLTu>;
1232 defm : SetgtPats<CPURegs, SLT, SLTu>;
1233 defm : SetgePats<CPURegs, SLT, SLTu>;
1234 defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
1237 def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
1239 //===----------------------------------------------------------------------===//
1240 // Floating Point Support
1241 //===----------------------------------------------------------------------===//
1243 include "MipsInstrFPU.td"
1244 include "Mips64InstrInfo.td"
1245 include "MipsCondMov.td"
1250 include "Mips16InstrFormats.td"
1251 include "Mips16InstrInfo.td"
1254 include "MipsDSPInstrFormats.td"
1255 include "MipsDSPInstrInfo.td"