1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
30 def SDT_MipsDivRem : SDTypeProfile<0, 2,
34 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
36 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
38 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
39 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
40 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
44 def SDTMipsLoadLR : SDTypeProfile<1, 2,
45 [SDTCisInt<0>, SDTCisPtrTy<1>,
49 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
50 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
54 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
55 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
57 // Hi and Lo nodes are used to handle global addresses. Used on
58 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
59 // static model. (nothing to do with Mips Registers Hi and Lo)
60 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
61 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
62 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
64 // TlsGd node is used to handle General Dynamic TLS
65 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
67 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
68 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
69 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
72 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
75 def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>;
77 // These are target-independent nodes, but have target-specific formats.
78 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
79 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
80 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
81 [SDNPHasChain, SDNPSideEffect,
82 SDNPOptInGlue, SDNPOutGlue]>;
85 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
86 [SDNPOptInGlue, SDNPOutGlue]>;
87 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
88 [SDNPOptInGlue, SDNPOutGlue]>;
89 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
90 [SDNPOptInGlue, SDNPOutGlue]>;
91 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
92 [SDNPOptInGlue, SDNPOutGlue]>;
95 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
97 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
100 // Target constant nodes that are not part of any isel patterns and remain
101 // unchanged can cause instructions with illegal operands to be emitted.
102 // Wrapper node patterns give the instruction selector a chance to replace
103 // target constant nodes that would otherwise remain unchanged with ADDiu
104 // nodes. Without these wrapper node patterns, the following conditional move
105 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
107 // movn %got(d)($gp), %got(c)($gp), $4
108 // This instruction is illegal since movn can take only register operands.
110 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
112 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
114 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
115 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
117 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
118 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
119 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
120 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
121 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
122 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
123 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
124 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
125 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
126 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
127 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
128 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
129 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
130 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
131 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
132 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
134 //===----------------------------------------------------------------------===//
135 // Mips Instruction Predicate Definitions.
136 //===----------------------------------------------------------------------===//
137 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
138 AssemblerPredicate<"FeatureSEInReg">;
139 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
140 AssemblerPredicate<"FeatureBitCount">;
141 def HasSwap : Predicate<"Subtarget.hasSwap()">,
142 AssemblerPredicate<"FeatureSwap">;
143 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
144 AssemblerPredicate<"FeatureCondMov">;
145 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
146 AssemblerPredicate<"FeatureFPIdx">;
147 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
148 AssemblerPredicate<"FeatureMips32">;
149 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
150 AssemblerPredicate<"FeatureMips32r2">;
151 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
152 AssemblerPredicate<"FeatureMips64">;
153 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
154 AssemblerPredicate<"!FeatureMips64">;
155 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
156 AssemblerPredicate<"FeatureMips64r2">;
157 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
158 AssemblerPredicate<"FeatureN64">;
159 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
160 AssemblerPredicate<"!FeatureN64">;
161 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
162 AssemblerPredicate<"FeatureMips16">;
163 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
164 AssemblerPredicate<"FeatureMips32">;
165 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
166 AssemblerPredicate<"FeatureMips32">;
167 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
168 AssemblerPredicate<"FeatureMips32">;
169 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
170 AssemblerPredicate<"!FeatureMips16">;
172 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
173 let Predicates = [HasStdEnc];
177 bit isCommutable = 1;
194 bit isTerminator = 1;
197 bit hasExtraSrcRegAllocReq = 1;
198 bit isCodeGenOnly = 1;
201 class IsAsCheapAsAMove {
202 bit isAsCheapAsAMove = 1;
205 class NeverHasSideEffects {
206 bit neverHasSideEffects = 1;
209 //===----------------------------------------------------------------------===//
210 // Instruction format superclass
211 //===----------------------------------------------------------------------===//
213 include "MipsInstrFormats.td"
215 //===----------------------------------------------------------------------===//
216 // Mips Operand, Complex Patterns and Transformations Definitions.
217 //===----------------------------------------------------------------------===//
219 // Instruction operand types
220 def jmptarget : Operand<OtherVT> {
221 let EncoderMethod = "getJumpTargetOpValue";
223 def brtarget : Operand<OtherVT> {
224 let EncoderMethod = "getBranchTargetOpValue";
225 let OperandType = "OPERAND_PCREL";
226 let DecoderMethod = "DecodeBranchTarget";
228 def calltarget : Operand<iPTR> {
229 let EncoderMethod = "getJumpTargetOpValue";
231 def calltarget64: Operand<i64>;
232 def simm16 : Operand<i32> {
233 let DecoderMethod= "DecodeSimm16";
235 def simm16_64 : Operand<i64>;
236 def shamt : Operand<i32>;
239 def uimm16 : Operand<i32> {
240 let PrintMethod = "printUnsignedImm";
243 def MipsMemAsmOperand : AsmOperandClass {
245 let ParserMethod = "parseMemOperand";
249 def mem : Operand<i32> {
250 let PrintMethod = "printMemOperand";
251 let MIOperandInfo = (ops CPURegs, simm16);
252 let EncoderMethod = "getMemEncoding";
253 let ParserMatchClass = MipsMemAsmOperand;
256 def mem64 : Operand<i64> {
257 let PrintMethod = "printMemOperand";
258 let MIOperandInfo = (ops CPU64Regs, simm16_64);
259 let EncoderMethod = "getMemEncoding";
260 let ParserMatchClass = MipsMemAsmOperand;
263 def mem_ea : Operand<i32> {
264 let PrintMethod = "printMemOperandEA";
265 let MIOperandInfo = (ops CPURegs, simm16);
266 let EncoderMethod = "getMemEncoding";
269 def mem_ea_64 : Operand<i64> {
270 let PrintMethod = "printMemOperandEA";
271 let MIOperandInfo = (ops CPU64Regs, simm16_64);
272 let EncoderMethod = "getMemEncoding";
275 // size operand of ext instruction
276 def size_ext : Operand<i32> {
277 let EncoderMethod = "getSizeExtEncoding";
278 let DecoderMethod = "DecodeExtSize";
281 // size operand of ins instruction
282 def size_ins : Operand<i32> {
283 let EncoderMethod = "getSizeInsEncoding";
284 let DecoderMethod = "DecodeInsSize";
287 // Transformation Function - get the lower 16 bits.
288 def LO16 : SDNodeXForm<imm, [{
289 return getImm(N, N->getZExtValue() & 0xFFFF);
292 // Transformation Function - get the higher 16 bits.
293 def HI16 : SDNodeXForm<imm, [{
294 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
297 // Node immediate fits as 16-bit sign extended on target immediate.
299 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
301 // Node immediate fits as 15-bit sign extended on target immediate.
303 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
305 // Node immediate fits as 16-bit zero extended on target immediate.
306 // The LO16 param means that only the lower 16 bits of the node
307 // immediate are caught.
309 def immZExt16 : PatLeaf<(imm), [{
310 if (N->getValueType(0) == MVT::i32)
311 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
313 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
316 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
317 def immLow16Zero : PatLeaf<(imm), [{
318 int64_t Val = N->getSExtValue();
319 return isInt<32>(Val) && !(Val & 0xffff);
322 // shamt field must fit in 5 bits.
323 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
325 // Mips Address Mode! SDNode frameindex could possibily be a match
326 // since load and store instructions from stack used it.
328 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>;
330 //===----------------------------------------------------------------------===//
331 // Instructions specific format
332 //===----------------------------------------------------------------------===//
334 // Arithmetic and logical instructions with 3 register operands.
335 class ArithLogicR<string opstr, RegisterClass RC, bit isComm = 0,
336 InstrItinClass Itin = NoItinerary,
337 SDPatternOperator OpNode = null_frag>:
338 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt),
339 !strconcat(opstr, "\t$rd, $rs, $rt"),
340 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], Itin, FrmR> {
341 let isCommutable = isComm;
342 let isReMaterializable = 1;
345 // Arithmetic and logical instructions with 2 register operands.
346 class ArithLogicI<string opstr, Operand Od, RegisterClass RC,
347 SDPatternOperator imm_type = null_frag,
348 SDPatternOperator OpNode = null_frag> :
349 InstSE<(outs RC:$rt), (ins RC:$rs, Od:$imm16),
350 !strconcat(opstr, "\t$rt, $rs, $imm16"),
351 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu, FrmI> {
352 let isReMaterializable = 1;
355 // Arithmetic Multiply ADD/SUB
356 let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
357 class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> :
358 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
359 !strconcat(instr_asm, "\t$rs, $rt"),
360 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> {
363 let isCommutable = isComm;
367 class LogicNOR<string opstr, RegisterClass RC>:
368 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt),
369 !strconcat(opstr, "\t$rd, $rs, $rt"),
370 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR> {
371 let isCommutable = 1;
375 class shift_rotate_imm<string opstr, PatFrag PF, Operand ImmOpnd,
376 RegisterClass RC, SDPatternOperator OpNode> :
377 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
378 !strconcat(opstr, "\t$rd, $rt, $shamt"),
379 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>;
381 // 32-bit shift instructions.
382 class shift_rotate_imm32<string opstr, SDPatternOperator OpNode = null_frag> :
383 shift_rotate_imm<opstr, immZExt5, shamt, CPURegs, OpNode>;
385 class shift_rotate_reg<string opstr, SDNode OpNode, RegisterClass RC>:
386 InstSE<(outs RC:$rd), (ins CPURegs:$rs, RC:$rt),
387 !strconcat(opstr, "\t$rd, $rt, $rs"),
388 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu, FrmR>;
390 // Load Upper Imediate
391 class LoadUpper<string opstr, RegisterClass RC, Operand Imm>:
392 InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
393 [], IIAlu, FrmI>, IsAsCheapAsAMove {
394 let neverHasSideEffects = 1;
395 let isReMaterializable = 1;
398 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
399 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
401 let Inst{25-21} = addr{20-16};
402 let Inst{15-0} = addr{15-0};
403 let DecoderMethod = "DecodeMem";
407 class Load<string opstr, PatFrag OpNode, RegisterClass RC, Operand MemOpnd> :
408 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
409 [(set RC:$rt, (OpNode addr:$addr))], NoItinerary, FrmI> {
410 let DecoderMethod = "DecodeMem";
411 let canFoldAsLoad = 1;
414 class Store<string opstr, PatFrag OpNode, RegisterClass RC, Operand MemOpnd> :
415 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
416 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> {
417 let DecoderMethod = "DecodeMem";
420 multiclass LoadM<string opstr, PatFrag OpNode, RegisterClass RC> {
421 def #NAME# : Load<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>;
422 def _P8 : Load<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> {
423 let DecoderNamespace = "Mips64";
424 let isCodeGenOnly = 1;
428 multiclass StoreM<string opstr, PatFrag OpNode, RegisterClass RC> {
429 def #NAME# : Store<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>;
430 def _P8 : Store<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> {
431 let DecoderNamespace = "Mips64";
432 let isCodeGenOnly = 1;
436 // Load/Store Left/Right
437 let canFoldAsLoad = 1 in
438 class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
440 InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src),
441 !strconcat(opstr, "\t$rt, $addr"),
442 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> {
443 let DecoderMethod = "DecodeMem";
444 string Constraints = "$src = $rt";
447 class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
449 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
450 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> {
451 let DecoderMethod = "DecodeMem";
454 multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
455 def #NAME# : LoadLeftRight<opstr, OpNode, RC, mem>,
456 Requires<[NotN64, HasStdEnc]>;
457 def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>,
458 Requires<[IsN64, HasStdEnc]> {
459 let DecoderNamespace = "Mips64";
460 let isCodeGenOnly = 1;
464 multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
465 def #NAME# : StoreLeftRight<opstr, OpNode, RC, mem>,
466 Requires<[NotN64, HasStdEnc]>;
467 def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>,
468 Requires<[IsN64, HasStdEnc]> {
469 let DecoderNamespace = "Mips64";
470 let isCodeGenOnly = 1;
474 // Conditional Branch
475 class CBranch<string opstr, PatFrag cond_op, RegisterClass RC> :
476 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset),
477 !strconcat(opstr, "\t$rs, $rt, $offset"),
478 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch,
481 let isTerminator = 1;
482 let hasDelaySlot = 1;
486 class CBranchZero<string opstr, PatFrag cond_op, RegisterClass RC> :
487 InstSE<(outs), (ins RC:$rs, brtarget:$offset),
488 !strconcat(opstr, "\t$rs, $offset"),
489 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> {
491 let isTerminator = 1;
492 let hasDelaySlot = 1;
497 class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> :
498 InstSE<(outs CPURegs:$rd), (ins RC:$rs, RC:$rt),
499 !strconcat(opstr, "\t$rd, $rs, $rt"),
500 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))], IIAlu, FrmR>;
502 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
504 InstSE<(outs CPURegs:$rt), (ins RC:$rs, Od:$imm16),
505 !strconcat(opstr, "\t$rt, $rs, $imm16"),
506 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))], IIAlu, FrmI>;
509 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
510 SDPatternOperator targetoperator> :
511 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
512 [(operator targetoperator:$target)], IIBranch, FrmJ> {
515 let hasDelaySlot = 1;
516 let DecoderMethod = "DecodeJumpTarget";
520 // Unconditional branch
521 class UncondBranch<string opstr> :
522 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
523 [(br bb:$offset)], IIBranch, FrmI> {
525 let isTerminator = 1;
527 let hasDelaySlot = 1;
528 let Predicates = [RelocPIC, HasStdEnc];
532 // Base class for indirect branch and return instruction classes.
533 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
534 class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>:
535 InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>;
538 class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> {
540 let isIndirectBranch = 1;
543 // Return instruction
544 class RetBase<RegisterClass RC>: JumpFR<RC> {
546 let isCodeGenOnly = 1;
548 let hasExtraSrcRegAllocReq = 1;
551 // Jump and Link (Call)
552 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
553 class JumpLink<string opstr> :
554 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"),
555 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> {
556 let DecoderMethod = "DecodeJumpTarget";
559 class JumpLinkReg<string opstr, RegisterClass RC>:
560 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"),
561 [(MipsJmpLink RC:$rs)], IIBranch, FrmR>;
563 class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>:
564 FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16),
565 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> {
571 class Mult<bits<6> func, string instr_asm, InstrItinClass itin,
572 RegisterClass RC, list<Register> DefRegs>:
573 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
574 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> {
577 let isCommutable = 1;
579 let neverHasSideEffects = 1;
582 class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>:
583 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>;
585 class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin,
586 RegisterClass RC, list<Register> DefRegs>:
587 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
588 !strconcat(instr_asm, "\t$$zero, $rs, $rt"),
589 [(op RC:$rs, RC:$rt)], itin> {
595 class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
596 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>;
599 class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>:
600 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> {
602 let neverHasSideEffects = 1;
605 class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>:
606 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> {
608 let neverHasSideEffects = 1;
611 class EffectiveAddress<bits<6> opc, string instr_asm, RegisterClass RC, Operand Mem> :
612 FMem<opc, (outs RC:$rt), (ins Mem:$addr),
613 instr_asm, [(set RC:$rt, addr:$addr)], IIAlu> {
614 let isCodeGenOnly = 1;
617 // Count Leading Ones/Zeros in Word
618 class CountLeading0<string opstr, RegisterClass RC>:
619 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"),
620 [(set RC:$rd, (ctlz RC:$rs))], IIAlu, FrmR>,
621 Requires<[HasBitCount, HasStdEnc]>;
623 class CountLeading1<string opstr, RegisterClass RC>:
624 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"),
625 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu, FrmR>,
626 Requires<[HasBitCount, HasStdEnc]>;
629 // Sign Extend in Register.
630 class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> :
631 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"),
632 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> {
633 let Predicates = [HasSEInReg, HasStdEnc];
637 class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>:
638 FR<0x1f, func, (outs RC:$rd), (ins RC:$rt),
639 !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> {
642 let Predicates = [HasSwap, HasStdEnc];
643 let neverHasSideEffects = 1;
647 class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass>
648 : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd),
649 "rdhwr\t$rt, $rd", [], IIAlu> {
655 class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
656 FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz),
657 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
658 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> {
663 let Predicates = [HasMips32r2, HasStdEnc];
666 class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
667 FR<0x1f, _funct, (outs RC:$rt),
668 (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src),
669 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
670 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))],
676 let Predicates = [HasMips32r2, HasStdEnc];
677 let Constraints = "$src = $rt";
680 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
681 class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
682 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
683 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
685 multiclass Atomic2Ops32<PatFrag Op> {
686 def #NAME# : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>;
687 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>,
688 Requires<[IsN64, HasStdEnc]> {
689 let DecoderNamespace = "Mips64";
693 // Atomic Compare & Swap.
694 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
695 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
696 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
698 multiclass AtomicCmpSwap32<PatFrag Op> {
699 def #NAME# : AtomicCmpSwap<Op, CPURegs, CPURegs>,
700 Requires<[NotN64, HasStdEnc]>;
701 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>,
702 Requires<[IsN64, HasStdEnc]> {
703 let DecoderNamespace = "Mips64";
707 class LLBase<string opstr, RegisterClass RC, Operand Mem> :
708 InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
709 [], NoItinerary, FrmI> {
710 let DecoderMethod = "DecodeMem";
714 class SCBase<string opstr, RegisterClass RC, Operand Mem> :
715 InstSE<(outs RC:$dst), (ins RC:$rt, Mem:$addr),
716 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
717 let DecoderMethod = "DecodeMem";
719 let Constraints = "$rt = $dst";
722 //===----------------------------------------------------------------------===//
723 // Pseudo instructions
724 //===----------------------------------------------------------------------===//
727 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
728 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
730 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
731 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
732 [(callseq_start timm:$amt)]>;
733 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
734 [(callseq_end timm:$amt1, timm:$amt2)]>;
737 let usesCustomInserter = 1 in {
738 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>;
739 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>;
740 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>;
741 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>;
742 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>;
743 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>;
744 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>;
745 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>;
746 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>;
747 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>;
748 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>;
749 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>;
750 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>;
751 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>;
752 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>;
753 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>;
754 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>;
755 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>;
757 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>;
758 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>;
759 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>;
761 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>;
762 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>;
763 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>;
766 //===----------------------------------------------------------------------===//
767 // Instruction definition
768 //===----------------------------------------------------------------------===//
769 //===----------------------------------------------------------------------===//
770 // MipsI Instructions
771 //===----------------------------------------------------------------------===//
773 /// Arithmetic Instructions (ALU Immediate)
774 def ADDiu : ArithLogicI<"addiu", simm16, CPURegs, immSExt16, add>,
775 ADDI_FM<0x9>, IsAsCheapAsAMove;
776 def ADDi : ArithLogicI<"addi", simm16, CPURegs>, ADDI_FM<0x8>;
777 def SLTi : SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, SLTI_FM<0xa>;
778 def SLTiu : SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, SLTI_FM<0xb>;
779 def ANDi : ArithLogicI<"andi", uimm16, CPURegs, immZExt16, and>, ADDI_FM<0xc>;
780 def ORi : ArithLogicI<"ori", uimm16, CPURegs, immZExt16, or>, ADDI_FM<0xd>;
781 def XORi : ArithLogicI<"xori", uimm16, CPURegs, immZExt16, xor>, ADDI_FM<0xe>;
782 def LUi : LoadUpper<"lui", CPURegs, uimm16>, LUI_FM;
784 /// Arithmetic Instructions (3-Operand, R-Type)
785 def ADDu : ArithLogicR<"addu", CPURegs, 1, IIAlu, add>, ADD_FM<0, 0x21>;
786 def SUBu : ArithLogicR<"subu", CPURegs, 0, IIAlu, sub>, ADD_FM<0, 0x23>;
787 def MUL : ArithLogicR<"mul", CPURegs, 1, IIImul, mul>, ADD_FM<0x1c, 2>;
788 def ADD : ArithLogicR<"add", CPURegs>, ADD_FM<0, 0x20>;
789 def SUB : ArithLogicR<"sub", CPURegs>, ADD_FM<0, 0x22>;
790 def SLT : SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>;
791 def SLTu : SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>;
792 def AND : ArithLogicR<"and", CPURegs, 1, IIAlu, and>, ADD_FM<0, 0x24>;
793 def OR : ArithLogicR<"or", CPURegs, 1, IIAlu, or>, ADD_FM<0, 0x25>;
794 def XOR : ArithLogicR<"xor", CPURegs, 1, IIAlu, xor>, ADD_FM<0, 0x26>;
795 def NOR : LogicNOR<"nor", CPURegs>, ADD_FM<0, 0x27>;
797 /// Shift Instructions
798 def SLL : shift_rotate_imm32<"sll", shl>, SRA_FM<0, 0>;
799 def SRL : shift_rotate_imm32<"srl", srl>, SRA_FM<2, 0>;
800 def SRA : shift_rotate_imm32<"sra", sra>, SRA_FM<3, 0>;
801 def SLLV : shift_rotate_reg<"sllv", shl, CPURegs>, SRLV_FM<4, 0>;
802 def SRLV : shift_rotate_reg<"srlv", srl, CPURegs>, SRLV_FM<6, 0>;
803 def SRAV : shift_rotate_reg<"srav", sra, CPURegs>, SRLV_FM<7, 0>;
805 // Rotate Instructions
806 let Predicates = [HasMips32r2, HasStdEnc] in {
807 def ROTR : shift_rotate_imm32<"rotr", rotr>, SRA_FM<2, 1>;
808 def ROTRV : shift_rotate_reg<"rotrv", rotr, CPURegs>, SRLV_FM<6, 1>;
811 /// Load and Store Instructions
813 defm LB : LoadM<"lb", sextloadi8, CPURegs>, LW_FM<0x20>;
814 defm LBu : LoadM<"lbu", zextloadi8, CPURegs>, LW_FM<0x24>;
815 defm LH : LoadM<"lh", sextloadi16, CPURegs>, LW_FM<0x21>;
816 defm LHu : LoadM<"lhu", zextloadi16, CPURegs>, LW_FM<0x25>;
817 defm LW : LoadM<"lw", load, CPURegs>, LW_FM<0x23>;
818 defm SB : StoreM<"sb", truncstorei8, CPURegs>, LW_FM<0x28>;
819 defm SH : StoreM<"sh", truncstorei16, CPURegs>, LW_FM<0x29>;
820 defm SW : StoreM<"sw", store, CPURegs>, LW_FM<0x2b>;
822 /// load/store left/right
823 defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>;
824 defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>;
825 defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>;
826 defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>;
828 let hasSideEffects = 1 in
829 def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype",
830 [(MipsSync imm:$stype)], NoItinerary, FrmOther>
835 let Inst{10-6} = stype;
839 /// Load-linked, Store-conditional
840 let Predicates = [NotN64, HasStdEnc] in {
841 def LL : LLBase<"ll", CPURegs, mem>, LW_FM<0x30>;
842 def SC : SCBase<"sc", CPURegs, mem>, LW_FM<0x38>;
845 let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
846 def LL_P8 : LLBase<"ll", CPURegs, mem64>, LW_FM<0x30>;
847 def SC_P8 : SCBase<"sc", CPURegs, mem64>, LW_FM<0x38>;
850 /// Jump and Branch Instructions
851 def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>,
852 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
853 def JR : IndirectBranch<CPURegs>, MTLO_FM<8>;
854 def B : UncondBranch<"b">, B_FM;
855 def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>;
856 def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>;
857 def BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>;
858 def BGTZ : CBranchZero<"bgtz", setgt, CPURegs>, BGEZ_FM<7, 0>;
859 def BLEZ : CBranchZero<"blez", setle, CPURegs>, BGEZ_FM<6, 0>;
860 def BLTZ : CBranchZero<"bltz", setlt, CPURegs>, BGEZ_FM<1, 0>;
862 let rt = 0, rs = 0, isBranch = 1, isTerminator = 1, isBarrier = 1,
863 hasDelaySlot = 1, Defs = [RA] in
864 def BAL_BR: FI<0x1, (outs), (ins brtarget:$imm16), "bal\t$imm16", [], IIBranch>;
866 def JAL : JumpLink<"jal">, FJ<3>;
867 def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM;
868 def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>;
869 def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>;
870 def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall;
871 def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall;
873 def RET : RetBase<CPURegs>, MTLO_FM<8>;
875 /// Multiply and Divide Instructions.
876 def MULT : Mult32<0x18, "mult", IIImul>;
877 def MULTu : Mult32<0x19, "multu", IIImul>;
878 def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>;
879 def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>;
881 def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>;
882 def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>;
883 def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>;
884 def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>;
886 /// Sign Ext In Register Instructions.
887 def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10>;
888 def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18>;
891 def CLZ : CountLeading0<"clz", CPURegs>, CLO_FM<0x20>;
892 def CLO : CountLeading1<"clo", CPURegs>, CLO_FM<0x21>;
894 /// Word Swap Bytes Within Halfwords
895 def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>;
898 /// FIXME: NOP should be an alias of "sll $0, $0, 0".
899 def NOP : InstSE<(outs), (ins), "nop", [], IIAlu, FrmJ>, NOP_FM;
901 // FrameIndexes are legalized when they are operands from load/store
902 // instructions. The same not happens for stack address copies, so an
903 // add op with mem ComplexPattern is used and the stack address copy
904 // can be matched. It's similar to Sparc LEA_ADDRi
905 def LEA_ADDiu : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>;
908 def MADD : MArithR<0, "madd", MipsMAdd, 1>;
909 def MADDU : MArithR<1, "maddu", MipsMAddu, 1>;
910 def MSUB : MArithR<4, "msub", MipsMSub>;
911 def MSUBU : MArithR<5, "msubu", MipsMSubu>;
913 def RDHWR : ReadHardware<CPURegs, HWRegs>;
915 def EXT : ExtBase<0, "ext", CPURegs>;
916 def INS : InsBase<4, "ins", CPURegs>;
918 /// Move Control Registers From/To CPU Registers
919 def MFC0_3OP : MFC3OP<0x10, 0, (outs CPURegs:$rt),
920 (ins CPURegs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">;
921 def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegs:$rt, CPURegs:$rd, 0)>;
923 def MTC0_3OP : MFC3OP<0x10, 4, (outs CPURegs:$rd, uimm16:$sel),
924 (ins CPURegs:$rt),"mtc0\t$rt, $rd, $sel">;
925 def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegs:$rd, 0, CPURegs:$rt)>;
927 def MFC2_3OP : MFC3OP<0x12, 0, (outs CPURegs:$rt),
928 (ins CPURegs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">;
929 def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegs:$rt, CPURegs:$rd, 0)>;
931 def MTC2_3OP : MFC3OP<0x12, 4, (outs CPURegs:$rd, uimm16:$sel),
932 (ins CPURegs:$rt),"mtc2\t$rt, $rd, $sel">;
933 def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>;
935 //===----------------------------------------------------------------------===//
936 // Instruction aliases
937 //===----------------------------------------------------------------------===//
938 def : InstAlias<"move $dst,$src", (ADD CPURegs:$dst,CPURegs:$src,ZERO)>;
939 def : InstAlias<"bal $offset", (BGEZAL RA,brtarget:$offset)>;
940 def : InstAlias<"addu $rs,$rt,$imm",
941 (ADDiu CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
942 def : InstAlias<"add $rs,$rt,$imm",
943 (ADDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
944 def : InstAlias<"and $rs,$rt,$imm",
945 (ANDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
946 def : InstAlias<"j $rs", (JR CPURegs:$rs)>;
947 def : InstAlias<"not $rt,$rs", (NOR CPURegs:$rt,CPURegs:$rs,ZERO)>;
948 def : InstAlias<"neg $rt,$rs", (SUB CPURegs:$rt,ZERO,CPURegs:$rs)>;
949 def : InstAlias<"negu $rt,$rs", (SUBu CPURegs:$rt,ZERO,CPURegs:$rs)>;
950 def : InstAlias<"slt $rs,$rt,$imm",
951 (SLTi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
952 def : InstAlias<"xor $rs,$rt,$imm",
953 (XORi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
955 //===----------------------------------------------------------------------===//
956 // Assembler Pseudo Instructions
957 //===----------------------------------------------------------------------===//
959 class LoadImm32< string instr_asm, Operand Od, RegisterClass RC> :
960 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32),
961 !strconcat(instr_asm, "\t$rt, $imm32")> ;
962 def LoadImm32Reg : LoadImm32<"li", shamt,CPURegs>;
964 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterClass RC> :
965 MipsAsmPseudoInst<(outs RC:$rt), (ins MemOpnd:$addr),
966 !strconcat(instr_asm, "\t$rt, $addr")> ;
967 def LoadAddr32Reg : LoadAddress<"la", mem, CPURegs>;
969 class LoadAddressImm<string instr_asm, Operand Od, RegisterClass RC> :
970 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32),
971 !strconcat(instr_asm, "\t$rt, $imm32")> ;
972 def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegs>;
976 //===----------------------------------------------------------------------===//
977 // Arbitrary patterns that map to one or more instructions
978 //===----------------------------------------------------------------------===//
981 def : MipsPat<(i32 immSExt16:$in),
982 (ADDiu ZERO, imm:$in)>;
983 def : MipsPat<(i32 immZExt16:$in),
984 (ORi ZERO, imm:$in)>;
985 def : MipsPat<(i32 immLow16Zero:$in),
986 (LUi (HI16 imm:$in))>;
988 // Arbitrary immediates
989 def : MipsPat<(i32 imm:$imm),
990 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
992 // Carry MipsPatterns
993 def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs),
994 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
995 def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs),
996 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
997 def : MipsPat<(addc CPURegs:$src, immSExt16:$imm),
998 (ADDiu CPURegs:$src, imm:$imm)>;
1001 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1002 (JAL tglobaladdr:$dst)>;
1003 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1004 (JAL texternalsym:$dst)>;
1005 //def : MipsPat<(MipsJmpLink CPURegs:$dst),
1006 // (JALR CPURegs:$dst)>;
1009 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1010 (TAILCALL tglobaladdr:$dst)>;
1011 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1012 (TAILCALL texternalsym:$dst)>;
1014 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1015 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1016 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1017 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1018 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1019 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1021 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1022 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1023 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1024 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1025 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1026 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1028 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
1029 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
1030 def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
1031 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
1032 def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
1033 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
1034 def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
1035 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
1036 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)),
1037 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
1040 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
1041 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
1042 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
1043 (ADDiu CPURegs:$gp, tconstpool:$in)>;
1046 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1047 MipsPat<(MipsWrapper RC:$gp, node:$in),
1048 (ADDiuOp RC:$gp, node:$in)>;
1050 def : WrapperPat<tglobaladdr, ADDiu, CPURegs>;
1051 def : WrapperPat<tconstpool, ADDiu, CPURegs>;
1052 def : WrapperPat<texternalsym, ADDiu, CPURegs>;
1053 def : WrapperPat<tblockaddress, ADDiu, CPURegs>;
1054 def : WrapperPat<tjumptable, ADDiu, CPURegs>;
1055 def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>;
1057 // Mips does not have "not", so we expand our way
1058 def : MipsPat<(not CPURegs:$in),
1059 (NOR CPURegs:$in, ZERO)>;
1062 let Predicates = [NotN64, HasStdEnc] in {
1063 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1064 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1065 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1067 let Predicates = [IsN64, HasStdEnc] in {
1068 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
1069 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
1070 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>;
1074 let Predicates = [NotN64, HasStdEnc] in {
1075 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1077 let Predicates = [IsN64, HasStdEnc] in {
1078 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
1082 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1083 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1084 Instruction SLTiuOp, Register ZEROReg> {
1085 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1086 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1087 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1088 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1090 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1091 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1092 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1093 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1094 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1095 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1096 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1097 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1099 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1100 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1101 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1102 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1104 def : MipsPat<(brcond RC:$cond, bb:$dst),
1105 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1108 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1111 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1112 Instruction SLTuOp, Register ZEROReg> {
1113 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1114 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1115 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1116 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1119 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1120 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1121 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1122 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1123 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1126 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1127 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1128 (SLTOp RC:$rhs, RC:$lhs)>;
1129 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1130 (SLTuOp RC:$rhs, RC:$lhs)>;
1133 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1134 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1135 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1136 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1137 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1140 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1141 Instruction SLTiuOp> {
1142 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1143 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1144 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1145 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1148 defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
1149 defm : SetlePats<CPURegs, SLT, SLTu>;
1150 defm : SetgtPats<CPURegs, SLT, SLTu>;
1151 defm : SetgePats<CPURegs, SLT, SLTu>;
1152 defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
1155 def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
1157 //===----------------------------------------------------------------------===//
1158 // Floating Point Support
1159 //===----------------------------------------------------------------------===//
1161 include "MipsInstrFPU.td"
1162 include "Mips64InstrInfo.td"
1163 include "MipsCondMov.td"
1168 include "Mips16InstrFormats.td"
1169 include "Mips16InstrInfo.td"
1172 include "MipsDSPInstrFormats.td"
1173 include "MipsDSPInstrInfo.td"